Fabrication and Characterization of 4H-SiC MOS Capacitors ...1181142/FULLTEXT01.pdftraditionally in...

Linköping University | Department of Physics, Chemistry and Biology Master’s thesis, 30 hp | Educational Program: Materials Physics and Nanotechnology

Spring term 2016 | LITH-IFM-A-EX—16/3263--SE

Fabrication and Characterization of 4H-SiC MOS Capacitors with Different Dielectric Layer Treatments

Otkur Wutikuer

Examiner: Wei-Xin Ni Supervisor:Chun-Xia Du

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Linköping University Electronic Press

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Abstract

4H-SiC based Metal-Oxide Semiconductor(MOS) capacitors are promising key components for

next generation power devices. For high frequency power applications, however, there is a major

drawback of this type of devices, i.e. they have low inversion channel mobility that consequently

affects the switching operation in MOS Field-Effect Transistors (MOSFETs). Carbon clusters or

excess carbon atoms in the interface between the dielectric layer and SiC is commonly considered

to be the carrier trapping and scattering centers that lower the carrier channel mobility. Based on

the previous work in the research group, a new fabrication process for forming the dielectric layer

with a lower density of the trap states is investigated. The process consists of standard

semiconductor cleaning, pre-treatments, pre-oxidation, plasma enhanced chemical vapor

deposition (PECVD) and post oxidation annealing. I-V measurements of the dielectric strength

showed that the resulting layers can sustain proper working condition under an electric field of at

least 5MV/cm. C-V characteristics measurements provided the evidence that the proposed method

can effectively reduce the interfacial states, which are main culprit for a large flat band voltage

shift of C-V characteristics, in particular under annealing at 900°C in nitrogen atmosphere.

Keywords:

4H-SiC, MOS capacitor, Dielectric layer, PECVD, C-V measurement, Interface states.

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Acknowledgement

First of all, I would like to express my gratitude to Professor Wei-Xin Ni for providing me the

opportunity to learn quite a lot in his interesting research subject. His novel idea, previous research

findings and timely advices form the foundation and guideline for all what I did in the experimental

work. I always felt that my interest in materials science and engineering grew greater every time

when we talked about the thesis project, the semiconductor research and technological trends.

Thank you so much for your precious time and all the efforts spent in my thesis project!

Without the help of my supervisor Dr. Chun-Xia Du, I would not have an easy start in the lab and

good continuation with the experiments. Her expertise in semiconductor device processing and

pleasant way of imparting knowledge as well as readiness for help are very much appreciated, and

I will cherish these experiences with her in Device Processing Lab in future.

I thank Dr. Ren-Xu Jia for doing some test runs of CVD deposition and provision of the SiC

wafers; Thanks to Dr. Ian Booker for teaching me how to carry out the C-V measurements on the

set-up that we have in IFM. Thanks also go to Asaad Al-Jammali who accompanied and assisted

me when measuring several early samples in the beginning of this work.

I pay special thanks to Dr. Hafiz Muhammad Sohail in surface and semiconductor physics group.

He had always been giving me advices, sharing his insights on study and most importantly

encouraging me to seek various kinds of knowledge with balanced devotion. Having a brother like

him makes my journey in Linköping University much brighter.

The master’s study wasn’t always easy, full of ups and downs, just like any other endeavour worth

striving for. My parents and sister all have been unreservedly backing me no matter what decision

I made all the time; my wife has made my life so much more complete and comfortable since we

got married. Without their love and support, it would be impossible to make such progresses

through my master study in Linköping. So, I want to dedicate this thesis to my beloved family

members.

June 2016 in Linköping,

Otkur Wutikuer

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Table of Contents

CHAPTER 1 INTRODUCTION ........................................................................................................ 1

1.1 Basics of MOS Structure ............................................................................................................................... 1

1.2 Silicon Carbide Material Properties .............................................................................................................. 4

1.3 Background and Objectives of This Research ................................................................................................ 9

CHAPTER 2 THEORY AND RESEARCH STRATEGY ....................................................................... 11

2.1 MOS Capacitor Physics ............................................................................................................................... 11 2.1.1 Ideal MOS Capacitor ................................................................................................................................. 11 2.1.2 Non-ideal MOS Capacitor ......................................................................................................................... 18

2.2 Research Strategy ....................................................................................................................................... 22

CHAPTER 3 EXPERIMENTAL DETAILS......................................................................................... 25

3.1 Sample Preparation .................................................................................................................................... 25 3.1.1 Cleaning .................................................................................................................................................... 26 3.1.2 Pre-oxidation ............................................................................................................................................ 26 3.1.3 PECVD Deposition ..................................................................................................................................... 26 3.1.4 Ellipsometry Measurement ...................................................................................................................... 29 3.1.5 Annealing .................................................................................................................................................. 32 3.1.6 Magnetron Sputtering .............................................................................................................................. 33 3.1.7 Summary of treatment procedures for the second round MOS capacitors ............................................. 35

3.2 I-V Measurements ...................................................................................................................................... 37

3.3 C-V Measurements ..................................................................................................................................... 37

CHAPTER 4 RESULTS AND DISCUSSIONS ................................................................................... 39

4.1 I-V Measurements ...................................................................................................................................... 39

4.2 C-V Measurements ..................................................................................................................................... 41

CHAPTER 5 CONCLUSIONS AND SUGGESTIONS ........................................................................ 51

5.1 Conclusions ................................................................................................................................................ 51

5.2 Suggestions for Future Works ..................................................................................................................... 51

REFERENCES................................................................................................................................... 53

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Chapter 1 Introduction

Metal-Oxide-Semiconductor (MOS) structure based devices have been extensively used

traditionally in low power electronic applications. In recent years, with the rapid material

development and advances of the material processing technology, Si-based MOS devices have

stepped into the market of high power electronics, e.g. RF power amplifiers and high frequency

power switchers for higher efficiencies and energy saving. However, the performance and heat

dissipation properties of Si-based power electronic devices are affected by the narrower

bandgap energy (Eg=1.1 eV at room temperature) and low dielectric strength of Si materials,

which therefore limited the device operation to only in the range of moderate voltages and

temperatures. Hence shifting the research and development focus to wide bandgap

semiconductor materials (with the bandgap typically larger than 2-3 eV) is a natural step

forward for eventually fulfilling the higher requirements on the MOS devices.

At present, as one of the most promising wide bandgap materials, Silicon Carbide (SiC) is

attracting much attention of researchers to be a substitute for Si in MOS structures, in particular

MOS field-effect-transistors (MOSFET). MOSFETs are three terminal transistors (i.e. source,

drain, gate terminals, with a substrate body terminal often connected to the source) used

commonly for amplifying and switching in circuits. MOS capacitors, being essentially the core

of MOSFETs (just leaving out the source and drain terminals), are very useful basic devices to

study and develop new MOSFETs. In this thesis project, the focus is on 4H-SiC MOS

capacitors, which were fabricated using different processes, and characterized mainly using C-

V and I-V measurements, in order to gain better understandings needed for the further

development of 4H-SiC MOSFETs.

1.1 Basics of MOS Structure

MOS structure is ubiquitous, simple and important, which can be found in most of the

semiconductor devices. The structure consists of a semiconductor substrate (also referred to as

the body), a metal layer or highly doped polycrystalline Si layer as the top gate, and an oxide

dielectric layer sandwiched in between. These three layers form a parallel plate capacitor as

shown in Figure 1.1, where it also indicates that the gate and body with applied bias VG and VB

are the field modulating and controlling terminals. If a non-oxide insulator is used to separate

Figure 1.1 Schematic of MOS capacitor basic structure.

Introduction

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the gate from the substrate, then this tri-layer structure can be referred to as Metal-Insulator-

Semiconductor or MIS, which is a more generic name for MOS like structures.

The capacitor nature of MOS structures makes them useful and interesting for building more

complicated structures. Although MOS capacitors are different from conventional capacitors,

some basics knowledge of the latter is still relevant to MOS capacitors, which will be essential

for further discussions in following chapters.

The capacitance is a physical quantity typically used to specify the ability of a pair of closely

placed electrical conductors separated by a thin dielectric layer to store charges, while being

biased to have an electric field between the two contacts. From the general sense, these

structures can be called capacitors. The charges on each conductor are of equal amount but of

opposite type. In a parallel plate capacitor, the overlapping areas on the two parallel plates hold

charges symmetrically. For a given bias applied on the capacitor, the larger the capacitance is,

the greater the amount of charges are hold on each plate. The capacitance C can thus be

expressed by Equation (1.1) in the form of the charge/voltage ratio:

𝐶 =𝑄

𝑉 (1.1)

where Q is the amount of charges stored on each plate, and V is the voltage applied to the

two plates. The SI unit for C is Farad, for Q is Coulomb and for V is Volt. The capacitance of

a parallel plate capacitor is determined by the geometry of the structure and dielectric property

of the insulator. In other words, if the area A of the overlapping region, the distance W between

two plates and relative static permittivity or dielectric constant εr of the insulator are known, the

capacitance can then be obtained readily. The formula needed can be derived as follows:

As shown in Figure 1.2 adapted after [1], the upper plate and the lower plate are charged

with +Q and –Q respectively under a bias V across them. The quasi-uniform electric field

formed between the two plates is E, which is expressed by Equation (1.2):

𝐸 =𝑉

𝑊 (1.2)

=

=

Plate area = A Charge on plate =Q

Figure 1.2 Side view drawing of a parallel plate capacitor.

1.1 Basics of MOS Structure

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For the ease of consideration, it is better to first choose a closed Gaussian surface that takes

a shape of cuboid with a length the same as the plates (which in turn is much larger in magnitude

than the plate distance W), and its upper surface contained inside the upper plate, lower surface

located in the dielectric media. The charges Q on the upper plate is enclosed within the cuboid.

According to the Gauss’s law, electric flux ΦE through the Gaussian surface here is:

𝛷𝐸 =∯𝐸 ∙ 𝑑𝐴𝑆

=𝑄

𝜀=𝜎 ⋅ 𝐴

𝜀 (1.3)

where is area charge density, and ε is electric permittivity of the dielectric, which is equal

to εrε0 (ε0 is the electric constant or the permittivity of vacuum). Actually, the surface integration

of the electric field above is just E⋅A. Therefore, from equation (1.3) one can get:

𝐸 =𝜎

𝜀𝑟𝜀0=

𝑉

𝑊 (1.4)

By combining equation (1.1) and (1.4), one gets the formula of capacitance as:

𝐶 = 𝜀𝑟𝜀0𝐴

𝑊 (1.5)

For a MOS capacitor, the capacitance changes with an applied voltage, which will be

discussed later, but equation (1.5) can still be used to calculate the capacitance components

therein. Capacitance components can be treated as capacitors connected to each other in parallel

or in series. The equations for the equivalent total capacitance C of the whole connected

structure, in which components have capacitance C1 and C2 respectively, are listed as follows

(Figure 1.3 is adapted after reference [2], from which the more detailed derivation can be found

also):

When the two capacitors are connected in parallel:

CC1

C2

(a)

C

C1 C2

(b)

Figure 1.3 Capacitors with capacitance C1 and C2 connected: (a) in parallel and (b) in series. C is the

equivalent total capacitance of the blue rectangle enclosed circuit parts.

Introduction

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𝐶 = 𝐶1 + 𝐶2 (1.6)

and when they are connected in series:

𝐶 =𝐶1𝐶2

𝐶1 + 𝐶2 (1.7)

For any more complicated way of connecting more than two capacitors, the capacitance can

be calculated just by properly using equation (1.6) and equation (1.7), repeatedly. This indeed

is very useful for determining the total capacitance of a MOS structure appearing to the outside

circuit or measurement.

1.2 Silicon Carbide Material Properties

Many crystals, including SiC, can exist in more than one crystalline structure for a single

chemical composition, which is called polymorphism. Specifically, for SiC crystals

specifically, it can be called polytypism. As reported in reference [3], SiC has more than 250

polytypes. All of those different crystalline structures have a basic building block-a tetrahedron,

with one carbon atom at the center, bonded by four silicon atoms at the vertices of the

tetrahedron, due to sp3 hybridization of valence electrons in C and Si, respectively. The other

way, i.e. with silicon as the central atom and carbon atoms at four vertices, is equivalent for

building up the crystalline structures. The latter tetrahedron is demonstrated in Figure 1.4. A

zinc-blende structured SiC crystal has a regular tetrahedron unit building block, in which the

nearest distance between two C atoms is around 3.08Å, and the nearest distance between a Si

atom and a C atom is around 1.89Å, while the angle between two adjacent Si-C bonds is around

109.5°. This holds for true for all other polytypes, i.e. the distance between nearest Si and C

atoms remains approximately 3.08 Å, but the other parameters may differ from a polytype to

another[4].

Figure 1.4 One of two equivalent SiC tetrahedron structures.


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All the closed-packed SiC are constructed in the same manner, i.e. same structured two-

dimensional Si-C bi-layer forms a stacking unit, which has three possible spatial locations

denoted as A, B and C, as shown in Figure 1.5 (note that each sphere represents a Si-C pair);

along the growth direction, the bi-layers stack in various sequences (e.g. ABCABC, ABAB),

resulting in different polytypes. Each polytype has its repeating unit that consists of two or more

stacking layers. Therefore, the polytypes can be distinguished from one to another by

identifying the repetition unit. Ramsdell’s notation is a commonly used designation method for

the closed-packed crystalline structures for this purpose, in which a number is used to specify

the number of stacking layers constitute a repetition unit, and a letter following the number

denotes the geometric structure, where C, H and R represents cubic, hexagonal and

rhombohedral. The polytypes denoted by 3C, 2H, 4H and 6H, as shown in Figure 1.6, are the

most encountered SiC materials in researches.

Top view of three possible positions relative to hexagonal configuration that a single Si-C bi-layer can occupy

( a )

Position A Si-C Atoms

Position B Si-C Atoms

Position C Si-C Atoms

Direction Of Side View

A

B

C

Figure 1.5 Top view of three possible positions relative to hexagonal configuration that a single Si-C

bi-layer can occupy. Direction shown here refers to side view in Figure 1.6.

Introduction

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Figure 1.6 Side view of four SiC polytypes with different stacking sequences: (a)

3C-SiC, (b) 2H-SiC, (c) 4H-SiC and (d) 6H-SiC.


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Various semiconductor power devices need to be operated at high temperature, high

frequency or high voltage conditions. SiC as a base material of choice has shown great

advantages compared to Si and other more conventionally used semiconductors. The better

performance of SiC can be ascribed to its wide energy bandgap (e.g. 4H- and 6H SiC have

bandgaps about three times larger than that of Si), high thermal conductivity, high electron

saturation velocity, and high breakdown field. Some critical electrical properties of Si, three

kinds of SiC polytypes and GaN are summarized in Table 1.1 for comparison.

Table 1.1 Basic electrical properties of Si and some wide bandgap semiconductors[5], [6].

Property Si 3C-SiC 4H-SiC 6H-SiC GaN

Bandgap (eV) at 300K 1.12 2.39 3.26 3.03 3.45

Dielectric Constant 11.9 9.7 9.66-10.1 9.66 9

Electric Breakdown Field

(kV/cm) 300 2120 2200 2500 2000

Electron Mobility

(cm2/V⋅s) 1500 1000 1000

500

80 1250

Thermal Conductivity

(W/cm⋅K) 1.5 4.9 4.9 4.9 1.3

Saturated Electron Drift

(×107cm/s) 1 2.5 2 2 2.2

To have a better understanding of the significance of the above listed properties of

semiconductors, especially in the realm of power devices fabrication, some theoretical analyses

are useful. R.W. Keyes presented a figure of merit (KFOM), which characterize materials in

terms of limitations imposed by thermal properties for high-speed switches[7]. The KFOM

equation (1.8) shows that for devices require a higher switching speed, materials with higher

thermal conductivity λ, higher saturation drift velocity vs, and lower dielectric constant ε are

then preferable.

B. J. Baliga derived the Baliga figure of merit (BFOM), which defines a parameter of

semiconductor material to evaluate the power losses in lower frequencies power FETs.

Moreover, Baliga high-frequency figure of merit (BHFFOM) can also serve the same purpose

for high frequencies switching devices[8]. Using the BFOM equation (1.9) and BHFFOM

equation (1.10), one can get a general guideline to choose a proper material for two kinds of

application. For low frequency operations, higher dielectric constant ε, higher electron mobility

μ and higher bandgap EG are desirable; while for high frequency operations, higher electron

mobility and higher critical electric field for breakdown EC are desirable (VG is gate drive

voltage, and VB is breakdown voltage, which can ultimately be taken into account by just

considering EC).

Introduction

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𝐾𝐹𝑂𝑀 = 𝜆 [𝑐 ⋅ 𝑣𝑠4𝜋𝜀

]

12 (1.8)

𝐵𝐹𝑂𝑀 = 𝜀 ⋅ 𝜇 ⋅ 𝐸𝐺3 (1.9)

𝐵𝐻𝐹𝐹𝑂𝑀 = 𝜇 ⋅ 𝐸𝐶2 ⋅

𝑉𝐺0.5

2𝑉𝐵1.5 (1.10)

According to the considerations based on reports in [9] and [10], 4H-SiC and GaN are

currently the best materials to choose among the potentially viable semiconductors choices for

unipolar high-power and high-frequency devices. Despite the excellent theoretical material

advantages, however, GaN has a key issue - there is no large enough GaN substrates available

for growth of homo-epitaxial GaN, which can be an economical limit for commercial

applications[11]. That is the reason for many researchers to choose in favor of 4H-SiC for the

development of high power and /or high frequency devices rather than GaN. The normalized

KFOM, BFOM and BHFFOM for Si, 3C-,4H-, 6H-SiC and GaN are summarized in Table 1.2

for comparison.

Table 1.2 Comparison of normalized figure of merits of Si and some wide bandgap semiconductors for

unipolar high-power and high-frequency devices. Excerpted from related tables in [9] and [10].

Property Si 3C-SiC 4H-SiC 6H-SiC GaN

KFOM 1 5.8 5.1 5.1 1.8

BFOM 1 40 290 90 910

BHFFOM 1 12 34 13 100

Two advantages of SiC materials worth mentioning are that they are the only semiconductor

material other than Si whose native oxide is SiO2 (an oxide with excellent dielectric properties)

[12], and they can be processed using fabrication technology similar to that of Si, only with

much higher temperature settings. This means for the research and development, the condition

for transition from Si based MOS to SiC based MOS in whole range of power electronics are

much more mature than other possible materials.

1.3 Background and Objectives of This Research

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1.3 Background and Objectives of This Research

Although SiO2 can be natively oxidized from SiC, the interface between SiO2 and SiC tends to

be less ideal than that between Si and SiO2. Interface defects like carrier traps and scattering

centers formed during the oxidation processes can largely deteriorate the channel electron

mobility, threshold voltage, leakage current, and hence the overall performance of SiC MOS

device’s [13].

The defects are normally referred to as interface states, and the high interface state density

Dit of SiC/SiO2 near the conduction band edge (about 1013 cm-2, almost 3 orders of magnitude

higher than Dit of Si/SiO2 [14]) is accountable for the channel mobility lowering in 4H-SiC

MOS devices by means of carrier trapping and de-trapping, field termination and Coulomb

scattering. R. Schörner et al.[15] pointed out that although for 6H-SiC and 15R-SiC, the large

Dit also appears at about 2.8-3.0 eV above the valence band edge, interface states have much

less effects on channel mobility than that in 4H-SiC. Due to the fact that EG of 6H-SiC is around

3.03 eV, they postulated that the distribution of large Dit is well situated above the conduction

band edge, and the interface states will be resonant with the energy states in the band at room

temperature or above, thus having a less effect on channel electrons. 6H-SiC and 15R-SiC have

however other well-known problems that restrict their applications in MOS devices, e.g. 6H-

SiC have anisotropic electron bulk mobility and 15R-SiC is not yet commercially available in

large scale[16].

Therefore, currently the 4H-SiC is considered as the best candidate for the research and

development of aforementioned device, with the challenge remaining huge for boosting the

channel electron mobility. Many attempts have been made in the past years in various

researches on 4H-SiC MOS structures to understand the mechanism of forming high interface

state density and its effect on lowering channel electron mobility, as well as the treatment

methods of the gate dielectric layer to improve the parameters.

V. Afanasev et al. proposed in [13] that carbon clusters formed at the SiC/SiO2 interface and

near interfacial oxide defects states are the main contributors to the interface states, whereas the

dangling bond defects and dopant-related defects are neglectable. K.-C. Chang et al. [17]

attributed the reduction of inversion channel mobility to the scattering caused by the excess

interfacial C atoms and rough SiC/SiO2 interface. They also managed to increase the channel

mobility after NO annealing, and suggested that the improvement may be related to the

reduction of the excess C atoms or introduction of interfacial nitrogen. T. Zheleva et al.

observed by experiments in [18] that the oxidation process highly disorders the top few layers

of SiC and produces an interfacial transition layer with a thickness of several nanometers

extending into both sides of SiC/SiO2 interface, in which ternary SiOxCy phases may be formed.

T. Biggerstaff et al. showed in [19] that the thickness of an interfacial transition layer with a

carbon to silicon ratio larger than 1 is inversely related to the effective channel mobility. J.

Taillon et al. [20] systematically characterized the transition layer and suggested that Si-C and

Si-O bonds coexist in the transition layer. There is a nonlinear inverse relationship between NO

annealing time and transition layer thickness, which is in turn inversely correlated to the

effective channel mobility as mentioned above. Furthermore, they did not notice any excess C

in the interface. A. Beltrán el al [21] verified this by using an atomic scale characterization

technique Atom Probe Tomography and High resolution transmission electron microscopy

coupled with spatially resolved Electron Energy Loss Spectroscopy. The analyses did not find

the evidence of any excess carbon or clusters between SiC and SiO2. Therefore, they proposed

that the interface roughness could play a greater role than excess C in reducing the channel

mobility.

Although these research efforts attempted for the understandings of 4H-SiC MOS structures

and the issue regarding the reduction of the channel mobility, the detailed theory, explanation

Introduction

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and clear conclusions are not yet completely established. This project work is thus another try

in this interesting field, with the following objectives to achieve:

• Discussing the origin of the high density of interface states, low channel electron

mobility, and the possible physical and chemical mechanisms therein.

• Exploring a novel processing method in fabricating 4H-SiC MOS structures for

efficient power electronics.

• Characterizing the fabricated MOS capacitors to verify the effectiveness of the

method and to find the possible directions of the improvement for further research.

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Chapter 2 Theory and Research Strategy

MOS capacitors, as mentioned in Chapter 1, have some unique properties compared to

conventional capacitors. These properties are strongly related to the structure and quality of the

semiconductor and dielectric layer. It is of great value to study these correlations, in order to

improve the overall performance of the device. Capacitance vs. Voltage (C-V) measurement is

a very useful and essential technique for MOS characterizations. Therefore, in this chapter some

details in physics will be introduced to understand the C-V characteristics of MOS capacitors

and the underlying mechanisms for its variation under non-ideal conditions. With the necessary

theoretical background provided, the second part of this chapter will elaborate on the research

strategy of this project based on understandings of the physics and chemistry involved during

the fabrication of 4H-SiC MOS structures.

2.1 MOS Capacitor Physics

2.1.1 Ideal MOS Capacitor

The capacitance of a MOS capacitor is not a constant. When varying applied voltage across the

MOS structure, the capacitance values are varied, which is different from a traditional double-

layer capacitor having only a constant capacitance regardless of the applied voltage. The

measured capacitance data are plotted as a function of voltage, and the characteristics of the

resulting C-V profile are indeed a capable diagnostic tool for determining parameters of MOS

structures, evaluating and modifying the manufacturing processes, and analyzing the possible

degradation mechanisms, in comparison to the ideal MOS structure.

Figure 2.1 Example of typical C-V measurements at high and low frequency, respectively.

Theory and Research Strategy

Page | 12

The relationship between the capacitance of an ideal MOS capacitor and applied voltage on

it can be typically divided into three regimes: accumulation region, depletion region and

inversion region. Typical C-V curves measured from a p-type MOS capacitor at a high and a

low frequency are shown in Figure 2.1. With the bias scanned from the negative voltage region,

the variation of capacitance under different voltage conditions is clearly revealed. For any n-

type MOS capacitor, the principles still hold true, and one can simply flip the p-type MOS C-

V characteristics curve symmetrically about the zero-voltage line to have a general picture of

n-type MOS C-V curve too. The sign of bias or gate voltage is chosen to be positive when the

electric potential is higher on the metal gate side and negative when it is higher on the

semiconductor body side. It deserves to be mentioned that the discussion of the physics of MOS

capacitor and some figures in this chapter are inspired and supported by R. Pierret’s classic

book [22] with necessary adaptations according to the needs and scope of this paper.

First, when the p-type MOS capacitor is biased with a relatively large negative direct current

(D.C.) gate voltage, the C-V characteristics are measured in the accumulation region

(corresponding to the left part of Figure 2.1), i.e. majority carrier holes in semiconductor

accumulate at a thin layer next to the oxide-semiconductor interface due to the coulomb force

experienced under the applied electric field (similarly, for the n-type semiconductor, the

accumulation region lies in the positive gate voltage side in the C-V curve). Meanwhile, the

same amount of carriers with opposite charge accumulate at the gate side. The charge

distribution in the capacitor is schematically shown in Figure 2.2 (a). Under D.C. bias, there is

no measurable current for charge Q across the oxide insulator, thus for measuring the

capacitance under certain gate voltage, one can use C=ΔQ/ΔV. To do this, a small alternating

current (A.C.) signal needs to be added on top of the D.C current, and then both ΔQ and ΔV are

measurable. The approximate charge distribution under D.C and A.C bias in metal and

semiconductor can be clearly visualized by a block charge diagram, as shown in Figure 2.2 (b).

The effect of the bias applied across the MOS capacitor on the energy band is shown in Figure

2.2 (c). The Fermi energy level in metal and semiconductor is separated by the applied bias V,

and the magnitude of the separation is determined by Equation (2.1) [22]:

𝐸𝐹(𝑀𝑒𝑡𝑎𝑙) − 𝐸𝐹(𝑆𝑒𝑚𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑜𝑟) = −𝑞𝑉 (2.1)

where q is the magnitude of electronic charge (1.6×10-19 C). When the applied voltage is

negative, the Fermi energy level of metal is raised relative to that of semiconductor.


Page | 13

Since majority carriers move in high speed (equilibrate typically within 10-10 -10 -13 seconds

at the probing frequency of 1MHz [22]), the variation of charges is instantaneous in the thin

accumulation layer in response to both D.C. ramping and superimposed A.C. modulation signal.

This implies that the capacitance of the MOS capacitor in this condition is essentially of a

parallel plate capacitor with an oxide layer as dielectric (CO), regardless of the probing A.C

signal frequencies. The total capacitance CAcc of the MOS capacitor is:

𝐶𝐴𝑐𝑐 ≅ 𝐶𝑂 = 𝜀𝑟(𝑂)𝜀0𝐴

𝑊𝑂 (2.2)

here εr(O) is specifically the dielectric constant of the oxide layer, and WO is the width of the

oxide layer. The equivalent circuit model of the MOS capacitor as a whole in accumulation

region is shown in Figure 2.2 (d).

With the increase of D.C bias, the capacitance basically remains stable around the value of

Co. When the total effective bias increases to the zero point, the ideal MOS capacitor is under

Flat-band condition as shown in Figure 2.3. The name comes from the fact that no band bending

occurs under this condition in the MOS device, and all the bands become flat from metal to the

bulk of semiconductor. There is no static charge on both sides of the oxide and the total

capacitance C remains at the value of CO.

Figure 2.2 Accumulation condition diagrams of an ideal p-type MOS capacitor. (a) MOS capacitor

with positive charge on semiconductor-oxide interface. (b) Block charge diagram. (c) Energy band

diagram. (d) Equivalent circuit model.


Page | 14

After the bias passes through the Flat-band voltage and becomes positive, major change

happens with the onset of depletion of majority carriers of semiconductor within the area in

close proximity to the oxide. The total capacitance C thus starts to decrease and the C-V

characteristics curve continues into the depletion region (corresponding to the central part of

Figure 2.1). The driving force of the depletion of majority carriers is still coulomb force. The

dopants, i.e. acceptors near the interface, lose majority carrier holes by filling holes with

incoming electrons from the semiconductor bulk, and hence are negatively charged as

illustrated in Figure 2.4 (a) (whereas in n-type MOS, donor atoms are stripped of electrons and

left as positive ions). This part of the semiconductor with charged dopants and depleted of

majority carriers are called the depletion layer. When the bias changes to a certain D.C. voltage

V in the depletion region, the depletion layer will expand or contract to a corresponding width

WS to provide an equal amount of charges to balance the gate charge. Here and in most of the

practical calculations, the depletion layer is simply approximated as having clear and flat

boundary with both oxide layer and unaffected bulk. The additional A.C. signal will vary the

width WS by a small fluctuating ΔWS to provide the additional ΔQ as shown in Figure 2.4 (b).

The Fermi energy in metal will then be lowered than that in the semiconductors. Notice from

Figure 2.4 (c), in the depletion layer, the energy position of the conduction band edge and

valence band edge move downward while the Fermi energy level always stays at the same

energy as in the unaffected semiconductor bulk, making this area less p-type like.

Figure 2.3 Flat-band condition diagrams of an ideal p-type MOS capacitor. (a) MOS capacitor

without charge. (b) Block charge diagram. (c) Energy band diagram. (d) Equivalent circuit model.


Page | 15

Just like in the accumulation region, the applied electric field drives/depletes majority

carriers in a rapid manner under D.C. ramping, and under both the high and low frequency of

A.C. signals, so much so that the fast altering of depletion width can be treated quasi-statically

in connection with the bias change. This observation is very helpful for deriving the equivalent

capacitance of the whole MOS capacitor. Apart from the oxide capacitance component, there

is a semiconductor capacitance component CS resulting from the charges stored within WS. The

voltage drop from metal to semiconductor is hence equal to the voltage drop on the “oxide

capacitor” part and voltage drop on the “semiconductor capacitor” part. The total capacitance

CDep can thus be calculated as the capacitance of the circuit, in which CO and CS are connected

in series as seen in Figure 2.4 (d). Cs can be obtained by treating it as a parallel plate capacitor

with the semiconductor as the dielectric media, of which the dielectric constant is εr(S). The CDep

can then be calculated using Equation (2.3):

𝐶𝐷𝑒𝑝 =𝐶𝑂𝐶𝑆

𝐶𝑂 + 𝐶𝑆=

𝐶𝑂

1 +𝐶𝑂𝐶𝑆

=𝐶𝑂

1 +𝜀𝑟(𝑂)𝜀0

𝐴𝑊𝑂

𝜀𝑟(𝑆)𝜀0𝐴𝑊𝑆

=𝐶𝑂

1 +𝜀𝑟(𝑂)𝑊𝑆

𝜀𝑟(𝑆)𝑊𝑂

(2.3)

It is noticed from this equation that with an increase of WS, the CDep decreases. This is exactly

what can be observed when the applied bias increasingly depletes the charges in semiconductor.

Figure 2.4 Depletion condition diagrams of an ideal p-type MOS capacitor. (a) MOS capacitor with

negative charge on semiconductor-oxide interface and depletion layer. (b) Block charge diagram.

(c) Energy band diagram. (d) Equivalent circuit model.


Page | 16

When the bias continues to increase, the minority carriers start to be generated through the

electron-hole pair generation mechanism. The minority carriers pile up near the semiconductor-

oxide interface while the majority carriers drift out of the depleted area. Once the minority

carrier concentration exceeds the majority carrier concentration of the bulk semiconductor, the

MOS capacitor starts to work under the inversion mode (the surface depleted region inverted

from p- to n-type, or n- to p-type). Under the inversion condition, the depletion layer’s width

continues to expand until the piled-up minority carrier forms an opposite field strong enough to

cancel the field caused by the applied gate bias. The maximum width of the depletion layer is

WS(Max). From this point on, there are two possible variations of the C-V curve depending on

the frequency of the C-V measurement signal.

If the signal frequency is low enough, there is enough time for electron-hole pairs to generate

and annihilate in the inversion layer in response to the signal. The total capacitance is then

equivalent to that in the accumulation condition, which is equal to CO. The C-V curve thus

assumes the shape as shown in Figure 2.1 top right part (labeled as “Low-frequency”).

From Figure 2.5, one can notice the band bending is even greater, and the Fermi energy

inside the inversion layer is above the intrinsic Fermi level (near the mid-bandgap), showing an

n-type like characteristic.

If the signal frequency is very high while electron-hole pair generation and annihilation

process is slow, the fluctuating ΔQ will be supplied by changing the depletion width a tiny

amount of ΔW instead. Then the equivalent circuit model is again like the one in the depletion

region, i.e. an CO connected to CS in series. In this case, the total capacitance of a MOS capacitor

Figure 2.5 Inversion condition diagrams of an ideal p-type MOS capacitor under low measurement

frequency. (a) MOS capacitor with negative charge on semiconductor-oxide interface and inversion

layer. (b) Block charge diagram. (c) Energy band diagram. (d) Equivalent circuit model.


Page | 17

will continue from the lowest depletion capacitance value and level out (as shown in Figure 2.1

bottom right part labeled as “High-frequency”). The equation (2.4) shows that the actual

inversion region capacitance in high frequency measurement is determined by the maximum

depletion width WS(Max).

𝐶𝐼𝑛𝑣(𝐻𝑖𝑔ℎ 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦) =

𝐶𝑂𝐶𝑆𝐶𝑂 + 𝐶𝑆

=𝐶𝑂

1 +𝐶𝑂𝐶𝑆

=𝐶𝑂

1 +𝜀𝑟(𝑂)𝑊𝑆(𝑀𝑎𝑥)


(2.4)

The Block charge diagram in Figure 2.6 (b) shows that the WS(Max) does not increase with

the increase of D.C. bias. This means the majority of the minority carriers in semiconductor

side to balance the opposite charges in metal side comes from the electron-hole generation

process, while only ΔQ part comes from contribution of the fluctuating width ΔW. This directly

relates to another possible circumstance, i.e., if the D.C. ramping rate is too high, the generation

rate is not high enough to supply the needed amount of minority carriers, then the deficit of

minority carriers must be supplied by the increase of the depletion layer depth over the

equilibrium WS(Max). This non-equilibrium condition is known as deep depletion. From equation

(2.4) it is evident that the CInv will decrease with the increase of WS, which means the C-V curve

will continuously go down at the inversion region.

Figure 2.6 Inversion condition diagrams of an ideal p-type MOS capacitor under high measurement

frequency. (a) MOS capacitor with negative charge on semiconductor-oxide interface and inversion

layer. (b) Block charge diagram. (c) Energy band diagram. (d) Equivalent circuit model.


Page | 18

2.1.2 Non-ideal MOS Capacitor

The C-V characteristics measured in real MOS capacitors are always deviated from above

described ideal situations. Although there are many possible reasons for the deviations, the

following five causes are most frequently encountered, leading to much more significant effects

than others. In other words, if these causes are studied in detail and taken care of, the

manufactured MOS devices can perform in rather good conformity with what can be predicted

by the ideal case.

For the convenience of reading, Figure 2.7 illustrates the relative positions of the charge

centers inside oxide and around oxide-semiconductor interface, which are in connection to the

causes (2) - (5) to shift the measured C-V curves.

(1) Work function difference between metal and semiconductor. The work function Φ, i.e.

the difference between the vacuum level and Fermi energy level, of isolated metal and

semiconductor are assumed to be equal in ideal MOS capacitor analysis. This implies that when

bringing together metal, insulator and semiconductor, their Fermi energy level must be in

alignment (ΦM= ΦS). However, this is the seldom case in real devices. The work function

difference between the two materials, ΦM- ΦS, will introduce a built-in potential VBI, which can

be calculated by Equation (2.5)[22]:

𝑉𝐵𝐼 =1

𝑞(𝛷𝑀 − 𝛷𝑆) =

1

𝑞(𝛷𝑀

′ − 𝜒′ − (𝐸𝐶 − 𝐸𝐹)𝐹𝐵) (2.5)

where Φ’M and χ’ are the effective surface barriers of metal and semiconductor. The effect of

the VBI is to shift the measured C-V curves of a real MOS capacitor along the voltage axis an

amount of ΔVG=VBI. The Vbi is usually a negative quantity with the common doping level in

practice, and the value is rather small with a magnitude of one volt or even less.

(2) Mobile ion charges. As shown in Figure 2.7, during different processing, handling and

testing stages, positive ions like Na+, K+ and sometimes H+ [23] are often incorporated in the

dielectric oxide of a MOS structure. They cause a shift of ΔVG(MI) [22] towards the negative

bias side of the C-V curve, which can be calculated using Equation (2.6):

Figure 2.7 Four kinds of oxide layer related charges. Adapted after [22].


Page | 19

𝛥𝑉𝐺(𝑀𝐼) = −1

𝜀𝑂𝜀0∫ 𝑥𝜌𝑖𝑜𝑛(𝑥)𝑑𝑥𝑥𝑜

0

(2.6)

where εO is the dielectric constant of oxide, and ρion is the ionic charge distribution. The

integration is made from the metal-oxide interface (set as 0 position) to the oxide-semiconductor

interface (position noted as xO). ρion through Equation (2.7) gives the total ionic charge inside

oxide layer per unit area[22]:

𝑄𝑀 = ∫ 𝜌𝑖𝑜𝑛(𝑥)𝑑𝑥𝑥𝑜

0

(2.7)

Equation (2.6) tells the shift of C-V curve ΔVG(MI) is also towards negative direction of

voltage axis if the mobile ions are positive, which is normally the most probable case.

As those ionic contaminants are very mobile in the oxide, the amount of voltage shifts

calculated using the above equations varies in various practical cases, thus resulting in the

instability during operation.

(3) Fixed charges at the oxide-semiconductor interface. Compared with the previous case,

this type of charges, to a large extend, are fixed in position in oxide very close to the oxide-

semiconductor interface. After some extensive studies in the past, the fixed positive charges are

postulated as ionic vacancies of silicon inside the oxidation front, which have not been oxidized

after ionization due to an abrupt stop of the oxidation process [23]. Similar to mobile ions, the

shift of C-V curve ΔVG(F) caused by fixed charges compared to ideal characteristics is also

towards the negative bias. Equation (2.8) is derived in [22] with a similar approach as ΔVG(MI),

but because of the fixed charge distribution ρf = QF δ(xO) , where QF is total fixed charges within

the oxide layer and δ(xO) is a delta-function, the resulting form is quite simplified.

𝛥𝑉𝐺(𝐹) = −𝑄𝐹𝐶𝑂

(2.8)

where CO is the capacitance of oxide capacitor per unit area of gate.


Page | 20

(4) Interface trapped charges. This type of non-ideality is the most complex one in term of

the C-V curve shifting effect and degrading effect. Interface states are distributed at different

energy levels throughout the band gap, and localized in position in relation to EC and EV at the

interface, as shown in Figure 2.8.

The causes of interface traps can be the structural defects like dangling bonds formed at the

surface of semiconductor[22], but also the metal impurities or other bond breaking

processes[23]. The allowed states above the mid-gap level are acceptor-like, while the ones

below the mid-gap are donor-like[24]. It thus means after band bending if the Fermi level (the

level above which almost all states are empty and below which almost all states are filled) is

higher than Ei at the interface, then the net interface trapped charges QIT will be negative; if it

is lower than Ei, then QIT will be positive; and if it is located near Ei, the QIT will be around

zero. The shift of ΔVG(IT) in a C-V curve caused by the interface trapped charges is given by

Equation (2.9). Notice here the QIT is a function of the bias, i.e. the MOS capacitor can be

charged or discharged with variation of the energy band bending in semiconductor (i.e. is a

function of the potential difference between bulk and surface ϕS). The effect of interface trapped

charges is to spread out the C-V curves as shown in Figure 2.9[22].

𝛥𝑉𝐺(𝐼𝑇) = −𝑄𝐼𝑇(𝜙𝑆)

𝐶𝑂 (2.9)

Figure 2.8 Allowed interfacial states (a) and interface trapped charges in: (b) inversion, (c) depletion

and (d) accumulation conditions. Adapted after [23].

Page | 21

(5) Oxide trapped charges. This type of charges can be introduced by ionizing radiation, ion

implantation, or other processes that can generate electrons and holes. After generation of

charges, defects near the site of charge generation or deep-level traps near the oxide-

semiconductor interface can trap them in the oxide bulk. Fortunately, oxide trapped charges can

be reduced by low-temperature annealing.

The total effect of the above introduced non-idealities on the measured C-V curves is

summarized in Equation (2.10) by giving the shift ΔVG between two equal capacitance points

(with the same level of band bending) on real and ideal C-V curves [22]:

𝛥𝑉𝐺 = 𝑉𝐵𝐼 −𝑄𝑀𝛾𝑀𝐶𝑂

−𝑄𝐹𝐶𝑂

−𝑄𝐼𝑇(𝜙𝑆)

𝐶𝑂 (2.10)

where γM is a dimensionless quantity given by Equation (2.11):

𝛾𝑀 =∫ 𝑥𝜌𝑖𝑜𝑛(𝑥)𝑑𝑥𝑥𝑜0

𝑥 ∫ 𝜌𝑖𝑜𝑛(𝑥)𝑑𝑥𝑥𝑜0

(2.11)

Figure 2.9 Example of spread out distortion (green curve) of ideal C-V curve (blue curve) caused by

interfacial traps.


Page | 22

2.2 Research Strategy

The theoretical introduction in subchapter 2.1 serves mainly one purpose: to explore the

common underlying basic mechanism that affect the C-V characteristics in real MOS devices,

in comparison to the ideal MOS structure with the same material and configurations, in order

to find the way for further improvement of device fabrication. It is better understood that:

1) The small built-in potential due to the work function difference between gate and

semiconductor materials can be easily engineered to a desired value by choosing the

proper material and dopant concentration, which is hence not the focus of this project.

The chosen gate material and semiconductor material are Al and 4H-SiC.

2) Mobile ion charges, fixed charges at interface and oxide trapped charges are strongly

related to certain fabrication processes, techniques and environment. The state of the art

industrial production technologies had already addressed these issues very well. But

when it comes to the interfacial trapped charges in 4H-SiC MOS structures, not so many

progresses have been made during the last two decades. Therefore, the research focus

here will be on the reduction of interfacial trapped charges.

As mentioned in the first chapter, previous theoretical and experimental studies through the

years have narrowed down the focus to three main areas that probably affect most for interface

states caused channel mobility degradation: oxidation process related excess carbon/carbon

clusters functioning as carrier traps and scattering centers; rough interface and oxidation

induced surface disordering, both of which causing strong carrier scattering; relation between

annealing condition and reduction of interfacial transition layer thickness, which is reported to

be inversely correlated to the carrier channel mobility.

This project is a part of and based on the research work led by W.X. Ni at Linköping

University. The unique approach here is a novel combination of pre-oxidation processes, plasma

enhanced chemical vapor deposition (PECVD) of oxide instead of conventional thermal

oxidations, as well as post oxidation annealing, which will be stated after the recognition of

serious negative effects in the conventional oxidation process.

Ni proposed that the presence of the excess carbon molecules or carbon clusters at the

interface is a bi-product of conventional thermal oxidation of SiC. The general reaction for

producing SiO2 is described in Equation (2.12) , which is actually a combination of two

competing reaction processes, as in Equation (2.13) and Equation (2.14) [25]:

2𝑆𝑖𝐶 + 4𝑂2 = 2𝑆𝑖𝑂2 ↓ +2𝐶𝑂2 ↑ (2.12)

2𝑆𝑖 + 2𝑂2 = (2 − 𝑥)𝑆𝑖𝑂2 ↓ +𝑥(𝑆𝑖+⋯) (2.13)

2𝐶 + 2𝑂2 = (2 − 𝑦)𝐶𝑂2 ↑ +𝑦(𝐶𝑛⋯) (2.14)

Even though the reaction for SiO2 production is slightly preferable in unrestricted situations,

at the beginning the two reactions are both active at the surface. However, the formation of a

thicker SiO2 layer creates a diffusion barrier for oxidant to enter into the reaction front, which

is further into SiC bulk. As a result, more and more unsatisfied Si+ ions are produced and

2.2 Research Strategy

Page | 23

embedded in the oxide layer. These ions act as fixed traps as described before. Another result

is that more CO2 are trapped in the oxidation area without being released in time also due to the

diffusion barrier effect of a SiO2 layer. The Cn species and C produced by a reverse reaction of

Equation (2.14), which triggered by a high concentration of CO2, are left in the oxide layer,

forming the interface traps and scattering centers by distorting the atomic bonding process and

creating a large amount of dangling bonds, which can drastically reduce the electron mobility

in the inversion channel. These Cn atoms are sp orbital hybridized to form σ bonded molecule

platelets, and become very hard to be oxidized and removed. Thus, elimination of the excess C

molecules, according to Ni, is the key procedure to reduce interface defects and states, which

in turn increases the inversion channel mobility.

Inspired by their experience in preparing C contamination-free crystalline surfaces for the

growth of molecular beam epitaxial Si-based layers, pre-oxidation using UV-ozone exposure

was chosen in this project to effectively oxidize and remove C-clusters and to form an

atomically cleaned surface, which consists of only a desirable thin oxide layer acting as a

protection from further contamination or surface deformation by the oxidation process[26].

There is also a pre-oxidation using oxygen plasma in PECVD, in comparison with the UV-

ozone treatment to verify if they can serve the same purpose.

Next and major step of the MOS capacitor fabrication is the formation of the dielectric layer.

In this project, low temperature PECVD of a silicon oxide and silicon nitride multi-layer stack

is used after the pre-oxidation and cleaning process. PECVD deposited oxide is reported to have

a lower Dit than that in the thermally grown oxide in fabrication of 3C-SiC MOSFETs [27].

The expectation here is that on the thin layer of produced clean preliminary oxide layer, which

has a clearly defined and protected interface with SiC, the PECVD oxide deposition on 4H-SiC

may also introduce much less defects and interface trapping sites compared with thermally

oxidized SiO2 layer. The added silicon nitride layer added is expected to reduce the porosity

and enhance the dielectric strength of the multi-stack layer.

Post deposition annealing (POA) is another crucial treatment of the dielectric layer in this

project, which is expected to passivate some of the interfacial and oxide defects that are

effectively reduced upon nitridation at interface[28]. The annealing processes are carried out in

N2 and N2+O2 and O2, respectively, with medium-high (below 1000°C to avoid surface

restructuring changing the controlled surface) temperatures for comparison.

Finally, C-V measurements are carried out to study the properties of the dielectric layer and

the interface, in order to have a better feedback for the improvement and optimization of the

whole process.


Page | 24

Page | 25

Chapter 3 Experimental Details

In this chapter, all the major experimental procedures in fabrication and characterization of the

p-type 4H-SiC MOS capacitors are reported with a brief description of the relevant techniques

and/or equipments used in the thesis project. In general, there are two rounds of experimental

tries in this work. In the first round, some C-V measurements were carried out on several already

fabricated MOS capacitors (by the previous researcher in the group) for characterization, and

in the second round, modified processes were adopted and new MOS capacitors are fabricated

again on the same 4H-SiC substrates used in first round. Meanwhile, 10 extra n-type 4H-SiC

MOS capacitors were also fabricated with similar conditions for I-V measurements. Following

the fabrication process and the I-V measurements (on n-type capacitors only), C-V

measurements were used to evaluate the performance of new MOS capacitors, particularly in

comparison to the devices processed in the first round. For a holistic view of the process flow,

this chapter is written in the sequence of the common processing procedures.

3.1 Sample Preparation

The 4H-SiC wafers were cut into small chips by the wafer provider, and each chip was used

as the semiconductor substrate of MOS structures. In the following, the chips are denoted as

SP1-1, SP1-2 and so on for the first round of samples. After the second round, the samples are

denoted as SP2-1, SP2-2 and so on. After a second annealing in the second round, they are

denoted as SP2-1-A2, SP2-2-A2 and so on. For 10 n-type samples fabricated for I-V tests, the

notations are SN3-1, SN3-2 and so on. The conditions of all the pre-treatments in the first round

including chemical cleaning, pre-cleaning and pre-oxidation are listed in Table 3.1.

Table 3.1 Pre-treatment conditions for nine SiC wafer chips.

Procedures Sample SP1-1 SP1-2 SP1-3 SP1-4 SP1-5 SP1-6 SP1-7 SP1-8 SP1-9

TL1

(1:1:5, 10 min at 80ºC)

HF DIP

(4%, 5 min)

TL2

(1:1:3, 10 min at 85ºC)

Rinsing and drying

UV-O3 pre-cleaning

(20 min at 22 ºC)

HF DIP (4%, 5 min)

Rinsing and drying

UV- O3 pre-oxidation

(10 min at 22ºC) Ref.

Experimental Details

Page | 26

O2-plasma pre-oxidation

(10min at 300ºC,500mTorr,100W) Ref.

3.1.1 Cleaning

Standard semiconductor wafer cleaning procedure RCA cleaning, developed by W. Kern at

RCA decades ago, is very commonly used in industries for obtaining the desired impurity-free

surface, which is a crucial prerequisite for production of a high-quality oxide layer in

semiconductor devices. Before any major treatments of the 4H-SiC substrates in this project,

the RCA based cleaning procedures were also used to minimize any possible contaminations.

At the beginning, small chips were wet cleaned in standard cleaning solution TL1 (solution

of 1 part of H2O2, 1 part of NH4OH and 5 parts of deionized water. The mixture is also called

SC-1 in many articles) for 10 minutes at 80 ºC. The purpose of TL1 cleaning is to remove the

majority of any possible organic contaminants, as well as to let ammonium hydroxide form

complex with some group I and II metals that could be stuck on the surface[29].

HF dipping was then implemented (immersion of chips about 5 minutes at 25 ºC in a solution

of 1 part of HF and 24 parts of deionized water) to strip away the oxide formed in TL1 cleaning

together with some ionic contaminations.

Subsequently, the chips were cleaned in standard cleaning solution TL2 (solution of 1 part

of H2O2, 1 part of HCl and 3 parts of deionized water. The mixture is also called SC-2) for 10

minutes at 85 ºC. This step aims at removing metallic ions remaining from previous steps. Then

the chips were thoroughly rinsed in flowing deionized water and dried in clean nitrogen gas

flow.

To effectively remove any stubborn carbon related atomic and molecular residuals on the

surface of the chips, 20 minutes of ultraviolet (UV)-ozone pre-cleaning exposure was used. This

step will form a layer with carbon oxide molecules, which needs to be stripped off by dipping

the chips in a 4% HF solution again for 5 minutes, followed by rinsing and drying.

3.1.2 Pre-oxidation

Four of the chips were then carefully pre-oxidized at 22 ºC with UV-ozone for 10 minutes, and

another four were pre-oxidized at 300 ºC with oxygen plasma for 10 minutes via PECVD

(detailed introduction of PECVD is given in the next sub-section). The purpose of this step is

to produce a surface layer of thin and clean oxide at low temperatures due to highly active

excited oxygen atoms in ozone and plasma. The C-V characterization were then made on those

two groups of samples, in order to provide the information on which pre-oxidation step can

more effectively protect the well-defined Oxide-SiC interface from C contamination and

restructuring. The chip S2 was not pre-oxidized, and is used as a reference sample.

3.1.3 PECVD Deposition

Chemical vapor deposition is a method of thin film deposition on a substrate or device structure

through adsorption of some vapor phase chemical reactants that are called precursors (normally

in gaseous state, sometimes also in liquid state). The actual reactions occur on the substrate

surface due to surface mediated catalytic process for deposition of the desired layer, but there

is also a risk to chemically react in the gas phase in some non-optimized conditions. The by-

products of the chemical reactions are ideally pumped away from the deposition chamber to air

simultaneously, after proper filtering of the gas exhausts.


Page | 27

CVD is thermally activated chemical reaction process, therefore, traditional systems utilize

heat for initiating and speeding up an intended deposition. But in many cases, the temperature

need to be low enough to avoid material restructuring and decomposition. Plasma enhanced

CVD can better address this problem. Through the glow-discharge process, low temperature

plasma (consisting of the energetic ions, radicals, and atoms and molecules at the exited states,

etc.) is formed in vacuum, in which chemical reactivities of the precursors can be greatly

enhanced using electromagnetic energy, such that the thin film deposition processes are enabled

at a relatively low temperature (< 350 °C) [30][31]. As an accompanied drawback, the PECVD

deposited layer is often very porous and more stressed with more thin film defects and

impurities, partly due to the incorporation of hydrogen from the plasm. Post annealing in oxygen

or nitrogen ambient are often engaged to make the deposited layer more densified.

Figure 3.1 below shows a photo of the PECVD system used in this project, together with a

schematic drawing of the deposition unit inside the chamber. A general schematic diagram of

atomic/molecular scale major deposition mechanisms happening near the substrate surface area

is also depicted. In the PECVD system, the sample stages are often designed to be connected to

ground (acting as bottom electrode of the plasma generating parallel electrode plates) and

heated from bottom to maintain temperature of the substrate at the desired temperature.

Figure 3.1 (a) Photo and (b) schematic of PECVD system used and (c) schematic of deposition

at atomic scale.


Page | 28

PECVD process is often affected by many variables, e.g. total pressure in chamber,

temperature, gas flow rate, gas partial pressure and time. Especially, there is an extra parameter-

RF power in PECVD, which is very important to control the process and to alter the film’s

density and stress[32].

In the project work, immediately following the pre-treatments in the last step, dielectric layer

was deposited using PECVD on top of the pre-oxidized layer of the samples. The dielectric

layer was deposited in the form of double-layer, which consist of first a silicon oxide layer at

the bottom and a silicon nitride layer on the top. The purpose of depositing the extra silicon

nitride (which in low temperature is normally deposited as SixNyHz [33] rather than Si3N4) layer

as mentioned in chapter 2 is mainly to enhance the overall dielectric strength, because the as

deposited silicon oxide (in form of SiOx) layer would normally be rather porous. The deposition

time was not so long compared to pre-oxidation, which was 25 seconds for each layer of

dielectric. The temperature of deposition of both layers was 275 ºC (note: the actual deposition

temperature recording error is in the range of ± 25 ºC) to make sure after this step the deposited

layer will be thoroughly oxidized, while at the same time the well-defined interface between

SiO2 and SiC is not affected, which is highly probable to be altered in high temperature CVD.

The description of parameters of PECVD is listed in Table 3.2.

Table 3.2 Conditions of dielectric layer deposition with PECVD (for first round experiments).

Parameters

Procedures

Pressure

(mTorr)

RF power

(W)

Composition

and flow of

gas (sccm)

Time

(sec)

Temperature

(ºC)

Theoretical

thickness

(Å)

Oxide (SiOx)

deposition 800 30

SiH4:150,

N2O:1000,

N2:800.

25 275± 25ºC 400

Nitride (SixNyHz)

deposition 1000 100

SiH4:250,

NH3:20,

N2O:500,

N2:1000.

25 275± 25ºC 400

Although chemical reactions for PECVD of silicon oxide and silicon nitride are among the

most studied CVD applications, the detailed chemical processes, which consist of a series of

(possible) reactions when being broken down to smaller steps, are not studied in detail at the

current stage of this project. Hence only overall reactions using the above mentioned precursors

(SiH4, N2O and N2 for oxide; SiH4, NH3, N2O and N2 for nitride) are listed as Equation (3.1)

and Equation (3.2) [34][35][36]. Note here, using N2O instead of O2 with SiH4 can effectively

bring down the activation energy for the oxidation reactions to happen (activation energy per

molecule is 2.5eV in N2O and 6.5eV in O2)[37].

𝑆𝑖𝐻4 + 2𝑁2𝑂 = 𝑆𝑖𝑂2(𝑆𝑖𝑂𝑥) + 2𝑁2 + 2𝐻2 (3.1)

3𝑆𝑖𝐻4 + 4𝑁𝐻3 = 𝑆𝑖3𝑁4(𝑆𝑖𝑥𝑁𝑦𝐻𝑧) + 12𝐻2(𝑔) (3.2)


Page | 29

3.1.4 Ellipsometry Measurement

Ellipsometry measurement is a non-contact and non-destructive method to characterize thin

films using optical techniques. Because it can measure, without special sample preparations,

the thickness and optical constants, etc. of a thin film (down to the angstrom/nanometer level

of thickness) in very short time, the applications are widely spread in the fields of thin film

research and production. The principle of the measurement is that upon reflection of a linearly

polarized light beam from the sample film surface, the polarization of light will be changed into

an elliptically polarized state, and the extent of change depends, other than the incident angle,

on the thickness and refractive index of the film. The change of polarization state can be

obtained by measuring the reflection wave amplitude and phase shift at p and s polarizations,

where p denotes the polarization direction parallel to the plane of incidence and s denotes the

polarization direction of the plane perpendicular to the beam. The Equation (3.3) of ellipsometry

measurement gives the relation between the measured complex Fresnel reflection coefficients

ratio ρ, the amplitude ratio (tanΨ), as well as phase shift (Δ) between p and s components of the

reflected wave. Once this ratio ρ is known, different ellipsometers can then calculate the

thickness and refractive index using different numerical model fitting and evaluation iterations

which compares the calculated values to the measured values.

𝜌 =𝑅𝑝

𝑅𝑠= 𝑡𝑎𝑛𝛹𝑒𝑖∆ (3.3)

In this project, the thickness measurements were performed for calibrating the PECVD

deposition rate (by measuring the film thicknesses on some silicon wafer chips, which was

deposited at the same time with the SiC test samples), as well as the refractive index as a

characteristic experimental parameter to assess the density and chemical composition of the

deposited film. The ellipsometer used was Rudolph AutoEl III null Ellipsometer. A photo of

the equipment together with a schematic diagram showing the measurement principle are shown

in Figure 3.2. In all ellipsometry experiments the working wavelength of the light source is

632.8 nm with an incident angle of 70°.

Figure 3.2 (a)Photo of Ellipsometer used and (b)schematic of ellipsometry measurement principle.


Page | 30

By running a series of testing depositions and ellipsometry measurements after the first

round, the proper deposition parameters for the second round experiments were chosen with the

help of thickness and refractive index analysis. Table 3.3 lists the parameters chosen to give the

satisfactory deposition rate and quality of PECVD of dielectric layers. Figure 3.3 shows the

relationship of silicon oxide deposition rate vs. total gas pressure in the chamber while keeping

the other parameters listed in Table 3.3 unchanged. 600 mTorr was chosen for the deposition of

both oxide and nitride layers, because the deposition rate in this case is optimized for controlling

the quality (not too fast and coarse deposition) and operational easiness in the PECVD system

used (no need to change pressure settings between two depositions).

Figure 3.4 shows the relationship of silicon nitride deposition rate vs. RF power, while

keeping the rest of the parameters unchanged. Here only two data points are shown for

estimation of deposition rate near 50 W instead of a wider range of data collected. This is

accurate enough to estimate the deposition rate even under the RF power range from 35W to

55W, because the variation of deposition rate is not dramatic with the change of RF power, for

the deposition under the listed conditions. The measured average refractive indices of the

deposited films under these conditions by ellipsometry are 1.458 for silicon dioxide films,

which is very ideal compared to the theoretical value 1.457 for the stoichiometric silicon

dioxide, under the measurement wavelength of 632.8nm[38], and 2.246 for the silicon nitride

films, which is a little bit higher than the theoretical value of the stoichiometric Si3N4 (around

2.023 for measurement wave length of 632.8nm[39]), but still acceptable for our purpose

[40][41]. As a result of the new deposition process parameters, in the second round of MOS

capacitor fabrication, the estimated dielectric layer thickness is around 1240 Å in total.

Table 3.3 Conditions of dielectric layer deposition with PECVD (for second round experiments).

Parameters

Procedures

Pressure

(mTorr)

RF power

(W)

Composition

and flow of

gas (sccm)

Time

(sec)

Temperature

(ºC)

Estimated

thickness

(Å)

Oxide (SiOx)

deposition 600 22

SiH4:81,

N2O:1000,

He:294.

120 355ºC 732

Nitride (SixNyHz)

Deposition 600 50

SiH4:81,

NH3:17,

N2:900.

180 355ºC 508


Page | 31

Figure 3.4 Silicon nitride PECVD deposition rate vs. RF power under selected parameters.

Figure 3.3 Silicon dioxide PECVD deposition rate vs. chamber pressure under selected parameters.


Page | 32

3.1.5 Annealing

Post-oxidation annealing is a very effective treatment for eliminating the point-defect induced

charges in the dielectric layer and lowering the density of traps in the SiO2/SiC interface. The

equipment employed for the dry annealing was TEMPRESS furnace system with Model 261

digital temperature controller. It is shown in Figure 3.5 with a schematic view of the tube area.

The furnace tube was heated in three regions, and the sample holder was placed in the central

part of the tube to utilize the homogeneous temperature distribution therein. What is not shown

in the figure are the gas lines connected to the rear part of the tube and system, which can supply

N2, O2 or a mixture of both to the annealing area.

After the dielectric layer growth using PECVD, all the fabricated samples were annealed

under the conditions listed in Table 3.4. The different temperature and time settings were chosen

to find out better processing conditions through the test by comparison.

Figure 3.5 (a) Front end photo of the furnace system and (b) schematic drawing of quartz tube with

loaded samples.


Page | 33

Table 3.4 Annealing conditions for the first round

Annealing conditions SP1-1 SP1-2 SP1-3 SP1-4 SP1-5 SP1-6 SP1-7 SP1-8 SP1-9

Annealing ambient gas O2 O2 O2 N2 O2 N2 O2 O2 O2

Time (hour) 3 2 2 2 3 2 3 2 3

Temperature (ºC) 875 875 875 875 850 875 850 875 875

3.1.6 Magnetron Sputtering

Sputtering, as a physical vapor deposition process which usually occur under a strong electric

field in plasma systems, mainly utilizes the momentum transfer from incident particles

(normally inert gas atoms ionized by electrons and accelerated by an electric field towards the

target) to the target surface atoms, in order to emit them out of the target and deposit on the

substrate. The other minor contribution to the sputtering yield may come from thermal

vaporization by the heat accumulated when incident particles continuously bombard the target

surface [42]. Magnetron sputtering is an improved technique for the higher yield/power

consumption ratio and efficiency, in which a meticulously configured magnetic field is applied

in the system behind the target to enhance electron circulation around the target surface (by

Lorentz-force), which in turn increases the ionization efficiency of inert gas atoms and other

neutral atoms in plasma. This ultimately increases the sputtering yield, and thus film deposition

rate. If the target material is insulating by nature, the electric field in the system should be

generated by the RF power instead of DC to sustain plasma and sputtering. Figure 3.6 shows

schematically the magnetron sputtering process, in which the system uses Ar gas in the chamber

and assumes a sputtering-down configuration like the system used in this project.

Figure 3.6 Schematic diagram of Magnetron sputtering inside vacuum chamber (notice: magnets and

backing plate are not drawn in proportion to atoms).


Page | 34

Immediately after the annealing treatment, the samples were loaded into the magnetron

sputtering system shown in Figure 3.7 [43] through the sample load lock. An Al-layer was then

deposited on the samples from the Al target to form metal gate parts of MOS capacitors. In the

figure, it also shows the metal mask with numerous circle-patterned holes, which was clamped

on the sample chips for the formation of round metal gates on top of the dielectric layer during

the deposition. Table 3.5 summarizes the major parameters for the gate metal deposition and

the metal layer thickness measured using Veeco Dektak 6M stylus profiler, which is shown in

Figure 3..8 together with a measured layer thickness profile.

Table 3.5 Magnetron sputtering parameters and film thickness.

Power supply

voltage (V) Current(mA)

Ar air flow rate

(cm3/min) Pressure (mTorr) Time (seconds) Thickness (Å)

400.0 440.0 16.2 1.8 1020.0 1340.0

Figure 3.7 Magnetron sputtering equipment (a) and deposition mask(b) used.


Page | 35

The fabricated MOS capacitors after sputtering are shown in Figure 3.9. There are two types

of metal gate on top of the oxide layer. One type consists of many round gates and the other is

just a large area single gate. This configuration is a common design in those measurement

systems, convenient for testing I-V and C-V characteristic curves with two probes both

contacting the sample from the frontside. It is worth mentioning here that on all the chips, each

small round metal gate has a diameter of around 0.64±0.03 mm (or an area of around 0.32 mm2),

and each of the large gates has an area of around 60 mm2 and above. Furthermore, the distance

between the two types of patterns ranges from 2 to 6 mm, the parasitic capacitance issue is thus

negligible.

3.1.7 Summary of treatment procedures for the second round MOS capacitors

The second round of the experiments was carried out on the samples SP1-1, SP1-2, SP1-3,

SP1-4, SP1-6 and SP1-8 chips again, after completely dissolving the deposited metal and

dielectric layer and cleaned using the modified treatments shown in Table 3.6.

Figure 3.8 (a) Veeco Dektak 6M stylus profiler and (b) thickness measurement result of a

sputtered film.

Figure 3.9 Picture of SiC MOS capacitor taken (a) before and (b) after sputtering.


Page | 36

Table 3.6 Summary of the treatment procedures for the 2nd round fabrication

Procedures Original Sample SP1-1 SP1-2 SP1-3 SP1-4 SP1-6 SP1-8

HCl solution dip

(25%, 20 min at 80 ºC)

HF DIP

(50%, 20 min)

TL2

(1:1:3, 15 min at 85 ºC)

Rinsing and drying

UV-O3 pre-cleaning

(30 min at 22 ºC)

HF DIP (17%, 3 min)

Rinsing and drying

UV- O3 pre-oxidation

(30 min at 22 ºC)

Ref. Do

nothing

N2O-plasma pre-oxidation

(30min at 350 ºC,600mTorr,22 W)

Ref. Do

nothing

PECVD of dielectric layer

(details listed in Table 3.3)

Annealing: N2 1h plus O2 2h (at 900 ºC)

Annealing: O2 (3h at 900 ºC)

Annealing: N2 (3h at 900 ºC)

Metal gate evaporation

Notation for C-V test in the 2nd round SP2-1 SP2-2 SP2-3 SP2-4 SP2-6 SP2-8

Remove Al by HCl solution dip

(25%, 20 min at 80 ºC)

Ref. Do

nothing

TL2

(1:1:3, 15 min at 85 ºC)

Ref. Do

nothing

Annealing: O2 (3h at 950 ºC) Ref. Do

nothing

Annealing: N2 (3h at 950 ºC) Ref. Do

nothing

Metal gate evaporation Ref. Do

nothing

Notation for C-V test after 2nd annealing SP2-1-A2 SP2-2-A2 SP2-3-A2 SP2-4-A2 SP2-5-A2 SP2-6-A2

3.2 I-V Measurements

Page | 37


Dielectric strength of the insulator layer in MOS capacitors can be simply understood as the

inherent ability of the insulator to withstand a high electric field and maintain operation in a

proper condition without any breakdown or failure. It depends on the chosen material, device

structure, thickness, temperature, and frequency of operation, etc.. It can be characterized using

I-V measurement equipments by applying a ramping voltage across the dielectric layer, while

measuring the current at the corresponding voltage point until the occurrence of the current

increasing abruptly towards infinity, i.e. a dielectric breakdown. The leakage may happen

through small current paths made up of defects created under stress and material

deterioration[44]. Time-zero dielectric breakdown (TZBD), a kind of breakdown measured in

this project, happens immediately when a certain high voltage stress is reached [45]. This is a

hard breakdown, and often results in the irreversible damage in the dielectric. Therefore, some

other samples of n-type 4H-SiC MOS capacitors, which were produced under similar

conditions, are tested to draw a statistically acceptable evaluation of the dielectric strength.

Figure 3.10 shows the I-V measurement system Wentworth Labs manual probing station, which

works together with Hewlett Packard 41501A SMU and pulse generator expander and 4156A

Precision semiconductor parameter analyzer (not shown).

3.3 C-V Measurements

The C-V measurements are performed using the same Wentworth Labs manual probing station,

but connected with a Capacitance-Voltage module. With contacts using two metal probe tips,

one on the small round Al gate and another on the large Al gate (as schematically shown in

Figure 3.11), the total MOS capacitor in test can be regarded as two capacitors connected in

series. Using C1 to denote the capacitance of a small area capacitor and C2 to denote the

capacitance of a large area capacitor, the total capacitance C can be calculated using Equation

(3.4) :

Figure 3.10 Probing station for I-V measurements.


Page | 38

𝐶 =𝐶1𝐶2𝐶1+𝐶2

=𝐶1

𝐶1𝐶2

+ 1≈ 𝐶1

(3.4)

Since the area of C2 is much larger than the area of C1 as mentioned in 3.1.6 (which means

C2 is much larger than C1), the C1 /C2 ratio in the denominator approximates to zero. The total

capacitance C is thus simplified to be equal to C1. In this manner, the measured capacitance is

essentially due to a parallel plate MOS capacitor with a small round metal gate area of around

0.32 mm2, which in turn is a series connection of an oxide capacitor component and a

semiconductor capacitor component with a same capacitor area. With the help of equations

mentioned before and C-V measurement results, many useful physical parameters of the

fabricated MOS capacitors can be determined, such as oxide thickness, oxide charges, and the

density of interface trap,etc..

Figure 3.11 Schematic drawing of (a) C-V measurement method, and (b) charge distribution analogue

to a series of two capacitors.

Page | 39

Chapter 4 Results and Discussions


The I-V measurement results, i.e. dielectric leakage current I vs. applied gate bias voltage V are

plotted for 10 SiC MOS capacitor samples in Figure 4.1. The data can also be converted to

leakage current density J vs. effective electric field E data set using Equation (4.1) and Equation

(4.2) to reveal non-device-specific properties. The area of dielectric AO chosen is approximately

3.200×10-3 cm2, and the dielectric layer thickness WO is estimated to be 1.104×10-5 cm.

𝐽 =𝐼

𝐴𝑂 (4.1)

𝐸 =𝑉

𝑊𝑂 (4.2)

Figure 4.1 Measured characteristic curves of dielectric leakage current density vs. applied electric field

for 10 MOS capacitors. The inset is the same curves re-plotted in log scale.

Results and Discussions

Page | 40

The pre-oxidation and annealing treatments for 10 n-type 4H-SiC MOS capacitors are listed

in Table 4.1. Compared to the p-type capacitors fabricated in the second round, pre-treatments

are the same, and conditions for PECVD of dielectric layer are similar with only a minor change

in chamber pressure (ca. 8%), which results in about a 5 to 10 nm change in the estimated total

dielectric thickness (also ca. 8%). Thus, the discrepancy is within a reasonable range for

estimating the dielectric strength of the p-type MOS capacitors, and evaluating which treatment

conditions are preferable to produce better results.

Table 4.1 Treatment conditions for 10 n-type 4H-SiC MOS capacitors before and after PECVD.

Treatment Sample SN3-1 SN3-2 SN3-3 SN3-4 SN3-5 SN3-6 SN3-7 SN3-8 SN3-9 SN3-10

Pre-oxidation No No UV- O3 UV- O3 UV- O3 UV- O3 N2O-

plasma

N2O-

plasma

N2O-

plasma

N2O-

plasma

Annealing atmosphere O2 N2+

N2/O2 O2

N2+

N2/O2

N2+

N2/O2

N2+

N2/O2 O2

N2+

N2/O2

N2+

N2/O2

N2+

N2/O2

Annealing time (hour) 3 1+2 3 1+2 1+2 1+2 3 1+2 1+2 1+2

Annealing

temperature (ºC) 875 900 875 875 900 950 875 875 900 950

As shown by the I-V characteristic curves in Figure 4.1, in general all the capacitors have

low leakage currents (leakage current is in the order of magnitude around 10-1 μA) when

operating with a bias ranging from 0 to 60 V. If the breakdown current is defined at 0.3 μA

(corresponding to J of around 0.9×10-4 A/cm2), which is a little bit above the noise background

of the measurement in Figure 4.1, then the breakdown electric field EBD of those ten samples

can be extracted and plotted in Figure 4.2. Basically the measured EBD for all samples are higher

than 5 MV/cm, indicating a generally satisfactory quality of the PECVD double layer dielectrics

for the normal operations of MOS device (3 to 4MV/cm[46], [47]). However, there is no

correlation whether the pre-oxidation process would affect the dielectric strength of the

deposited layers. Sample SN3 and SN1 annealed in O2 ambiance at 875 ºC for 3 hours show

distinctively higher EBD, which may suggest an enhanced oxidation effect in pure oxygen

annealing to more effectively remove the vacancy type layer defects due to insufficient

oxidation during PECVD, and the dielectric layer becomes denser. This speculation needs

however to be ascertained by further experiments, as the electrode layout of the MOS capacitors

in SN1 and SN3 is not the same as that in other samples. The shape and area of large Al

electrodes of these two samples differ from that of the other samples.


Page | 41


The C-V measurement curves of the first and second round experiments are plotted in Figure

4.3, Figure 4.5, and Figure 4.7, respectively, while the normalized C-V curves are

correspondingly shown in Figure 4.4, Figure 4.6, and Figure 4.8 for comparison.

Figure 4.3 Comparison of C-V curves of the fabricated MOS capacitors in the first round experiments.

Figure 4.2 Breakdown electric field of 10 samples, plotted from the lowest to highest.


Page | 42

Figure 4.5 Comparison of C-V curves of the fabricated MOS capacitors in the second round experiments.

Figure 4.4 Comparison of normalized C-V curves of the fabricated MOS capacitors in the first round

experiments (shifted curves to reduce overlapping) and treatment condition for them.


Page | 43

Figure 4.6 Comparison of normalized C-V curves of the fabricated MOS capacitors in the second

round experiments.


Page | 44

Figure 4.8 Comparison of normalized C-V curves of the fabricated MOS capacitors in the second round

experiments after the second annealing.

Figure 4.7 Comparison of C-V curves of the fabricated MOS capacitors in the second round

experiments after the second annealing.


Page | 45

At first glance of these figures, one would notice that all the C-V curves for the second round

experiments, except sample 1, shifted towards the negative bias direction for at least several

volts compared to the C-V curves from the first round samples, meaning that the net charge

inside the dielectric layers under the flat band condition are much more positive in these

samples. This could be caused by a higher density of positive charge centers or mobile ions

presented in the dielectric layer, or by a higher density of trap states at the dielectric/SiC

interface, since the interstitial states are donor like in the lower half of the bandgap, and in p-

type MOS under the flat band condition the interfacial charges will be positive.

There is a way, fortunately, to distinguish the origin of the left shift of the curves. When one

sweeps the measurement bias reversely from positive to negative, if the curves will shift towards

the negative bias direction, especially at an elevated temperature, implying there are significant

amount of mobile ions. If the curves shift towards the positive bias direction, however, it is an

indication that there is a significant amount of interface states. If the curves do not shift

obviously, it means the positive charge centers are mainly fixed charges or oxide trapped

charges. This kind of examinations are carried out on all the samples, and the results clearly

show that the main cause for the negative shift of the C-V curves in the above-listed

measurements are due to the interface states.

Figure 4.9 shows two examples of the C-V measurement (SP2-1 and SP2-2 in the second

round experiment) under the normal and reverse sweep of the gate bias. The mechanism behind

the positive shift in reverse sweep is that starting with a large positive bias, the interface states

in the upper half of the bandgap are filled with electrons and thus cause the flat-band voltage of

the curves shifting more positively than the ideal case. This is an expected result, as many have

postulated, carbon atoms or clusters may have induced the interface states, which tend to trap

electrons under some period of the positive bias and generally cause a positive shift of C-V

curves [48].

All the measured C-V curves from Figure 4.3 to Figure 4.9 also demonstrate a common

feature: there is no obvious inversion region. Instead, they all move continuously into the deep

depletion region. A main reason for this feature is that SiC MOS capacitors have very low level

of intrinsic carrier density. Therefore, if the carrier generation/recombination rate is not fast

enough (which is the case when no extra light illumination), the depletion width has to vary in

order to balance the gate charge variation [12]. Hence, the capacitance decreases just like in the

Figure 4.9 Normal vs. reverse sweep of C-V measurement bias for SP2-1 and SP2-2 MOS capacitors.


Page | 46

depletion region even when a larger positive bias is applied. The relation between capacitance

and gate voltage in this case follows the Equation (2.3), which can be rewritten in a detailed

form as Equation (4.3) with the help of Equation (16.35) and (16.36) in Pierret’s book [22]:

𝐶𝐷𝑒𝑝

𝐶𝑂=

1

1 +𝜀𝑟(𝑂)𝑊𝑆


=1

√1 +2𝜀𝑟(𝑂)2𝜀0𝑉𝐺𝑞𝜀𝑟(𝑆)𝑊𝑂

2𝑁𝐴

(4.3)

where VG is the applied gate bias, and NA is the SiC substrate acceptor doping concentration.

Rearranging the Equation (4.3), one can get Equation (4.4) as below:

(𝐶𝑂𝐶𝐷𝑒𝑝

)

2

− 1 =2𝜀𝑟(𝑂)

2𝜀0𝑉𝐺

𝑞𝜀𝑟(𝑆)𝑊𝑂2𝑁𝐴

(4.4)

This equation shows that if one plots a [(CO/C)2-1] vs. VG curve based on the measured C-V

data of the MOS capacitors, the slope k of the curve in the part after the flat band voltage VFB

into depletion will be:

𝑘 =2𝜀𝑟(𝑂)

2𝜀0

𝑞𝜀𝑟(𝑆)𝑊𝑂2𝑁𝐴

=2

𝑞𝜀𝑟(𝑆)𝜀0𝑁𝐴

𝜀𝑟(𝑂)2𝜀0

2

𝑊𝑂2 = 𝑍 (

𝜀𝑟(𝑂)𝜀0

𝑊𝑂)2

= 𝑍𝐶𝑂/𝐴2 (4.5)

where CO/A denotes CO/A, i.e. dielectric layer capacitance per unit area, and coefficient Z is

approximated here to be the same for all the samples, since in this project all the substrates were

cut from one homogeneously doped 4H-SiC wafer (so the same original εr(S) and NA). Moreover,

during the fabrication of SiC MOS capacitors, the substrate surface under the dielectric layer is

not thermally oxidized, such that the surface structures were highly unaffected (i.e. the changes

in surface local εr(S) and NA near the surface are minimized). On the other hand, the samples are

first treated with different pre-oxidation methods, then dielectric layers are deposited by

PECVD with different parameters, and finally annealed with different conditions. All of those

process steps may result in different apparent εr(O) and WO.

Figure 4.10 and Figure 4.11 in the following show the excerpted [(CO/C)2-1] vs. VG plots of

all the MOS capacitors fabricated in two experiment rounds. The k value is expected to decrease

with VG if a large amount of interface states exists. Therefore, to be more accurate, only the data

points close to the flat band voltage are plotted. The curves are then approximated by linear

fittings, in order to extract k values. The following parameters are obtained by using and

comparing the k coefficient of each capacitor:

(1). By utilizing Equation (4.5), with k values calculated from two figures, εr(S) value 9.7

obtained from

Table 1.1 1.1, gate area 3.200×10-3 cm2 from previous text, Co values (approximately the

largest C values in the accumulation region) from Figure 4.3, Figure 4.5 and Figure 4.7,


Page | 47

respectively, SiC substrate doping concentration NA is calculated to be in the range from

0.5×1016 cm-3 to 3.3×1016 cm-3.

(2). The built-in potential VBI caused by the metal-semiconductor work function difference is

calculated using Equation (2.5) and Equation (4.6) [22]. Φ’M - χ’ is approximately 0.5 eV

[49][50] and ni is approximately 6.4×10-9 cm-3 (calculated using Equation (28) from [51],

Equation (4), (5), (6) and Table 2 values from [52] ) . Using these values and NA in the previous

paragraph, VBI ≈ -2.565V is calculated for all samples with less than 1% deviations.

(𝐸𝐶 − 𝐸𝐹)𝐹𝐵 =𝐸𝑔

2+ 𝑘𝑇 𝑙𝑛

𝑁𝐴𝑛𝑖

(4.6)

(3). In theory, a linear curve fitting of the right part (where the voltage range corresponding to

the depletion voltage range of C-V curve) of a [(CO/C)2-1] vs. VG plot will be a straight line

(characterized by the slope k) intersecting VG axis at VFB. Compared with the theoretical flat

band voltage value for ideally fabricated MOS capacitors, which do not have any dielectric

charges and only VBI causes any C-V curve shifts (i.e. VFB=VBI), the difference VFB-VBI is the

flat band voltage shift ΔVFB, which is a critical parameter for MOS capacitance evaluation.

(4). As seen from Equation (4.5), √𝑘/𝑍 gives the value of CO/A. If the exact values of εr(S) and

NA for the SiC substrate are determined, the actual numerical value of CO/A can be calculated.

However, in this study these two values are not determined because the interest is the relative

changes among different MOS capacitors fabricated. Therefore, the values obtained for

comparison will just be mentioned with Z in their unit as relative values.

(5). Effective charge per unit area QEff/A of the dielectric layers under the flat band condition

can be calculated by Equation (4.7), which is modified from Equation (6.7) in [12] to

characterize the properties per unit area:

Figure 4.10 [(CO/C)2-1] vs. gate bias VG lines for capacitors fabricated in the first round.


Page | 48

𝑄𝐸𝑓𝑓/𝐴 = 𝐶𝑂/𝐴 ⋅ |𝛥𝑉𝐹𝐵| (4.7)

Table 4.2 lists some parameters extracted from Figure 4.10 and Figure 4.11.

Table 4.2 Extracted parameters for all MOS capacitors

1st round SP1-1 SP1-2 SP1-3 SP1-4 SP1-5 SP1-6 SP1-7 SP1-8 SP1-9

k (V-1) 1.7177 1.4173 1.2022 1.6474 2.0777 1.7910 2.3420 1.4285 1.5233

ΔVFB (V) -3.6334 1.9725 3.3406 4.4322 4.6625 1.7228 1.3795 3.5128 2.8274

CO/A (V-0.5Z-0.5) 1.3106 1.1905 1.0964 1.2835 1.4414 1.3383 1.5304 1.1952 1.2342

QEff/A (V0.5Z-0.5) -4.7620 2.3483 3.6628 5.6888 6.7206 2.3056 2.1111 4.1985 3.4896

2nd round SP2-1 SP2-2 SP2-3 SP2-4 NA. SP2-6 NA. SP2-8 NA.

k (V-1) 1.4424 2.4714 2.3183 2.3092 NA. 2.4188 NA. 1.9058 NA.

ΔVFB (V) -1.1089 -10.197 -11.857 -8.2959 NA. -6.4973 NA. -7.1952 NA.

CO/A (V-0.5Z-0.5) 1.2010 1.5721 1.5226 1.5196 NA. 1.5552 NA. 1.3805 NA.

QEff/A (V0.5Z-0.5) -1.3318 -16.031 -18.053 -12.607 NA. -10.105 NA. -9.9330 NA.

2nd round

2nd annealing

SP2-1-

A2

SP2-2-

A2

SP2-3-

A2

SP2-4-

A2 NA.

SP2-6-

A2 NA.

SP2-8-

A2 NA.

k (V-1) 1.4424 2.4026 2.2803 2.3665 NA. 2.4205 NA. 2.1196 NA.

Figure 4.11 [(CO/C)2-1] vs. gate bias VG lines for capacitors fabricated in the second round.


Page | 49

ΔVFB (V) -1.1089 -6.8061 -8.0073 -4.7657 NA. -6.1068 NA. -5.8941 NA.

CO/A (V-0.5Z-0.5) 1.2010 1.5500 1.5101 1.5383 NA. 1.5558 NA. 1.4559 NA.

QEff/A (V0.5Z-0.5) -1.3318 -10.550 -12.092 -7.3312 NA. -9.5008 NA. -8.5812 NA.

Figure 4.12 shows intuitively how each MOS sample is positioned in a CO/A vs. ΔVFB

diagram. The closer the sample locates to the axis origin 0 point, the smaller the ΔVFB and

dielectric layer effective charge are. Considering the experimental conditions of the samples

and combining observations from Table 4.2 and Figure 4.12, one can discover some general

trends, which are discussed as follows:

(1). The first round samples contain fewer net charges in the dielectric layer than those in the

second round samples, but have higher amount of negative charge centers than positive ones.

(2). The second round samples have a larger amount of flat band voltage shift and interface

states, all of which are effectively brought down by the second annealing at higher temperature

(950°C). In the first round, higher temperature also produces better annealing effect when

keeping other parameters at the same level.

(3). Generally speaking, UV-ozone pre-oxidation method produce more positive charge centers

than the plasma pre-oxidation method in each round of the experiments.

(4). Reference samples in both rounds contain less dielectric layer effective charge, which could

be an indication that pre-oxidation methods actually produce more charge centers. But

considering the project is still in its preliminary phase, and some parameter setting are just

tentative, the pre-oxidation could be improved largely to reduce the effective charge.

(5). While other conditions are the same or comparable, annealing in nitrogen ambience may

be more effective to bring down CO/A compared to annealing in oxygen ambience. But this

Figure 4.12 Distribution of all the MOS capacitors on a CO/A vs. ΔVFB diagram.


Page | 50

speculation is considered to be weak at current situation, as it is only based on a small number

of experimental data, while sample SP1-2 annealed in oxygen ambient is an exception for this

speculation.

Page | 51

Chapter 5 Conclusions and Suggestions

5.1 Conclusions

The present thesis project investigated the effects of interface defects on the performance of

4H-SiC MOS capacitors and the mechanisms for the defects generation in conventional thermal

oxidation techniques, which are believed to be strongly related to the interface or dielectric layer

containing excess amount of carbon atoms as the direct result of the thermal oxidation

processes. A new approach to fabricate and treat the dielectric layer is proposed and

experiments from fabrication to characterization are carried out to examine the effectiveness of

the technique. The experimental results are summarized and presented as follows.

• The capacitors produced using the proposed technique have a low leakage current

density at the level of magnitude around 10-6 A/cm2 to 10-5 A/cm2, when operating

at an electric field of 0-5 MV/cm.

• All the samples using double stack dielectric layers have strong dielectric strength,

which is larger than 5 MV/cm, when the breakdown current density is defined at

2×10-4A/cm2. This result is considered to be more than adequate for most MOS

device applications.

• Interface states/traps are determined by experiment to be the main cause for the

negative C-V curve shift for the MOS capacitors fabricated in the second round of

this project, compared to the samples from the first round.

• The flat band voltage shift of the MOS capacitors are in the range of -11.9 V to 4.7

V, and the effective charge density of capacitors fabricated in the second round are

roughly 2-4 times higher than those samples in the first round. UV-ozone pre-

oxidation method induces more negative shift of VFB.

• Higher temperature (but lower than 1000 °C) annealing in nitrogen ambiance for 2-

3 hours can generally reduce the effective charge density in dielectric layers, more

efficiently than using oxygen ambient annealing.

5.2 Suggestions for Future Works

The next step of the research could continue in the following proposed directions:

• There is a need to carry out more experiments using similar fabrication conditions to

verify the results and speculations come out of this project.

• The density of interfacial states can be determined and more quantitatively calculated

by measuring the C-V characteristics under high frequencies and low frequencies.

This “High-Low method” is commonly used in MOS capacitor research.

• UV-ozone pre-oxidation equipment and temperature could be changed to get better

results.

Conclusions and Suggestions

Page | 52

• The measurements of electrical properties can be done in higher temperatures even

with light illumination, in order to understand the behaviour of the deep level traps.

• MOSFET structures should be fabricated when enough improvements are gained to

test and characterize the full transistor functions, which can determine the effective

channel mobility for evaluation of the technique employed.

Page | 53

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