ASIX MultiPort Ethernet EEPROM UserGuide v101 3

7/30/2019 ASIX MultiPort Ethernet EEPROM UserGuide v101 3

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ASIX Multi-Port Ethernet Controller

EEPROM/Manufacture User Guide

Revision 1.01Mar. 1st, 2010



Copyright (C) 2008-2010Reserved by ASIX Electronics Corporation


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Revision History

Revision Date Description0.10 2008/07/30 Preliminary release.1.00 2009/11/13 1.Added AX88782/AX88613 EEPROM related information.1.01 2010/03/01 1.Added Section 3-2-6 about how to configure Non-802.1Q Port-Based

VLAN Entry.2.Added some FAQs about AX88613 EEPROM in Section 4-4, 4-5.


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Contents

1. ........................................................................................... 5Introduction2. .................................................................. 6EEPROM Device Selection3. .................................................. 7EEPROM Data Related Information

3-1. ..................................................................................... 7EEPROM Data Format3-2. .............................................................. 8EEPROM Write Command Examples

3-2-1. .......... 8Configure Port 0/Port 1 MAC Addresses and Enable PHY0/PHY13-2-2. ............. 9Indirectly Write PHY0/PHY1 Registers through MDIO Interface3-2-3.

............................................................................................................ 9Set PCI Vendor/Device and Sub-Vendor/Sub-Device IDs (for AX88742

only)

3-2-4.

............................. 10

Configure L2 Routing Table for Source Port 0/Port 13-2-5. ................................................................ 11Configure 802.1Q VLAN Entry3-2-6. ..................................... 12Configure Non-802.1Q Port-Based VLAN Entry3-2-7. ............................. 13Configure 802.1P QoS Mapping Table for Port 0/1/23-2-8. .................................. 14Configure IGMP Multicast IP Group Table Entry3-2-9. ........................................................... 15Configure RX Rate Limit Function3-2-10. ........................................................... 16Configure TX Rate Limit Function

4. .................................................................................. 17EEPROM FAQs4-1.

...................... 17Do we need to register our own PCI Vendor ID/Device ID and SubsystemVendor ID/Subsystem Device ID for AX88742 applications?

4-2..................................... 17

Do I have to assign two unique MAC addresses for Port 0 and Port 1 of everyASIX Multi-Port Ethernet Controller based devices?

4-3. ............................ 17How to register a MAC/Ethernet address from IEEE-SA?4-4. ........................ 18Is the EEPROM device required for AX88613 applications?4-5. .............. 18How to program the EEPROM content on AX88613 applications?

Appendix 1. ........................... 19AX88742 EEPROM Reference SettingAppendix 2. .......... 20AX88783/AX88782 EEPROM Reference SettingAppendix 3. ........................... 21AX88613 EEPROM Reference Setting

A3-1. ..... 21Port 2 in MII Mode with External PHY (default setting for demo board)A3-2. ........................................................................... 24Port 2 in Reverse MII ModeA3-3. ....................................................... 26Port 2 in RMII Mode with External PHYA3-4. ......................................................................... 29Port 2 in Reverse RMII Mode


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TablesTable 1. .................................................................. 6EEPROM Device Selection Table (PD: Pull-Down, PU: Pull-Up)Table 2. ..................................................................................................................................... 7EEPROM Data FormatTable 3. .......................................................................................................... 19AX88742 EEPROM Reference SettingTable 4. .......................................................................................... 20AX88783/AX88782 EEPROM Reference SettingTable 5. ......................................... 23AX88613 EEPROM Reference Setting (Port 2 in MII mode with external PHY)Table 6. ................................................................ 25AX88613 EEPROM Reference Setting (Port 2 in Rev-MII mode)Table 7. ....................................... 28AX88613 EEPROM Reference Setting (Port 2 in RMII mode with external PHY )Table 8. .............................................................. 31AX88613 EEPROM Reference Setting (Port 2 in Rev-RMII mode)


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1. Introduction

ASIX Electronics provides some multi-port embedded Ethernet controllers that support differentprocessor host interfaces commonly used in embedded system applications. The supportedprocessor host interfaces are PCI bus, non-PCI bus (SRAM-like) and Ethernet MACs MII/RMIIbus. The following URL provides detailed online resource of ASIX Electronics multi-portembedded Ethernet solutions:(Refer tohttp://www.asix.com.tw/products.php?op=ProductList&PLine=65).

This user guide applies specifically to the following multi-port Ethernet controllers, namely,AX88742, AX88783, AX88782 and AX88613.

2-Port PCI Fast Ethernet

AX88742 -- 32-bit PCI 2-Port 10/100M Fast Ethernet Controller

2-Port Non-PCI Fast Ethernet

AX88783 -- Non-PCI 8/16/32-bit 2-Port 10/100M Fast Ethernet ControllerAX88782 -- Non-PCI 8/16-bit 2-Port 10/100M Fast Ethernet Controller

2-Port MII/RMII Fast Ethernet

AX88613 -- 3-Port 10/100M Fast Ethernet Switch Controller

This user guide provides the information about the EEPROM configuration of ASIX Electronicsmulti-port embedded Ethernet controllers.
http://www.asix.com.tw/products.php?op=ProductList&PLine=65http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=99;65;105&PLine=65http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=98;65;86&PLine=65http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=101;65;86&PLine=65http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=102;65;107&PLine=65http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=102;65;107&PLine=65http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=101;65;86&PLine=65http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=98;65;86&PLine=65http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=99;65;105&PLine=65http://www.asix.com.tw/products.php?op=ProductList&PLine=65


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2.EEPROM Device SelectionThe multi-port embedded Ethernet controllers support 8-bit mode 93C46, 93C56 and 93C66

EEPROM. The multi-port embedded Ethernet controllers will detect the CS and SK signals state(Pull-Up or Pull-Down) to decide the EEPROM device type (93C46, 93C56 or 93C66) duringthe hardware reset cycle or the reload EEPROM command.

The following table defines the EEPROM device type based on the CS and SK signals. ThePD means the signal is connected to ground through a 4.7K resistor, and PU means thesignal is connected to 3.3V VCC through a 4.7K resistor.

EEPROM size(Byte)

SK CS

N/A (default) PD PD1K(93C46) PD PU2K(93C56) PU PD4K(93C66) PU PU

Table 1. EEPROM Device Selection Table (PD: Pull-Down, PU: Pull-Up)

Note:1. The multi-port embedded Ethernet controllers can only support 8-bit mode 93C46, 93C56

and 93C66 EEPROM. Please make sure you select a correct EEPROM type on your targetapplications.

2. The EEPROM is optional for AX88783/AX88782 if the MAC addresses of Port 0 and Port 1can be stored on the Flash memory of your embedded system. In this case, theAX88783/AX88782 driver should read the MAC addresses of Port 0 and Port 1 from theFlash memory and then configure the related Port 0/Port 1 MAC address registers for normaloperation.

3. The EEPROM is optional for AX88742 if the MAC addresses of Port 0 and Port 1 can bestored on the Flash memory of your embedded system and the AX88742 PCI Vendor ID andDevice ID of your application uses the AX88742 default Vendor ID (0x125B) and Device ID(0x7420). In this case, the AX88742 driver should read the MAC addresses of Port 0 andPort 1 from the Flash memory and then configure the related Port 0/Port 1 MAC addressregisters for normal operation.

4. The EEPROM is optional for AX88613 if your MCU supports the SPI interface and theMAC addresses of Port 0 and Port 1 can be stored on the Flash memory of your embeddedsystem. In this case, your MCU firmware can read the MAC addresses of Port 0 and Port 1from the Flash memory and then configure proper AX88613 registers through the SPIinterface for normal operation. Please refer to Section 4.4 of AX88613 datasheet for moredetails about the AX88613 SPI Data Write command format.


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3.EEPROM Data Related Information3-1.

EEPROM Data Format

The multi-port embedded Ethernet controllers will auto-configure the MAC registers based onthe write commands in the EEPROM during the hardware reset operation or the reload EEPROMoperation. The following is the data format of EEPROM Write Command,

Address [9:2] Data [31:24] Data [23:16] Data [15:8] Data [7:0]

Address [9:2]: MAC register address (Address[9:2] * 4)Data [31:24], Data [23:16], Data [15:8], Data [7:0]: MAC register written 32-bit value

The EEPROM Write Command contains the MAC register address and four bytes of databecause the MAC registers of the multi-port embedded Ethernet controllers are 32-bit wide.

The Address [9:2] value 0x00 and 0xFF are reserved. If the Address [9:2] value is 0x00 or 0xFF,the multi-port embedded Ethernet controllers will ignore this write command and continue to runnext write command.

The EEPROM Write End Command is defined as Address [9:2] =0x00 and Data [31:0] =0x84149435. The EEPROM used space should be terminated by an EEPROM Write EndCommand. When the multi-port embedded Ethernet controllers decode this Write End Command,the multi-port embedded Ethernet controllers will stop the EEPROM auto-loading operation. If

the Write End Command is not defined on the last field of EEPROM used space, the multi-portembedded Ethernet controllers will read through all 1K (93C46), 2K (93C56) or 4K (93C66)pre-defined EEPROM address space. In this case, the rest of EEPROM unused space should befilled in 00 or FF to avoid to run the wrong EEPROM write commands due to theunexpected data in the EEPROM unused space.

EEPROM Address EEPROM Contents0 Address [9:2] (1S Write Command)1 Data [31:24]2 Data [23:16]

3 Data [15:8]4 Data [7:0]5 Address [9:2] (2n Write Command)6 Data [31:24]7 Data [23:16]8 Data [15:8]9 Data [7:0]: :: :: :

Table 2. EEPROM Data Format


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3-2. EEPROM Write Command ExamplesThe following are some examples of the EEPROM write commands,

3-2-1. Configure Port 0/Port 1 MAC Addresses and Enable PHY0/PHY1Addr[9:2] Data[31:24] Data[23:16] Data[15:8] Data[7:0] EEPROM Write Command8C 56

Port0 MACAdd[23:16]

78Port0 MACAdd[31:24]


ABPort0 MACAdd[47:40]

Set Port 0 MAC address 12 34 56 7890 ABWrite 0x567890AB toMAC register address 0x230(i.e. 0x8C * 4 =0x230)

8D 00 00 12Port0 MAC

Add[7:0]

34Port0 MAC

Add[15:8]

Write 0x00001234 toMAC register address 0x234

(i.e. 0x8D * 4 =0x234)9C CC

Port1 MACAdd[23:16]

DDPort1 MACAdd[31:24]

EEPort1 MACAdd[39:32]

FFPort1 MACAdd[47:40]

Set Port 1 MAC address AA BB CCDD EE FFWrite 0xCCDDEEFF toMAC register address 0x270(i.e. 0x9C * 4 =0x270)

9D 00 00 AAPort1 MACAdd[7:0]

BBPort1 MACAdd[15:8]

Write 0x0000AABB toMAC register address 0x274(i.e. 0x9D * 4 =0x274)

01 11Port 1 PHY

ID

01 10Port 0 PHY

ID

11 Enable PHY0 and PHY1Set PHY ID 0 =10000

Set PHY ID 1 =10001Enable PHY Power Saving functionWrite 0x11011011 toMAC register address 0x004(i.e. 0x01 * 4 =0x004)

50 33 00 11Port 1 PHYID

10Port 0 PHYID

Enable switch Auto-polling functionWrite 0x33001110 toMAC register address 0x140(i.e. 0x50 * 4 =0x140)

00 84 14 94 35 The EEPROM Write End Command


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3-2-2. Indirectly Write PHY0/PHY1 Registers through MDIO Interface

Addr[9:2] Data[31:24] Data[23:16] Data[15:8] Data[7:0] EEPROM Write Command

0F 90{010,10000PHY ID}

04PHYRegisterAddress

05Data[15:8]

E1Data[7:0]

Indirectly Write 0x05E1 to PHY0ANAR register (address 0x04)(PHY0 ID 0x10) through MDIOinterfaceWrite 0x900405E1 toMAC register address 0x03C(i.e. 0x0F * 4 =0x03C)

0F 91{010,10001PHY ID}

04PHYRegisterAddress

05Data[15:8]

E1Data[7:0]

Indirectly Write 0x05E1 to PHY1ANAR register (address 0x04)(PHY0 ID 0x11) through MDIOinterfaceWrite 0x910405E1 toMAC register address 0x03C(i.e. 0x0F * 4 =0x03C)


3-2-3. Set PCI Vendor/Device and Sub-Vendor/Sub-Device IDs (for AX88742 only)Addr[9:2] Data[31:24] Data[23:16] Data[15:8] Data[7:0] EEPROM Write CommandBD 74 20 12 5B Set PCI Vendor ID to 0x125B and

Device ID to 0x7420Write 0x7420125B toMAC register address 0x2F4(i.e. 0xBD * 4 =0x2F4)

BE 74 20 12 5B Set PCI subsystem Vendor ID to0x125B and subsystem Device ID to0x7420Write 0x7420125B toMAC register address 0x2F8(i.e. 0xBE * 4 =0x2F8)



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3-2-4. Configure L2 Routing Table for Source Port 0/Port 1


06 56MAC Add.Entry #1[23:16]

78MAC Add.Entry #1[31:24]


ABMAC Add.Entry #1[47:40]

Write the MAC address 12 34 56 7890 AB to the L2 Routing Table entryfor Source Port 0Write 0x567890AB toMAC register address 0x018(i.e. 0x06 * 4 =0x018)

07 80 10 12MAC Add.Entry #1[7:0]


Write 0x80101234 toMAC register address 0x01C(i.e. 0x07 * 4 =0x01C)

06 CCMAC Add.Entry #2[23:16]

DDMAC Add.Entry #2[31:24]

EEMAC Add.Entry #2[39:32]

FFMAC Add.Entry #2[47:40]

Write the MAC address AA BB CCDD EE FF to the L2 Routing Tableentry for Source Port 1Write 0xCCDDEEFF toMAC register address 0x018(i.e. 0x06 * 4 =0x018)

07 80 11 AAMAC Add.Entry #2[7:0]

BBMAC Add.Entry #2[15:8]

Write 0x8011AABB toMAC register address 0x01C(i.e. 0x07 * 4 =0x01C)



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3-2-5. Configure 802.1Q VLAN Entry


04 FC 40 00 00 Enable 802.1Q Port-base VLANWrite 0xFC400000 toMAC register address 0x010(i.e. 0x04 * 4 =0x010)

24 00 07 FF CF Set VLAN Entry 0Set Port 0/1/2 to the same VLANgroup with VLAN ID 4095 (0xFFF)and Port 0 with VLAN Tag, Port 1/2without VLAN TagWrite 0x0007FFCF toMAC register address 0x090(i.e. 0x24 * 4 =0x090)

25 00 04 14 0B Set VLAN Entry 1Set Port 0/1 to the same VLANgroup with VLAN ID 80 (0x050) andPort 0 with VLAN Tag, Port 1without VLAN TagWrite 0x0004140B toMAC register address 0x094(i.e. 0x25 * 4 =0x094)

26 00 04 0C 0D Set VLAN Entry 2SetPort 0/2 to the same VLANgroup with VLAN ID 48 (0x030) and

Port 0 with VLAN Tag, Port 2without VLAN TagWrite 0x00040C0D toMAC register address 0x098(i.e. 0x26 * 4 =0x098)



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3-2-6. Configure Non-802.1Q Port-Based VLAN Entry


04 FC 10 00 00 Enable Non-802.1Q Port-basedVLANWrite 0xFC100000 toMAC register address 0x010(i.e. 0x04 * 4 =0x010)

08 03 65 00 00 Set Port 0/Port 2 to group 1 and setPort 1/Port 2 to group 2Write 0x03650000 toMAC register address 0x020(i.e. 0x8 * 4 =0x020)



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3-2-7. Configure 802.1P QoS Mapping Table for Port 0/1/2


04 FC 20 00 00 Enable 802.1P QoS FunctionWrite 0xFC200000 toMAC register address 0x010(i.e. 0x04 * 4 =0x010)

81 00 00 FA 50 Set Port 0 QoS Mapping TableMapping QoS Priority values [0:7] to4 internal queues [0:3] for Port 0Write 0x0000FA50 toMAC register address 0x204(i.e. 0x81 * 4 =0x204)

91 00 00 FA 50 Set Port 1 QoS Mapping TableMapping QoS Priority values [0:7] to4 internal queues [0:3] for Port 1Write 0x0000FA50 toMAC register address 0x244(i.e. 0x91 * 4 =0x244)

A1 00 00 FA 50 Set Port 2 QoS Mapping TableMapping QoS Priority values [0:7] to4 internal queues [0:3] for Port 2Write 0x0000FA50 toMAC register address 0x284(i.e. 0xA1 * 4 =0x284)



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3-2-8. Configure IGMP Multicast IP Group Table Entry


04 FC 00 20 00 Enable IGMP FunctionWrite 0xFC002000 toMAC register address 0x010(i.e. 0x04 * 4 =0x010)

54 91 02 03 04 Set IGMP Entry 0Set Port 0 to Multicast IP 225.2.3.4GroupWrite 0x91020304 toMAC register address 0x150(i.e. 0x54 * 4 =0x150)

55 B5 06 07 08 Set IGMP Entry 1Set Port 0/1 to Multicast IP 229.6.7.8GroupWrite 0xB5060708 toMAC register address 0x154(i.e. 0x55 * 4 =0x154)

56 DF 0A 0B 0C Set IGMP Entry 2Set Port 0/2 to Multicast IP239.10.11.12 GroupWrite 0xDF0A0B0C toMAC register address 0x158(i.e. 0x56 * 4 =0x158)



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3-2-9. Configure RX Rate Limit Function


80 00 01 01 99 Configure Port 0 MAC and enableRx Rate Limit functionWrite 0x00010199 toMAC register address 0x200(i.e. 0x80 * 4 =0x200)

90 00 01 01 99 Configure Port 1 MAC and enableRx Rate Limit functionWrite 0x00010199 toMAC register address 0x240(i.e. 0x90 * 4 =0x240)

A0 00 01 20 00 Configure Port 2 MAC and enableRx Rate Limit functionWrite 0x00012000 toMAC register address 0x280(i.e. 0xA0 * 4 =0x280)

87 FF FF 00 01 Set Port 0 Rx Rate LimitWrite 0xFFFF0001 toMAC register address 0x21C(i.e. 0x87 * 4 =0x21C)

97 FF FF 00 01 Set Port 1 Rx Rate LimitWrite 0xFFFF0001 toMAC register address 0x25C(i.e. 0x97 * 4 =0x25C)

A7 FF FF 00 01 Set Port 2 Rx Rate LimitWrite 0xFFFF0001 toMAC register address 0x29C(i.e. 0xA7 * 4 =0x29C)



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3-2-10. Configure TX Rate Limit Function

80 00 02 01 99 Configure Port 0 MAC and enable

Tx Rate Limit functionWrite 0x00020199 toMAC register address 0x200(i.e. 0x80 * 4 =0x200)

90 00 02 01 99 Configure Port 1 MAC and enableTx Rate Limit functionWrite 0x00020199 toMAC register address 0x240(i.e. 0x90 * 4 =0x240)

A0 00 02 20 00 Configure Port 2 MAC and enableTx Rate Limit functionWrite 0x00022000 to

MAC register address 0x280(i.e. 0xA0 * 4 =0x280)

87 00 01 FF FF Set Port 0 Tx Rate LimitWrite 0x0001FFFF toMAC register address 0x21C(i.e. 0x87 * 4 =0x21C)

97 00 01 FF FF Set Port 1 Tx Rate LimitWrite 0x0001FFFF toMAC register address 0x25C(i.e. 0x97 * 4 =0x25C)

A7 00 01 FF FF Set Port 2 Tx Rate Limit

Write 0x0001FFFF toMAC register address 0x29C(i.e. 0xA7 * 4 =0x29C)



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4.EEPROM FAQs4-1. Do we need to register our own PCI Vendor ID/Device ID and

Subsystem Vendor ID/Subsystem Device ID for AX88742 applications?

The Vendor ID and Device ID registers identify the device, and are commonly called the PCI ID.The 16-bit vendor ID is allocated by the PCI SIG (http://www.pcisig.com/). The 16-bit deviceID is then assigned by the vendor. There is an ongoing project to collect all known Vendor andDevice IDs. (Seehttp://www.pcidatabase.com/ for more details.)

The Subsystem Vendor ID and the Subsystem Device ID further identify the device. TheVendor ID is that of the chip manufacturer, and the Subsystem Vendor ID is that of the cardmanufacturer. The Subsystem Device ID is assigned by the subsystem vendor, but is assigned

from the same number space as the Device ID.

The answer to above question really depends on the real requirements of your AX88742 targetapplications. If your AX88742 application doesnt have special requirements and can work withthe standard AX88742 drivers, you can consider using ASIXs AX88742 default PCI Vendor ID(125Bh)/Device ID (7420h) and Subsystem Vendor ID (125Bh)/Subsystem Device ID (7420h)directly.

4-2. Do I have to assign two unique MAC addresses for Port 0 and Port 1 ofevery ASIX Multi-Port Ethernet Controller based devices?

Yes, every Ethernet device must have a unique MAC address. Users should assign two uniqueMAC addresses in the EEPROM for Port 0 and Port 1 of every ASIX Multi-Port EthernetController based devices.

You should refer to Section 4-2 to register a block of MAC addresses for your company.

4-3. How to register a MAC/Ethernet address from IEEE-SA?You must first have an OUI or an IAB, to which you then append 24 or 12 bits respectively, in away that makes the resulting 48-bit number unique, i.e., your 24 or 12 bits must be unique withinyour organization, which will require coordination among all the users of your organization'sOUI or IAB. Please visit the IEEE-SA web site(http://standards.ieee.org/regauth/registry_OUI.html) for details.
http://www.pcisig.com/http://www.pcidatabase.com/http://standards.ieee.org/regauth/registry_OUI.htmlhttp://standards.ieee.org/regauth/registry_OUI.htmlhttp://www.pcidatabase.com/http://www.pcisig.com/


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4-4. Is the EEPROM device required for AX88613 applications?The AX88613 supports 8-bit mode 93C46/93C56/93C66 EEPROM. The EEPROM is optional

for AX88613 if the MCU on your target platform supports the SPI interface to configureAX88613 registers through AX88613 SPI interface directly.

Otherwise, you should implement the EEPROM on your AX88613 applications to configureAX88613 to reach the specific requirements (such as routing table, VLAN, etc.) of yourAX88613 applications.

4-5. How to program the EEPROM content on AX88613 applications?The following are the recommended solutions to program the EEPROM on AX88613applications.

1. You can program AX88613 EEPROM content by AX88613 ECR register (Address 0x144)through the SPI interface. Please refer to Section 5.1.30 EEPROM Control Register (ECR)of AX88613 datasheet for more details.

2. You can use the GPIO pins of your MCU to simulate the SPI interface and create thenecessary SPI command signals through these MCUs GPIO pins. Please refer to Section 4.4Serial Peripheral Interface (SPI) of AX88613 datasheet for more details.

3. If your MCU doesn't support either SPI interface or GPIO pins, you can consider pre-programming the EEPROM content by the universal programmer or the EEPROM

manufacturer.


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Appendix 1. AX88742 EEPROM Reference SettingThe EEPROM device is optional for the AX88742 application and can be used to store the

unique MAC addresses for AX88742 Port 0 and Port 1. If the Port 0 and Port 1 MAC addressescan be stored on the Flash memory of your embedded system and your AX88742 application canuse the AX88742 default PCI Vendor ID (0x125B)/Device ID (0x7420), you can considereliminating the EEPROM device on your AX88742 application. The AX88742 driver canconfigure the rest of initialization process later. The following is an example of the AX88742EEPROM default setting.

Addr[9:2] Data[31:24] Data[23:16] Data[15:8] Data[7:0] EEPROM Write Command01Reg:004

11 01 10 01 Set Port 0/Port 1 internal PHY tonormal operation modeWrite 0x11011001 to MAC registeraddress 0x004(i.e. 0x01 * 4 =0x004)

8CReg:230

C6Port0 MACAdd[23:16]




Set Port 0 MAC address 00 0E C6 0012 38Write 0xC6001238 MAC address toMAC register address 0x230(i.e. 0x8C * 4 =0x230)Note 0x000EC6 is ASIX Electronicscompany MAC address. You shouldreplace with your own companyMAC address value.

8D

Reg:234

00 00 00

Port0 MACAdd[7:0]

0E

Port0 MACAdd[15:8]

Write 0x0000000E to

MAC register address 0x234(i.e. 0x8D * 4 =0x234)

9CReg:270





Set Port 1 MAC address 00 0E C6 0012 39Write 0xC6001239 MAC address toMAC register address 0x270(i.e. 0x9C * 4 =0x270)

9DReg:274

00 00 00Port1 MACAdd[7:0]

0EPort1 MACAdd[15:8]

Write 0x0000000E toMAC register address 0x274(i.e. 0x9D * 4 =0x274)

BDReg:2F4

74 20 12 5B Set PCI Vendor ID to 0x125B andDevice ID to 0x7420Write 0x7420125B toMAC register address 0x2F4(i.e. 0xBD * 4 =0x2F4)

BEReg:2F8

74 20 12 5B Set PCI subsystem Vendor ID to0x125B and subsystem Device ID to0x7420Write 0x7420125B toMAC register address 0x2F8(i.e. 0xBE * 4 =0x2F8)


Table 3.

AX88742 EEPROM Reference Setting


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Appendix 2. AX88783/AX88782 EEPROM Reference SettingThe EEPROM device is optional for the AX88783/AX88782 applications and can be used tostore the unique MAC addresses for AX88783/AX88782 Port 0 and Port 1. If the Port 0 and Port1 MAC addresses can be stored on the Flash memory of your embedded system, you canconsider eliminating the EEPROM device on your AX88783/AX88782 applications. TheAX88783/AX88782 driver can configure the rest of initialization process later. The following isan example of the AX88783/AX88782 EEPROM default setting.



8CReg:230





Set Port 0 MAC address 00 0E C6 0012 38Write 0xC6001238 MAC address toMAC register address 0x230(i.e. 0x8C * 4 =0x230)Note 0x000EC6 is ASIX Electronicscompany MAC address. You shouldreplace with your own companyMAC address value.

8D

Reg:234

00 00 00

Port0 MACAdd[7:0]

0E

Port0 MACAdd[15:8]

Write 0x0000000E to

MAC register address 0x234(i.e. 0x8D * 4 =0x234)

9CReg:270





Set Port 1 MAC address 00 0E C6 0012 39Write 0xC6001239 MAC address toMAC register address 0x270(i.e. 0x9C * 4 =0x270)

9DReg:274

00 00 00Port1 MACAdd[7:0]

0EPort1 MACAdd[15:8]

Write 0x0000000E toMAC register address 0x274(i.e. 0x9D * 4 =0x274)


Table 4. AX88783/AX88782 EEPROM Reference Setting


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Appendix 3. AX88613 EEPROM Reference SettingThe EEPROM device is optional for AX88613 if your MCU supports the SPI interface and theMAC addresses of Port 0 and Port 1 can be stored on the Flash memory of your embeddedsystem. In this case, your MCU firmware can read the MAC addresses of Port 0 and Port 1 fromthe Flash memory and then configure proper AX88613 registers through the SPI interface fornormal operation. Please refer to Section 4.4 of AX88613 datasheet for more details about theAX88613 SPI Data Write command format.

A3-1. Port 2 in MII Mode with External PHY (default setting for demo board)The following is an example of the AX88613 EEPROM setting when the AX88613 Port 2 wasset to MII mode with external PHY. The EEPROM of AX88613 demo board is set to MII mode

by default.

AX88613 Port 0 & Port 1 in internal PHY mode, Port 2 in MII mode with external PHY



37Reg:0DC

03 00 01 04 Set PHY0 & PHY1 LED DisplayMode

Write 0x03000104 toMAC register address 0x0DC(i.e. 0x37* 4 =0x0DC)

7CReg:1F0

40 0C 00 00 Set Port 2 to MII modeWrite 0x400C0000 toMAC register address 0x1F0(i.e. 0x7C* 4 =0x1F0)

00 00 00 00 00 Delay (No operation)52Reg:148

07 FF FF FF Delay about 1.3 second(0x07FFFFFF 134,217,727 *10ns =1.3 sec) to wait for PHYinitialization completionWrite 0x07FFFFFF toMAC register address 0x148(i.e. 0x52* 4 =0x148)Note: AX88613 BLCR register(address 0x148) works as a delaytime counter (in 10ns unit) duringauto-loading EEPROM operation.Users can fine tune this delay timecounter to reach the realrequirements on your AX88613target applications.


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0FReg:03C

90 04 05 E1 Write PHY0 ANAR PHY registerthrough MDIO Read/WriteControl register

Write 0x900405E1 toMAC register address 0x03C(i.e. 0x0F* 4 =0x03C)Note: The default PHY address ofPHY 0 is 0x10

00 00 00 00 00 Delay for MDIO process(No operation)

0FReg:03C

91 04 05 E1 Write PHY1 ANAR PHY registerthrough MDIO Read/WriteControl registerWrite 0x910405E1 to

MAC register address 0x03C(i.e. 0x0F* 4 =0x03C)Note: The default PHY address ofPHY 1 is 0x11


0FReg:03C

95[28:24]:ExternalPHY ID0x15

04 05 E1 Write Port 2 external PHY ANARPHY register through MDIORead/Write Control registerWrite 0x950405E1 toMAC register address 0x03C(i.e. 0x0F* 4 =0x03C)Note: Assume the PHY address ofPort 2 external PHY is 0x15


0FReg:03C

90 00 33 00 Restart PHY0 auto-negotiationfunction through MDIORead/Write Control registerWrite 0x90003300 toMAC register address 0x03C(i.e. 0x0F* 4 =0x03C)

00 00 00 00 00 Delay for MDIO process

(No operation)0FReg:03C




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0FReg:03C

95[28:24]:External

PHY ID0x15

00 33 00 Restart Port 2 external PHY auto-negotiation function throughMDIO Read/Write Control

registerWrite 0x95003300 toMAC register address 0x03C(i.e. 0x0F* 4 =0x03C)

50Reg:140

77 15[20:16]:ExternalPHY ID0x15

11 10 Enable auto-polling function oninternal PHY 0/PHY1 and Port 2external PHYWrite 0x77151110 toMAC register address 0x140(i.e. 0x50 * 4 =0x140)


Table 5. AX88613 EEPROM Reference Setting (Port 2 in MII mode with external PHY)


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A3-2. Port 2 in Reverse MII ModeThe following is an example of the AX88613 EEPROM setting when the AX88613 Port 2 was

set to Reverse MII mode.

AX88613 Port 0 & Port 1 in internal PHY mode, Port 2 in Reverse MII mode


01Reg:004


37Reg:0DC



7CReg:1F0

04 08 00 00 Set Port 2 to Reverse MII modeWrite 0x04080000 toMAC register address 0x1F0(i.e. 0x7C* 4 =0x1F0)


07 FF FF FF Delay about 1.3 second(0x07FFFFFF 134,217,727 *10ns =1.3 sec) to wait for PHY

initialization completionWrite 0x07FFFFFF toMAC register address 0x148(i.e. 0x52* 4 =0x148)Note: AX88613 BLCR register(address 0x148) works as a delaytime counter (in 10ns unit) duringauto-loading EEPROM operation.Users can fine tune this delay timecounter to reach the realrequirements on your AX88613

target applications.0FReg:03C

90 04 05 E1 Write PHY0 ANAR PHY registerthrough MDIO Read/WriteControl registerWrite 0x900405E1 toMAC register address 0x03C(i.e. 0x0F* 4 =0x03C)Note: The default PHY address ofPHY 0 is 0x10



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0FReg:03C




0FReg:03C

90 00 33 00 Restart PHY0 auto-negotiationfunction through MDIORead/Write Control registerWrite 0x90003300 to

MAC register address 0x03C(i.e. 0x0F* 4 =0x03C)00 00 00 00 00 Delay for MDIO process




68Reg:1A0

C0 00 00 12 Set Port 2 slave MDC/MDIO PHYaddress to 0x12 (for Rev-MIIinterface)Write 0xC0000012 toMAC register address 0x1A0(i.e. 0x68 * 4 =0x1A0)

A0Reg:280

00 00 01 99 Enable Port 2 MAC function andforce to 100Mbps Full-duplex modeWrite 0x00000199 toMAC register address 0x280(i.e. 0xA0 * 4 =0x280)

50Reg:140 33 00 11 10 Enable auto-polling function oninternal PHY0/PHY1Write 0x33001110 toMAC register address 0x140(i.e. 0x50 * 4 =0x140)


Table 6. AX88613 EEPROM Reference Setting (Port 2 in Rev-MII mode)


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A3-3. Port 2 in RMII Mode with External PHYThe following is an example of the AX88613 EEPROM setting when the AX88613 Port 2 wasset to RMII mode with external PHY.

AX88613 Port 0 & Port 1 in internal PHY mode, Port 2 in RMII mode with external PHY


01Reg:004


37Reg:0DC

03 00 01 04 Set PHY0 & PHY1 LED DisplayModeWrite 0x03000104 to

MAC register address 0x0DC(i.e. 0x37* 4 =0x0DC)

7CReg:1F0

40 08 00 04 Set Port 2 to RMII mode, Low-Port,Enable RMII clock generator, MDCI/O PAD SelectWrite 0x40080004 toMAC register address 0x1F0(i.e. 0x7C* 4 =0x1F0)

7CReg:1F0

40 08 40 44 Enable Port 2 RMII interface andoutput 50MHz clock signals toP2_REFCLKO (pin #54)Write 0x40084044 toMAC register address 0x1F0(i.e. 0x7C* 4 =0x1F0)Note: Please set bit14(CLK50_EN) when yourAX88613 application needs tooutput 50MHz clock signals fromAX88613 P2_REFCLKO pin.


07 FF FF FF Delay about 1.3 second(0x07FFFFFF 134,217,727 *10ns =1.3 sec) to wait for PHYinitialization completionWrite 0x07FFFFFF toMAC register address 0x148(i.e. 0x52* 4 =0x148)Note: AX88613 BLCR register(address 0x148) works as a delaytime counter (in 10ns unit) duringauto-loading EEPROM operation.Users can fine tune this delay timecounter to reach the realrequirements on your AX88613target applications.


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0FReg:03C




0FReg:03C

91 04 05 E1 Write PHY1 ANAR PHY registerthrough MDIO Read/WriteControl registerWrite 0x910405E1 toMAC register address 0x03C

(i.e. 0x0F* 4 =0x03C)Note: The default PHY address ofPHY 1 is 0x11


0FReg:03C

95[28:24]:ExternalPHY ID0x15

04 05 E1 Write Port 2 external PHY ANARPHY register through MDIORead/Write Control registerWrite 0x950405E1 toMAC register address 0x03C(i.e. 0x0F* 4 =0x03C)Note: Assume the PHY address of

Port 2 external PHY is 0x1500 00 00 00 00 Delay for MDIO process




0FReg:03C




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0FReg:03C

95[28:24]:External

PHY ID0x15

00 33 00 Restart Port 2 external PHY auto-negotiation function throughMDIO Read/Write Control

registerWrite 0x95003300 toMAC register address 0x03C(i.e. 0x0F* 4 =0x03C)

50Reg:140

77 15[20:16]:ExternalPHY ID0x15

11 10 Enable auto-polling function oninternal PHY 0/PHY1 and Port 2external PHYWrite 0x77151110 toMAC register address 0x140(i.e. 0x50 * 4 =0x140)


Table 7. AX88613 EEPROM Reference Setting (Port 2 in RMII mode with external PHY )


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A3-4. Port 2 in Reverse RMII ModeThe following is an example of the AX88613 EEPROM setting when the AX88613 Port 2 was

set to Reverse RMII mode.

AX88613 Port 0 & Port 1 in internal PHY mode, Port 2 in Reverse RMII mode



37Reg:0DC



7CReg:1F0

00 08 00 04 Set Port 2 to RMII mode, Low-Port,Enable RMII clock generatorWrite 0x00080004 toMAC register address 0x1F0(i.e. 0x7C* 4 =0x1F0)

7CReg:1F0

00 08 40 44 Enable Port 2 RMII interface andoutput 50MHz clock signals toP2_REFCLKO (pin #54)Write 0x00084044 toMAC register address 0x1F0(i.e. 0x7C* 4 =0x1F0)Note: Please set bit14(CLK50_EN) when yourAX88613 application needs tooutput 50MHz clock signals fromAX88613 P2_REFCLKO pin.


07 FF FF FF Delay about 1.3 second(0x07FFFFFF 134,217,727 *

10ns =1.3 sec) to wait for PHYinitialization completionWrite 0x07FFFFFF toMAC register address 0x148(i.e. 0x52* 4 =0x148)Note: AX88613 BLCR register(address 0x148) works as a delaytime counter (in 10ns unit) duringauto-loading EEPROM operation.Users can fine tune this delay timecounter to reach the real

requirements on your AX88613target applications.


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0FReg:03C




0FReg:03C




0FReg:03C



0FReg:03C



68

Reg:1A0

C0 00 00 12 Set Port 2 slave MDC/MDIO PHY

address to 0x12 (for Rev-RMIIinterface)Write 0xC0000012 toMAC register address 0x1A0(i.e. 0x68 * 4 =0x1A0)

A0Reg:280

00 00 01 99 Enable Port 2 MAC function andforce to 100Mbps Full-duplex modeWrite 0x00000199 toMAC register address 0x280(i.e. 0xA0 * 4 =0x280)


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50Reg:140

33 00 11 10 Enable auto-polling function oninternal PHY0/PHY1Write 0x33001110 to

MAC register address 0x140(i.e. 0x50 * 4 =0x140)00 84 14 94 35 The EEPROM Write End Command

Table 8. AX88613 EEPROM Reference Setting (Port 2 in Rev-RMII mode)


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ASIX Multi-Port Ethernet ControllerEEPROM/Manufacture User Guide

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ASIX MultiPort Ethernet EEPROM UserGuide v101 3

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