asic lecture 9~10 chapter_3

8/20/2019 asic lecture 9~10 chapter_3

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Chapter 3

EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John SebastianSmith, Addison Wesley, 1997

ASIC Library Design

Application-Specific Integrated CircuitsMichael John Sebastian Smith

Addison Wesley, 1997


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ASIC Library Design

ASIC design is usually performed using a predefined and

precharacterized library of cells

In designing this library, the original designer had to optimize

speed and area without knowing the actual application that

the cells will be used for - i.e., how large a load they will be


wire load

fanout load

Being aware of the source and effect of these trade-offs will

make it easier to understand how to optimally design usingthe library cells


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Model of CMOS Inverter with ParasiticResistances and Capacitances


Figure 3.1 A model for CMOS logic delay. (a) A CMOS inverter with load capacitance. (b) Input and output waveforms

showing the definition of falling propagation delay tPDF. (c) The switch model of the inverter showing parasitic

resistances and capacitances.


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Effect of Load Capacitance on Inverter Performance

Figure 3.3 Simulation of an inverter driving a variable number of

gates on its output



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Parasitic Capacitances of a CMOSTransistor

Figure 3.4 Transistor parasiticcapacitance. (a) An N-

channel MOS transistor

with gate length L and

width W. (b) The

components of the gate

capacitance. (c)

Approximating

capacitances with planar

components. (d) The

components of the diffusion

capacitance. (e)-(h) The


dimensions of the gate,

overlap, and sidewall

capacitances.


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VDD VDD

RPon

VOH = VDD

CMOS Inverter: Steady State Response


Vout

Vout

Vin = VDD Vin = 0

RNon

VOL= 0

VM = RPon

)f(RNon

,

RNon 1/WN

RPon 1/WP

Figures from material provided with Digital Integrated Circuits, A DesignPerspective, by Jan Rabaey, Prentice Hall, 1996


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Vout

4

5

NMOS off

PMOS lin

NMOS sat

PMOS lin

CMOS Inverter VTC


Vin1 2 3 4 5

1

2

3

NMOS lin

PMOS off

NMOS sat

PMOS sat

NMOS lin

PMOS sat



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The Ideal Gate

V out

=


V in

g=

Ro = 0

Vm = Vdd/2



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VDD

Balanced CMOS Inverter

Assume that due to differences in µp and µn, for a minimum

sized transistor, Rp = 2RnFor a balanced inverter we want RP = RN, so in this case, WPmust be 2WN


Vin Vout

CL

P P =

WN/LN = 2/1


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Logical Effort


Figure 3.8 Logical effort. (a) The input capacitance looking into the input capacitance of a minimum size inverter. (b) Sizing a

logic cell’s transistors to have the same delay as a minimum size inverter. (c) The logical effort of a cell is Cin/Cinv.


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Logical Effort Of a Complex Gate


Figure 3.10 An AOI221 cell with logical effort vector g=(8/3, 8/3, 7/3).


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The Basic Trade-off

to other gates (fanout)





buffer Which is faster?

asic lecture 9~10 chapter_3

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