APPLICATIONS AROUND THE CONNECTED CARsoiconsortium.eu/wp-content/uploads/2019/03/CEA...3D STACKED...

APPLICATIONS AROUND THE CONNECTED CAR

Emmanuel Sabonnadière, CEO, Leti-CEA Tech

SOI Silicon Valley Symposium - San Jose (USA) – 2019, April 9th

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Since 1967

France, USA, Japan

2,000 People

> 2,760 Patents in Portfolio

350 Industrial Partners

> 65 Startups Created

10,000 m² Cleanroom 200-300mm

315 M€ Budget (85% from R&D contracts)

Grenoble (FR)

LETI, FOR 50 YEARS, THE PLACE TO BE TO INVENT TOMORROW©

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SOI Silicon Valley Symposium – San Jose (USA) – 2019, April 9th

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Compute

Commu-nicate

Store

Sense

Display

Secure

Circuits & Systems

Hardware

Technologies

• More Moore (Scaling) – HPC & serversFDSOI, Stacked GAA Nanowires, CoolCubeTM

• More than Moore – DiversificationMEMS Sensors & Actuators, 3D integrationImagers & Displays, Si PhotonicsRFPower electronics

• Circuit Design• System Integration• Architecture Development

LETI, A CORNERSTONE FOR THE INNOVATION

IN THE SEMICONDUCTOR & ICT INDUSTRY

Optimized power


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GRENOBLE

ALBANY, NY

Crolles

Dresden

From research to production 28FDSOI 22FDX 12FDX

18FDSOI


LETI, A PIONNEER IN THE SOI INDUSTRY

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EUROPE HAS 37% OF AUTOMOTIVE SEMICONDUCTOR MARKET SHARE

AND HAS STRENGTH IN ALL DOMAINS

http://www.eetimes.com/document.asp?doc_id=1329375

Source: IHS

Source: Market Realist – Dec 2015


LETI, AN EUROPEAN ACTOR IN THE AUTOMOTIVE INDUSTRY

http://www.eetimes.com/document.asp?doc_id=1329375

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TRIPLEPLAY

FOR CARS ?Electrification

Digitalization

Robotization

A NEW ERA FOR AUTOMOTIVE INDUSTRY

BASED ON

SEMICONDUCTOR

TECHNOLOGY !

▪ 80 % of all core innovation

▪ 50% of vehicle production

cost in 2030 (30% in 2015)

▪ Shorter time gap

consumer vs automotive


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LETI, AN R&D ACTOR IN THE CONNECTED CAR ECOSYSTEM


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• 3 years European Project Budget > 100M€

• Opportunity to Carry European Autonomous driviNg further with FDSOI

technology up to 12nm node and beyond

Based on the innovative FDSOI technology, OCEAN12 will develop new processors and applications

designs that leverage Fully Depleted Silicon On Insulator (FD-SOI) technology to offer the industry’s lowest

power consuming processor and components, especially for following applications.


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Making the leap from physical information to data interpretation

AUTONOMOUS EFFICIENTSMART & CONNECTED

High precision & smart sensing

Embedded Processing & Fusion

New computing paradigms and Deep Learning

Ultra-low power computing nodes & framework

Ultra-low power connectivity for Internet Of Things

Energy management and scavenging

Security

We c

over

all

aspects

...

CONNECTED CAR « AT THE EDGE »


| 10SOI Silicon Valley Symposium l April 9, 2019 l San Jose

VISION “AT THE EDGE”

High precision & smart sensing


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HARDWARE ACCELERATORS FOR ADAS

• Reconfigurable processor

• Design and Integration of reconfigurable accelerator in

ARM11-based STM FDSOI SoC

• Reconfigurable connection of heterogeneous computing node- Patented IPs on flexible filtering, classification operators,

morphomathematical operations, …

• 50 GOPS @ 200 MHz

• 3D perception

• REEFS : flexible coprocessor for stereovision processing

- supporting various application constraints

- manageable on the fly

- Image resolution, maximum disparity range

- Disparity processing methods (local, semi-global)

- Input image filtering, disparity map filtering

- 286 GOP@200MHz

MemoryController

cluster

clusterclustercluster

clusterclusterOn-Chipmemory

Reconfigurable Image processor

Video Pipeline

Sensor interface

AX I b rid ge

ARM11 Core

STxP70Micro-controller

Progmem

Datamem

Off chip DDRmemory

STNOC

IR/CMOSsensor

Reconfigurable Processeur for ADAS applications

Reconfigurable component for stereovision systems


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3D STACKED RETINA WITH SPIKING NEURAL NETWORKS

RETINE: image sensor + 3D stacked SIMD processors• Image sensor: 70% fill factor, 12 µm pixel, >5000 fps

• SIMD processors: 192 units, distributed memory, 11.7 MOPS/mW

• 1 k instructions / pixel @ 1000 fps

Preprocessing

Asynchronous AER coding

Lens

Sensor layer

130nm SOI

Passive interposer or PCB

➔ x100 computing power, x10 energy efficiency, /15 processing latency

Retine ChipALTIS 130nm, CuCu bonding

Processor array die

Circuit demonstrator “Retine”

L1@130 nm / L2@130 nm

IC size : 160 mm²

- Sensor : 192x256 @ 5500 fps /

768x1024 @ 60 fps

- Processing : 72 GOPS (192 SIMD

processors)

L2

L1

Goal: to meet the performances and flexibility of the human eye for

image analysis, inspection of defaults, detection of problems,

…Making an “intelligent retina”


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PROPHESEECOMPANY KEY STRENGTHS

• Based in Orsay, France

• Specializes in real-time application development

• Offers integrated solutions

• Fully integrated solutions

• Based on strong expertise from CEA, Areva, Delphi

and Schneider Electric

Start-up creation, automotive domain2011

OASIS initiation phase1995

PHAR-OS automotive & infrastructures2003

AREVA Deterministic RT

instrumentation & control

VALEO

DELPHI

RENAULT

Schneider

Fully functional and awarded demonstrators2010

2 successful demonstrators,

Electron D’Or award

€19M raised2018

first device to combine Prophesee’s patented sensor and AI algorithms2016



SAFE ASSESMENT “AT THE EDGE”

Embedded Processing & Fusion


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« SAFETY COPILOT »


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All driving

tasks

“Engaged”

Warning

“Feet Off”

assistance

Level 0 Level 1 Level 2

Human monitors environment

All driving tasks

Only some

driving

modes

“Eyes Off”

takeover

requests

“Hands Off”

Level 3 Level 4 Level 5

Vehicle monitors environment

Perception: Objet fusion

Object Detection

Perception: Map fusion

obstacles and

free space are

monitored

NE

XT

NE

XT

PERCEPTION REQUIREMENTS

SIGMA Fusion

2018

2017


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SAFE PERCEPTION

Radar

Vision

Lidar

GNSS

Computing & Decision: number

cruncher

Car actuation

Watchdog: embedded on safe

microcontroller (ASIL-D standard)

SOTA AI

SIGMA Fusion Online real-time safety assessment

• Spatial queries from main system

• Guaranteed behavior over time

• Cost effective (no redundancy)

• Can be run on SAFE processors

“Trajectory is safe”



PROCESSING “AT THE EDGE”

Ultra-low power computing nodes & framework


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2019-2026

EuroHPC: A New Legal and

funding entity For Deploying in

Europe a world-class

supercomputing infrastructure

Supercomputing Infrastructure

Research & Innovation actions

https://eurohpc-ju.europa.eu/

25 founding

members

2015-2019

Core technologies

3D Integration

IP design

2017-2020

Novel IPs

Processor design

2018-2021

23 partners to develop

microprocessors for future

supercomputers

Advanced

Architecture

& Designs

LETI, IN THE HEART OF THE EUROPEAN COMPUTING EFFORT


https://www.cineca.it/

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LETI, PIONEER ON CHIPLETS ARCHITECTURE

96 cores compute fabric with 6 chiplets stacked on an active interposer<

System Architecture

Cache Coherent Compute Fabric with:

• 96 cores (MIPS32),

• 3 levels of caches,

• integrated power management

Design Technology

Heterogeneous 3D partitioning with:• 28nm FDSOI chiplets (x6)

• Low power compute fabric

• Wide voltage range (0.6V – 1.2V)

• Body biasing for logic boost & leakage ctrl

• 65nm active interposer

• Power unit (Switched Cap DC-DC conv.)

• Interconnect (Network-on-Chip)

• Test, clocking, thermal sensors, etc

µ-bumps

Ø 10 µm

Pitch 20 µm

TSV

Ø 10µm

Height 100µm

Symposium’2016

3DIC’2015

ISVLSI’2015

Performance targets• 100 GOPS

• 10 GOPS/Watt

• 25 Watts total

Ongoing validation:

• To execute full Linux onto 96

cores

Application


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Many-Core Architecture Integration Experiments in a Representative Avionics Environment

Engine Control (EC)

Hard real time

constraints

DAL A

DGEN Control

Application

Signal Processing Application

Health Monitoring (HM)

High Performance constraints

DAL E

FromTwo applications running separately

ToOne Kalray MPPA® processor

Average Phase

Subtraction

Resample Data

Resample Data

Challenges◼ Mixed-Criticality on a Many-Core

◼ Significant performance Increase◼ In Safe and Secure way

◼ Consume less Energy

On a 256 cores MPPA chip (BOSTAN)

XCOEUR – MIXED CRITICALITY IN MANY-CORE

Results◼ Segregation is ensured thanks to specific architecture configuration◼ HM performance speedup up to 35 times faster than single CPU execution

◼ In-depth MPPA® analysis is necessary for demonstration of determinism


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Multi & Many core architecture2005

Kalray Start-up creation2008

Starting date1990

Mixed criticity applications for avionics developed for Safran2016

COMPANY KEY STRENGTHS

• Based in Montbonnot (38)

• 65 employees

• Offices in Los Altos, CA

• Industry-leading ratio of computing power/energy

consumptions

• Time predictability and low latency

• Unique processing scalability

• High programmability

Launch of SIMD

architecture

activities

KALRAY

Creation of

the successful start-up

Kalray, with the key

product being the MPPA

® processors

architecture, a low

power yet capable of

advance computing

technology

Development of

programmable,

multi & many

core, parallel

architectures for

HPC

2 critical avionics

applications running

separately gathered on 1

MPPA® processor

Source : http://www.price-induction.com/dgen-engine/

$26M Investment for the 3rd generation of its microprocessors2017

Euronext IPO €43M raised2018


http://www.kalrayinc.com/

http://www.price-induction.com/dgen-engine/


ARTIFICIAL INTELLIGENCE “AT THE EDGE”

New computing paradigms and Deep Learning


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INFERENCE & LEARNING « AT THE EDGE »

Simple

sensor

Cloud computing

Deep Learning

Inference

Row Data

Ro

w D

ata

Co

mm

an

d

Multi-sensor

Data fusion

Pre-processing

Pre-processed

Data

Cyber-Physical Systems

Pre

-pro

ce

ss

ed

Da

ta

Co

nfi

gu

rati

on

Deep Learning

Inference

Knowledge

Multi-sensor

Behavior sensor

Co

op

era

tio

n

Bio-inspired

computing

Bio-inspired computing

LearningInference

Quantum Computing Edge AIIntegrated LidarSOI Silicon Valley Symposium - San Jose (USA) – 2019, April 9th

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LETI, A COMPLETE TOOL BOX FOR NEW AI APPLICATIONS


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DEEP NEURAL NETWORKS EXPLORATION PLATFORM

AppObjectRecognition/

Live object recognition

application

based on ILSVRC2012 (ImageNet)

dataset

AppFaceDetection/

Live face detection application,

with gender recognition

based on the IMDB-WIKI dataset

AppRoadDetection/

Simple road segmentation

application

based on the KITTI Road dataset

N2D2 is available at https://github.com/CEA-LIST/N2D2/

• Smallest dependencies and requirements among major frameworks:GCC 4.4 or Visual Studio 12 (2013) / OpenCV 2.0.0

• Easily extendable with a “plug-and-play” modular system for user-made modules

Development of efficient solutions for Deep Learning Inference

: Neural Network Design & Deployment

OpenMP

OpenCL

CUDA

HLS FPGA

Parallel CPU

GPUFPGA


https://github.com/CEA-LIST/N2D2/

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PNeuroASIC 500MHz is 7 times faster & 200 times more energy efficient than an embedded GPU<P-Neuro runs neural networks with x200 less power than embedded GPU

Need several applications could benefit from deep neural networks (DNN) but face the

challenge (processing, size, power) to run them on embedded systems

Fully-programmable energy efficient hardware accelerator for DNN

• Scalable: can be sized to fit the best area/performance

• Clustered and modular SIMD architecture

Our technology

• 50 instructions (control + computing)

• Easy programming through N2D2 platform

Achievements test chip is x200 more energy efficient than embedded GPU

• 28nm FDSOI

• 1.1 TOPS/Watt

• 0.126mm2 for a single cluster (8 Processing Elements)

• 500 MHz

P-Neuro architectureBenchmark on a DNN face extraction application

ENERGY EFFICIENT PROGRAMMABLE ACCELERATOR


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NEURAL COMPUTING ARCHITECTURES

Leti is part of the NeuRAM 3 European

collaborative research project for the development

of a FDSOI 28nm DynapSEL processor (Dynamic

Neuromorphic Asynchronous Processor Scalable-

Learning) for implementation. The design taped

out in November 2016 and silicon was received

during summer 2017.

Chip includes an Ultra low power, scalable and

configurable NN architecture

• Gain x50 in power consumption

vs conventional digital solutions

• 3D FDSOI at 28nm integrating

RRAM synaptic elements

• TFT device technology to interconnect

multiple processor chips

FDSOI 28nm DynapSEL chip – NeuRAM3 projectSource: Institute of Neuroinformatics of University of Zurich (Prof G.Indiveri)


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FULLY SYNCHRONOUS CLUSTER

• 512 neurons, 4096 synapses, 4b elementary weight

• Supporting benchmark MAC operators and basic signal processing

• Proof of concept FDSOI 28nm 2mm²

Conv. SRAMs

GALS FIFOs

SchedulerManager

DPRAM

Comp. unit

Async. control

Po

we

r d

om

ain

Topologies

NeuronsSynapses Proof of conceptINSPIRE SOI Silicon Valley Symposium - San Jose (USA) – 2019, April 9th

| 30Computing research topics | 2018, Oct. 15th

BRAIN

INSPIRED

TECHNOLOGIES


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MACHINE LEARNING MULTI-VALUE NVM OxRAM

→ Work in collaboration btw CEA and Stanford

→ T. F. Wu, ”A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs

Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and

Resilience Techniques”, ISSCC’19

Multi-Value OxRAM bit-cell

(2.3bit/cell, eq. 5 values/cell)

Endurer mechanim for RRAM reliability :- Temparary Write failure

- Permanent Write failures

Using Random remap + assocaiteive SRAM

RRAM integrated

on Silicon CMOS[Barlas, IEDM 17

Grossi, TED 19]

- 18 Kbyte OxRAM

- Simple 16-bit micro-controller core

- Ultra fast & energy efficient transitions

between On & Off modes



CONNECTIVITY “AT THE EDGE”

Ultra-low power connectivity for Internet Of Things


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Natively designed to:

• Enable ultra-low power “active standby” and fast wakeup

• Enable efficient power management to shutdown unused features or adjust power supply to requested

functionalities

• Address a wide range of IoT applications

STRATEGY FOR IOT NODES: 1/ AN ARCHITECTURE

Applications

(few examples)

Video surveillance Smart Camera

Secure communications

Data Fusion

Tracking and Monitoring

L-IOT

ArchitectureALWAYS-RESPONSIVE

SUB-SYSTEM

ON-DEMAND

SUB-SYSTEM

pW-µW area mW area

Perf

orm

an

ce/

En

erg

y n

eed

s

Embeds in-house wakeup

features for ultra-fast

wake up (<50ns)

Embeds classical CPU

and IPs for generic

computation

Embeds power management

feature and flexibility for best

use of energy


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• Address the most challenging requirements of IoT applications

• Benefit from FDSOI technology specificities and local ecosystem

• Drive technology roadmaps for new FDSOI nodes and Non-Volatile-Memories

2/ KEY IPS BEYOND STATE-OF-THE-ART

Security

Configurable lightweight

AES/PRESENT and TRIVIUM crypto IPs

Software polymorphism algorithm

Wake-Up

Wakeup controller

Wakeup radio

Wakeup imager

Ultra low power memory

Power Management

Voltage generator/ regulator

Distributed back-bias generator (FDSOI-

specific)

Embedded flexible clock generator

Asynchronous service network

Processing

ARM Cortex M0+ FDSOI low-power implementation

RISC-V CPU FDSOI low-power

implementation

Embeds AI processing

Wireless

Sub-GHz ultra narrow band RF transceiver


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3/ A STRUCTURING ROADMAP



SECURITY “AT THE EDGE”

Security


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CYBERSECURITY @ LETI : THE APPROACH

CHARACTERIZE

THE THREAT

SECURE

THE OBJECTEVALUATE

➢ 100 people

➢ 50+ patents

➢ 1 cybersecurity platform

1 accredited lab.

> 15 dedicated testbenches

Physical, Side channel, fault injection

LETI’s technology platforms

Design capabilities


http://www.emvco.com/?referred_from_www.paymentsnews.com

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OUR VISION OF SECURITY

Tamper resistance

Memory reading

Probing

By technology, architecture & embedded software

Side channel resistance

Time

Power

EM

Lifecycle management

Authenticity

Integrity

Security of communications

Authentication

Confidentiality

Integrity

Fault injection resistance

Glitches,

Light

Laser

EM

Security protocols

Bootstrap

Update

Recovery

Security architecture

Rôle

Audits

LogsValidated

Softawre


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CoolCube TM

Improving attacks

Machine learning for SDA

Nanofocused Xrays

Security characterization of

emerging technologies

Memories

Interconnect

FDSOI

Technology to improve robustness

2.5/3 D

PackagingTechnology to define new security

functions

PUF FDSOI

TRNG (FDSOI)Design to improve security

Encrypted instruction flow

BEST

PAPER

AWARD

TECHNOLOGIES INVOLVEMENT IN DEVICES SECURITY



CONCLUSION


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Sensor design

& pre-processing

• High-performance sensors

(image & others)

• Specific acquisition schemes &

associated processing for

various sensors

• Optimized format conversion

(eg Analog Digital Conversion)

• Light-weight sensor data

conditioning algorithms

Algorithm, Intelligence

& Processing architecture

• Algorithm & Architecture Codesign

• Optimized architecture for

on-sensor processing

• Smart embedded accelerators

(image, deep learning & others)

• Low latency perception & data

fusion

Connected

Embedded System

• Energy scavenging

• Low-power connectivity

• Advanced computing &

optimized software

• Security

INTELLIGENT DEVICES “AT THE EDGE”


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Leti Innovation Days | June 28-29, 2017

LETI, YOUR PARTNER FOR COLLABORATING ON INTELLIGENT DEVICES


APPLICATIONS AROUND THE CONNECTED CARsoiconsortium.eu/wp-content/uploads/2019/03/CEA...3D STACKED...

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