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APPLICATION OF MICROPROCESSORS AND MINICOPUTERS IN THE MONITORING AND CONTROL OF IRRIGATION SYSTEIMS US/USSR, 1979

D. G. EHLER

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APPLICATION OF MICROPROCESSORS AND MINICOMPUTERS

TO THE MONITORING AND CONTROL OF IRRIGATION SYSTEMS

by

David G. Ehler

U.S. Department of the Interior Bureau of Reclamation Denver, Colorado

A Paper to be Presented at a USA/USSR Joint Symposium

Frunze, USSR May 1979

ABSTRACT

This paper presents a modern practical approach to providing an upgradeable medium-priced system for control of open channel irrigation canals. The system is microprocessor based and utilizes already proven algorithms for providing control. The new concept is the utilization of the microprocessor to provide multiple control algorithms and EPROMS (Eraseable Programmable Read Only Memory) to provide the upgradeable feature. The development of the Colvin and EL-FLO control algorithms is discussed in this application using the INTEL 8080 microprocessor.

INTRODUCTION

The importance of irrigation today requires effective control of water to provide the right amount of water to the farm with minimum losses and the shortest lead time possible. These factors lead to the desire for a responsive controller at-low cost that provides short lead time scheduling or even availability on demand.

A number of controllers have been developed such as the Littleman, Colvin, and EL-FLO. Remote supervisory is also a viable alternative. A system that contains two or more of these alternatives might also be desirable.

In the past, a single controller has been chosen that will meet the requirements of the system and the dollars available at that time. If a subsequent decision is made to change to a different control algorithm, from Colvin to EL-FLO for example, the original controller must be removed and replaced with the new one.

The microprocessor-minicomputer concept is an approach to provide the following desirable features. The cost of a system to implement the simplest microprocessor-based controller should approximate that of the conventional controller. The microprocessor can be expanded and modified to incorporate more complex control algorithms at a later date if desired.

CONTROL ALGORITHMS

Existing automatic control algorithms are being utilized for the microprocessor control approach. Analog versions of the EL-FLO controller and the Colvin controller have been built and installed in the field and are operating with good results. Therefore, algorithms for these controllers were selected as the first two control algorithms to be tested in the microprocessor. Other control algorithm schemes will develop a two-level network with a centralized minicomputer and remote microprocessors. Other control systems might include remote supervisory capabilities and inter-active control schemes using the multiple control algorithms and a complex central minicomputer-based system.

A multiple control algorithm system might include three levels of control: Remote supervisory, EL-FLO, and Colvin. Remote super-visory could be utilized to set targets for the EL-FLO, and manually control certain changes. The EL-FLO would automatically be selected if the central minicomputer were to fail or lose communication. The Colvin would take control upon loss of all communication. Such a scheme becomes possible with remote microprocessors and

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at little more cost than the highest level of control (remote super-visory). This is one example of the flexibility and options available by using (minicomposer or microprocessor) remote controllers.

Such a system also provides the possibility of utilizing new control algorithms as they are developed.

THE MICROPROCESSOR SYSTEM

The Intel 8080A was selected for these systems because of numerous support-integrated circuits, hardware and software support, and availability of components with extended environmental characteris-tics. The Intel 8080A system is available in readymade system boards from Intel and many other suppliers.

The cards manufactured by Pro-Log were selected for development because of availability and low cost. The analog-to-digital con-verter was manufactured by Burr-Brown. An additional printed circuit board was developed in our laboratories to provide the necessary functions not provided on commercially available cards. This board provides gate control relays, status LED indicators, 6-trim potentiometers (for input of operator variables), a micro-processor reset circuit, and an 8-pole switch (for two variable inputs). The analog-to-digital converter provides an 8-bit digital output. Twelve-bit converters are readily available, but the use of a 12-bit would increase the memory requirement. The 8-bit converter is generally adequate for most applications.

Figure 1 is a block diagram of the microprocessor system used in these first two tests. Figures 2 and 3 describe the functions and instructions of the (A to D) 8080A.

An 8-pole switch is presently used to input two variables. A future revision will provide a switch matrix to input a number of variables using switches in lieu of the present input via potentiometers and the multiplexed analog-to-digital (A to D) converter. The A to D would then be devoted to dynamic controller inputs.

SOFTWARE SUPPORT

Software support is available in many forms from many suppliers. This includes, but is not limited to, development systems, emula-tors, assemblers, and compilers. Software may be resident or in a host computer. Intel 8080 system assemblers are available in the Engineering and Research Center for the Intelec 8 development system and the Hewlett Packard 2100 laboratory computer system. A PL/M

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POWER SUPPLY

ROM ROM READ w ONLY i

i MEMORY

1Kx8 WORDS

CPU OUTPUT TTY .16 BIT ADDRESS LATCH OR

COMMUN- 6 BIT CONTROL ICATION

4-8 BIT 8 I BIT DATA PORTS -

INPUT SPECIA

4-8BIT PORTS

GATE CONTROL

RAM RANDOM ACCESS MEMORY

1-:TO 4K x8 WORD!

ANALOG TO

DIGITAL

8 BITS 16 PORT

WATER LEVEL

GATE POSITION

FIGURE 1 MICROPROCESSOR ~RXZTEM

BLOCK DIAGRAM

1

III-DIRECTIONAL

11 , 80E0A CPU FUNCTIONAL

BLOCK DIAGRAM DATA BUS

DATA BUS • ' r .' BUFFERhATCH

to BIT) 1 ; : IS BITI INTERNAL DATA BUS INTERNAL DATA BUS

ACCUMULATOR TEMP. AEG. INSTRUCTION 11

MULTIPLEXER lei ul REGISTER 1111 -

FLAG RI FL

W 1s1 TEMP REG.

= UI TEMP REG.

1

FLIP FLOPS ACCUMULATOA 1- B u1 C ill

LA1CH I6 w REG. REG.

ARITHMETIC INSTRUCTION w D Ili E ILI LOGIC

DECODER REG. FIEO.

UNIT MACHINE F H l6 L I6 REGISTER

IALUI CYCLE H REG. I REG. "RAW 16 ENCODING w 116

a: STACK POINTER

- U6

PROGRAM COUNTER

DECIMAL INCREMENTER/DECREMENTER ADJUST ADDRESS LATCH 11bi

1

C~.

L~....~ TIMING AND

CONTROL

►O1MtR —• •12V SUPPLIES If<V DATA BUS INTERRUPT Liao WAIT

—• -6V WRITE CONTROL CONTROL CONTROL CONTROL SYNC CLOCKS

—+ OND

WA DBIN INTE INT HOLD HOLD WAIT I SYNC ♦1 42 RESET ACK READY

ADDRESSBUFFER ILCI

A, - AV ADDRESS BUS

FIGURE 2

INSTRUCTION SET

Summary of Processor Instructions

Instre+ctian Codeltl ClockCll lnsauctian Codeltl

momeoic Oescriptiew 07 0e DS Da 03 DZ a Do Cycles Maaeaewat Darvrptiert 07 Be DS Oa D3 DZ 01 11q

MOV,t, Q Mow register to register 0 1 0 D 0 S S S 5 RZ Ramwes at afro 1 1 0 0 1 0 0 0

MDV M. r Mow register to memory 0 1 1 1 0 S S S 7 RNZ Romero an no ram 1 1 0 0 0 0 0 0 MOV r, M Mort memory to register 0 1 0 0 0 1 1 0 l OF Ram" en positive 1 1 1 1 0 0 0 0

HLT Halt 0 1 1 1 0 1 1. 0 7 RM Retain anminus 1 1 1 1 1 0 0 0

MVI r Mow immediate regiter 0 0 0 0 0 1 1 0 7 RPE Rotave on panty even 1 1 1 0 1 0 0 0

MVI M Move immediate memory 0 0 1 1 0 1 1 Q 10 RPO Rarowa on panty odd 1 1 1 0 0 0 0 0 1NR r Increment register 0 0 0 0 0 1 0 0 5 RST Resort 11 A A A 1 1 1 OCR r Decrement register 0 0 0 0 0 1 0 1 5 IN Mgae I 1 0 1 1 0 1 1 INR M Increment memory 0 0 1 1 0 1 0 0 10 OUT Qaepst 1 1 0 1 0 0 1 1 OCR M Decrement memory 0 0 1 1 0 1 0 1 10 LX18 Land immediate register 0 0 0 0 0 0 0 1

ADD r Add register to A 1 0 0 0 O S S S 4 Pair 8& C ADC r Add regirter to A with carry 1 0 0 O 1 S S S 4 LXI 0 Load immediate register 0 0 0 1 0 0 0 1 SUB r Subtract register from A 1 0 0 1 0 S S S 4 pair & E

S88 r Subtract register from A 1 0 0 1 1 S S S 4 LXI H load immediate register 0 0 1 0 0 0 0 1 eaith borrow Pair H & L

ANA r And register with A 1 0 1 0 0 S S S .4 LXI SP Load iewmediats stack pointer 0 0 1 1 0 0 0 1 XRA r Exclusive Or register with A 1 0 1 0 1 S $ S 4 PUSH B Pusb resistar Pair B& C on 1 1 0 0 0 1 0 1 ORA r Or register with A 1 0 1 1 0 S S S 4 luck CUP r Compare register with A 1 0 1 1 1 S S S 4 PUSH 0 Push resister Pair 0& E on 1 1 0 1 0 1 0 1 ADD M Add memory to A 1 0 0 0 0 1 1 0 7 Stick ADC M Add memory to A with tarry 1 0 0 0 1 1 1 0 7 PUSH H Push a e istsr Pair H& L on 1 1 1 0 0 1 0 1 SUB M Subtract memory from A 1 0 0 1 0 1 1 0 7 stack $59 M Subtract memory from A 1 0 0 1 1 1 1 0 7 PUSH PSW Push Aand Flags 1 1 1 1 0 1 0 1

with borrow an sack ANA M And memory with A 1 0 1 0 0 / 1 0 7 POP 8 Pap r giistxr pair B& C off 1 1 0 0 0 0 0 / XRA M Exclusive Or memory with A 1 0 1 0, 1 1 1 0 7 stack ORA M Or memory with A 1 0 1 1 0 1 1 0 7 POP 0 Pop ryism pair 0& E off 1 1 0 1 0 0 0 1 CUP M Compare memory with A 1 0 1 1 1 1 1 0 7 stack A01 Add immediate to A 1 1 0 0 0 1 1 0 7 POP H Pop rellisttr pair H& L off 1 1 / 0 0 0 0 1 ACI Add immediate to A with 1 1 0 0 1 1 1 0 7 stick

Cory POP PSW Pup A and Flags 1 1 1 1 0 0 0 1 Sul Subtract immediate from 1 1 0 1 0 1 1 0 7 aft stack S81 Subtract immediate from A 1 1 0 1 1 1 1 0 7 STA St"A direct 0 0 1 1 0 0 1 0

with borrow, LOA Loud A dir:ct 0 0 1 1 1 0 1 0 ANI And immediate with A t 1 1 0 0 1 1 0 7 XCHG Ex iarege 0& E, H& L 1 1 1 0 1 0 1 1 XRI Exclusive Or immediate with 1 1 1 0 1 1 1 0 7 Reoses,

A XTHL Ea'sange top of stack, H&L 1 1 1 0 0 0 1 1 ORi Or immediate with A 1 1 1 1 0 1 1 0- 7 SPHL H& L to stack pointer 1 1 1 1 1 0 0 7 CP1 Compare immediate with A 1 1 1 1 1 1 •1 0 7 PCHL H& L to program counter 1 1 1. 0 1 0 0 1 RLC Rotate A left O 0 0 0 0 1 1 1 4 DAD 8 Add 6& C to H& L 0 0 0 0 1 0 0 1 RRC Rotate A right 0 0 0 0 1 1 1 1 4 DAD 0 Add 0& E to H& L 0 0 0 1 1 0 0 1 RAL Rotate A left through wry 0 0 0 1 O 1 1 1 4 GAO H Add H& L to H& L 0 0 1 0 1 0 0 1 RAR Route A right through . 0 0 0 1 1 1 1 1 4 DAD SP Add stack pointer to H& L 0 0 1 1 1 0 0 1

carry STAX 8 Stun A indirect 0 0 O 0 0 0 1 0 JMP Jump unconditional 1 1 0 0 0 0 1 1 10 STAX D Stone A indinect 0 0 0 1 0 0 1 0 JC Jump on Carry 1 1 0 1 1 0 1 0 10 LDAX 8 Laid A indirect 0 0 0 0 1 0 1 0 JIIC Jump on no arry 1 1 0 1 0 0 1 0 10 LOAX 0 Load A indirect 0 .0 O 1 1 0 1 0 Jz Jump on zero 1 1 0 0 1 0 1 0. 10 INX 8 Increment 8& C registers 0 0 0 0 0 0 1 1 JNZ Jump on no two 1 1 0 0 0 0 1 0 10 INX 0 IrKn wem 0& E registers 0 0 0 1 0 0 1 1 JP Jump an positive 1 1 1 1 0 0 1 0 10 INX H Inoreawnt H& L registers 0 0 1 0 0 0 1 1 JM Jump on minus 1 1 1 1 1 0 1 0 10 INX SP Inaeewent stack pointer 0 0 1 l 0 0 1 1 JPE Jump on panty even 1 1 1 0 1 0 1 0 10 OCX 8 Deawnem 8 S C 0 0 0 0 1 0 1 1 JPO Jump on parity odd 1 1 1 0 0 0 1 0 .10 OCX 0 Decrement 0& E 0 0 0 1 1 0 1 1 CALL Call unconditional 1 1 0 0 1 1 0 1 17 OCX H Oemreem H& L 0 0 1 0 1 0 1 1 CC Call on carry 1 1 O 1 1 1 0' 0 11/17 OCX SP Decrement stack pointer 0 a 1 1 1 0 1 1 CNC Call an no carry 1 1 0 1 0 1 0 0 11!17 CMA Caswplemant A 0 0 1 0 1 1 1 1

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Cz Can on am 1 .1 0 0 1 1 0 0 11/17 STC Set carry 0 0 1 1 0 1- l a 1 i CNz Call an no zero 1 1 0 0 0 1 0 0 I1/17 CMC Compka wnt carry 0 0 1 1 1 1 1 1 CP Can on positive 1 / 1 1 0 1 0 0 11117 OAA Daoanel adjust A 0 0 / 0 0 1 1 1 CM Cad on minus 1 1 1 1 1 1 0 0 11/17 SHLO Sttueki & L direct 0 0 1 0 0 0 1 0 CPf Can on parity even 1 1 1 0 1 1 0 0 11/17 LHLD Load H& L direct 0 0 1 0 1 0 1 0 CPO Call on parity odd 1 1 1 0 0 1 0 0 11/17 El E 1a Interrupts 1 1 1 1 1 0 1 1 A" Return 1 1 0 0 1 0 0 1 10 0t Disable interrupt 11 1 1 0 0 1 1 RC Return on carry 1 1 0 1 1 0 0 0 sill ' NOP Ne+praeww 0 0 0 0 0 0 0 0 ARC Retum on no carry 1 . 1 - 0. . 1 0 0 0 0 sill

NOTES: 1. 000 or SSS — 000 8 — 001 C-0100-011 E-100H-101 L-110 Memory-111 A.

i I

a

2. Two possible Cycle times. (5/11) indicate instruction cycles dependent on condition Flaps. FIGURE 3

compiler is also available on the Bureau of Reclamation's Control Data Corporation Cyber System. The data transfer medium is punched paper tape. The software for the Intel 8080A is also on paper tape.

ANTICIPATED PROBLEMS

Anticipated problems fall into three categories: site preparation, maintenance support, and equipment reliability.

Site preparation requires providing electric power for gate hoists and electronic equipment; providing the gate hoist mechanisms, motors, and controls; and providing a water level stilling well and structure to house the electronic equipment. This preparation applies to any mode of automatic or remote control. Most systems will require communications circuits.

Maintenance support for microprocessors is far more complicated than that for analog or simple mechanical controllers. Special equipment is required to test, repair, and analyze the microprocessor system. These systems also require maintenance personnel with an electronics background and often additional special training is required.

Equipment reliability can only be compared to similar applications of microprocessor-based equipment in the field. Operating and environmental tests in the laboratory have been successful. However, simulation of all field exposure elements is difficult, particularly lightning transients which have presented problems with analog controllers. Similar microprocessor apparatus in field applications seem to have a high tolerance to these problems. A-C line lightning protection and the use of rechargeable battery power supplies might be desirable. Batteries are used in many field applications and, in addition to providing isolation from transients, have the additional advantage of providing backup power.

THE COLVIN CONTROLLER

Colvin and EL-FLO algorithms have been developed for the micro-processor system described in this paper. Further development using communications between remote (microprocessor controllers) and a control minicomputer or microprocessor is being-considered for the next step.

The Colvin control algorithm was selected for the first application because it is field proven and not extremely complex. The Colvin algorithm has been used in the field for two seasons in an analog electronic controller. The first microprocessor.controller is used primarily for microprocessor hardware testing. The Colvin controller

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has evolved from an elementary mechanical controller through a number of mechanical and electronic analog versions. It is an open loop controller in which gate movements are generated with water moving away from the desired water level or at a constant level out of the dead band. The controller does not calculate a gate position and does not receive gate position. Therefore, limit switches are required on the gate hoist to prevent the gate from traveling too far.

The Colvin controller is based on an algorithm well suited to the microprocessor. A flow chart is provided in figure 4. The colvin controller can be used as an upstream or downstream controller simply by reversing the gate control.

The Colvin controller routine was written in Intel assembly lan-guage. The initial program utilized the Intelec 8 assembler and editor. This procedure was found to be slow and awkward because the assembler and editor were on paper tape and only one could be resident in the development system. A dual resident 8080 assembler/ editor developed for the Hewlett Packard 2100 minicomputer was utilized for editing and debugging the program and adding additional features.

The operating program was tested in three phases: operational testing, environmental testing, and laboratory canal model testing. The operational test time has been in excess of 2,000 hours with the unit operating at an accelerated rate. A power-up restart problem was encountered during this phase of testing. A 15-second reset circuit was added and further tests were satisfactory.

The controller was tested using two environmental chambers. The first chamber was used to test for extreme temeeratures in a dry environment -.two cycles of 24 hours each, 70 C (160 °F) for 4 hours, 0 °C (32 °F) for 4 hours, and ambient temperature approxi-mately 20 °C (68 °F) for 16 hours. For the second chamber test the relative humidity was varied from 30 percent to 100 percent. Zero to 70 °C are the operating limits and -65 to 150 °C are the storage limits for the commercial Intel 8080 series microprocessor compon-ents. No failures were encountered in the environmental tests. For harsh environment sites, the Intel 8080 components are available with a -55 to +125 °C temperature operating range.

The Colvin controller uses less than 512 words of 8-bit code, inputs 7 analog signals, uses 7 random access memory words, and has 4 LED status indicators. The analog inputs are converted to 8-bit quantities. Operator adjusted system variables are input as analog variables and digital inputs for step increment and dead band. The controller is limited in resolution by the 8-bit analog-to-digital converter.

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INITIALIZE RT } DECREMENT GT f

COLVIN CONTROL

READ THE NWL AND INITIALIZE LT

IS NWL WITHIN A DBD OF TG

no

NWL = new water level OWL - old water level DBD = dead band TO - target RT = reset time LT = loop time GT = gate rate time SI = step increment GRT1= gate run timer 1 GRT2= gate run timer 2

IS NWL WITHIN A SI OF OWL

no

IS NWL MOVING TOWARD TG

HAS RT TIMER TIMED OUT

yes

j DECREMENT I GT

SELECT AND CLOS

DID GT TIMER TIME OUT

no USE LONG GATE T

RELAY I (gate raise or lower)

USE SHORT GATE TIME GRTl I

OPEN RELAY AFTER GATE TIME & FORM CORRECTED LOOP TIME

UPDATE OWL AND INITIALIZE GT AND RT

WAIT FOR THE LOOP TIME TO TIME OUT

COLVIN CONTROLLER FLOW CHART

FIGURE 4

A field test site has been selected for this controller which will be installed on a Bureau of Reclamation Project soon. The controller will operate two radial gates in parallel. The gates control the flow from an afterbay reservoir into a canal.

THE EL-FLO CONTROLLER

The EL-FLO algorithm was selected as the second algorithm for microprocessor application. The EL-FLO algorithm has been field tested for 3 years in an analog controller with excellent results for control of open channel flow.

The EL-FLO controller is a downstream controller with the water level sensor located just upstream from the first check structure downstream from the controlled check. The controller uses a variable resistance capacitance filter with time constants from 500 to 1,300 to filter the input water level. The controller processes the following algorithm to derive the required gate position:

Gate opening = K3 (K1e + k2 T edt) 0

where:

k1, k2, k3 = Parameters for a particular canal reach

e = Filtered voltage representing deviation of water level from target

dt = Increment of time K3K1e = Proportioned gate opening

k3 k2 o T edt = Reset control gate opening

Due to the complexity of the EL-FLO algorithm, the P/M compiler was selected for developing the microprocessor program. The control

` routine requires approximately 1K words of read only memory and 500 ' words of random access memory, 400 of which are used for the digital

input filter and digital reset subroutine tables.

i The EL-FLO and Colvin programs will be resident in the microprocessor controller. A 1-bit toggle switch allows the operator to select the algorithm he wishes to use for control on the canal.

Communications for the required downstream water level will be t accomplished with an analog tone transmitter-receiver. When

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digital measurement and communication are shown to be superior, the water level information can be transmitted digitally. The micro-processor EL-FLO is currently in the early stages of laboratory testing, and laboratory tests should be complete within the year. The microprocessor EL-FLO will be tested on the Corning Canal near Red Bluff, California.

CONTINUING DEVELOPMENT OF THE MICROPROCESSOR

The next area of development by providing digital communica-tions between the microprocessor canal controllers and a central micro or minicomputer, will give many new options of control using the same basic microprocessor based remote unit.

The first level of development will be to set up a centralized supervisory control system with digital communications. This will provide check information such as gate position, upstream water level, downstream water level, and possibly some turnout demands. The system will also provide positive gate control and possibly setpoint gate control and turnout control.

The second level of development will make the supervisory control interactive with the resident Colvin and EL-FLO controllers. Options such as selecting EL-FLO or Colvin controller, changing the setpoint or target, and presetting gates are possible. Automatic failure modes such as transfer to EL-FLO when the central computer is down or communications are lost, and transfer to Colvin (a local control algorithm) when all communications are out are possible with microprocessor-based remote terminals.

A third level is also under development. This level has a complex control algorithm in the centralized control center. With this mode of operation, the remote controllers act as gate controllers opera-ting on gate positions provided by the control algorithms and as data collectors providing analog quantities, status, and alarms to the control algorithm.

The central computer or processor will contain most of the software for the system. The software includes data tables, display formats, communications drivers, logging formats, bulk data storage, and the control algorithms. Hardware configurations provide man-machine interface such as CRT (cathode ray tube) terminals, hard copy terminals, high-speed printers, disk memories, magnetic tape, redundant processors, communications interface, and noninterruptible power supplies.

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SUMMARY AND CONCLUSIONS

The microprocessor has potential of being an excellent method for canal control. The most important benefit of the microprocessor approach to canal control is the ease of modification and expansion. The basic controller is the same for either Colvin or EL-FLO algor-ithms; the only change is the addition of read only memory. When the required communications link and sensor for downstream water level and the gate position sensor potentiometer are installed, it is only necessary to provide the necessary constants and to change the selector switch to implement either the Colvin or the EL-FLO control algorithm.

When and if a central control system change is desired the changes at the canal controller (remotes) are primarily in the software and communications. The central control center can range from a micro-processor, communications, and a CRT or teletypewriter to dual redundant minicomputer system with disc memory, color CRT's with light pen, hard copy, and magnetic tape. A typical system would consist of a minicomputer (or possibly redundant computers and terminals) CRT operators terminal, hard copy logging and printout typewriter, disc memory, and communications equipment.

With central control a number of options are available: (1) Central-ized remote control requiring an operator to monitor displays of telemetered information and to make required control operations, (2) Automatic control, where the computer has the necessary informa-tion to cause control actions based on telemetered quantities, (the operator could alter the response or take positive control), and (3) A mode with a hierarchy of methods with operator or computer selec-tion of control algorithms.

Maintenance is still a problem, partly because of the unknown performance in the field. Maintenance will require a higher level of skill°than with early electrical-mechanical controllers. As both avocational and professional skills develop in micropro-cessor systems, the availability of skilled personnel to repair and service microprocessor systems should also improve.

If a canal system is small and expansion or change in operating objective is not anticipated, then analog controllers should probably be utilized for control. If the canal is large, or if the

i uses of the canal are changing, or if future changes are anticipated then a microprocessor based controller system should be considered. If a large number of control actions are required a microprocessor based system should be considered for the remote units in a super-visory control system to allow future expansion. The microproc-essor also has a favorable cost comparison with analog controllers.

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REFERENCES

[1] 8080 Microcomputer Systems User's Manual, September 1975, Intel Corporation

[2] Operation of Central Valley Project Canals by Edwin F. S. Sullivan and Clark P. Buyalski, Bureau of Reclamation, Sacramento, California

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