Announcements - bwrcs.eecs.berkeley.edu
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1 EE241 - Spring 2004 Advanced Digital Integrated Circuits Borivoje Nikolic Lecture 28 Flash memory 2 Announcements Project presentations Thursday, May 6, 9:30-12 BWRC classroom 2108 Allston Way, Downtown Berkeley Final on May 11, 9:30-11am 203 McLaughlin Homeworks returned Solutions posted
Transcript of Announcements - bwrcs.eecs.berkeley.edu
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EE241 - Spring 2004Advanced Digital Integrated Circuits
Borivoje Nikolic
Lecture 28Flash memory
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Announcements
Project presentations Thursday, May 6, 9:30-12BWRC classroom2108 Allston Way, Downtown Berkeley
Final on May 11, 9:30-11am203 McLaughlin
Homeworks returnedSolutions posted
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Project Reports and PresentationsShould be in paper format – max of 6 pages
Title of the project/ your names and e-mail addressesAbstract (100 words)MotivationProblem statementPossible solutions from literature (from midterm report)Proposed comparison/solution. Discuss why did you select this particular one.Conditions/assumptions of your designAnalysis: Does it work? Analytical analysis, simulation results.Conclusion. What is this approach good for? What else could be done?References
Due on May 6, at 8am (on the web), both the report and the slidesTime = 5min + 5min/person
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Outline
Design for testFlash memory
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Flash Memory
Slides adapted from Ken Takeuchi, Toshiba
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Semiconductor Memory Trends
From [Itoh01]
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Trends in Memory Cell Area
From [Itoh01]
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Some New(?) Kids on the BlockFRAM (Ferroelectric RAM): Use a “programmable capacitor”(made of Perovskite crystals).
During write, capacitor is polarizedDuring read, an electrical field is applied and current is measured
MRAM (Magnetoresistive RAM): use magnetic charges in contrast to electrical charges – very similar to old core memories
Magneto-resistive material changes resistivity when placed in a magnetic field
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Flash EEPROM
Control gate
erasure
p-substrate
Floating gate
Thin tunneling oxide
n+ source n+ drainprogramming
Many other options …
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Basic Operations in a NOR Flash Memory? Erase
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Basic Operations in a NOR Flash Memory? Write
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Basic Operations in a NOR Flash Memory? Read
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History of Flash Memories
‘84 ‘85 ‘86 ‘87 ??????‘91 ‘92 ‘93 …PRESENT
SanDisk-type
DiNOR-type
SanDisk-type
NOR-type
NAND-type
DiNOR-type
AND-type
SST-typeX
SST-type
X
File-Storage
Code-Storage
NOR-type
NAND-type
ACEE-type
AND-type
Split-gate-type
FLASH MEMORYInvention
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Flash Memory Comparison - Code vs File Storage -
Code Storage
File Storage
Applications Type of Flash memory Performance
Program storage for- Cellular Phone- DVD- Set TOP BoxBIOS for- PC and peripherals
Small form factor card for- Digital Still Camera- Silicon Audio- PDA ... etcMass storage as- Silicon Disk Drive
Important :
Acceptable :
• High speed random access• Byte programming
• Slow programming• Slow erasing
• High speed programming• High speed erasing• High speed serial read
• Slow random access
Important :
Acceptable :
NOR • Intel / Sharp• AMD / Fujitsu / Toshiba
DINOR • Mitsubishi
NAND • Toshiba / Samsung
AND • Hitachi
•SanDisk: NOR
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Requirements for File Storage Memory
Low Bit Cost <$.2/MByteHigh Density >256MByteHigh Speed Programming >6MByte/sec
and Erasing <3msec/blockHigh Speed Serial Read Low Power ConsumptionGood Program/Erase Endurance >1 million cycles
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Cell Array Comparison
Simplest wiringSmallest area
NOR SanDisk AND NAND
Erase gate(poly)
Unit Cell Unit Cell
Word line(poly) Word line(poly)
Source line(Diff. Layer)
Word line(poly)
Bit line(metal)
Source line(Diff. Layer)
Unit Cell
Contact
Source line(Diff. Layer)
Word line(poly)
Bit line /Source line(metal)
Unit Cell
Sub Bit line (Diff. Layer)
9F2 8F2 4F210F2
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Word linesSelect transistor
Bit line contact Source line contact
Active area
STI
NAND Cell Array (Top view)
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NAND Cell Array (Cross sectional view)
Word line
Word line
Bit line
Select gate
A A’
A A’
Source line
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Cell Size Shrink by Self-Aligned STI
Current
2 F
3F Floating Gate
Word Line
LOCOS_NAND : 6F2+aLOCOS_NAND : 6F2+a
2 F
2 F
STI_NAND : 4F2+aSTI_NAND : 4F2+a
3 F2 F
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NAND Cell Array (Cross sectional view)
Word line
Word line
STI
1st floating gate
2nd floating gate
B B’
B B’
Si
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+ Multi Level Cell
Floating Gate
LOCOS
Control Gate
3.5F
3F
2F
3F
NAND-type Cell(Contactless)
2F
2F
Self-AlignedSTI Cell
2F
2F
Self-Aligned STI Cell
Floating Gate
STI
Control Gate
Cell Size 10-11F2 6-7F2 4-5F2 2-2.5F2 Isolation LOCOS LOCOS SA-STI SA-STI
NOR-type Cell
NAND Cell Trend
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NAND Flash Cell Size Trend
Start of Mass Production
Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan-‘93 ‘94 ‘95 ‘96 ‘97 ‘98 ‘99 ‘00 ‘01 ‘02 ‘03 ‘04
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Cell
Size
( um
2 )
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LOCOS SA-STI
MLC
0.01
Multi Level Cell
Floating Gate
LOCOSTunnel Oxide
Control GateWSiONO
Control Gate ONOFloating Gate
Tunnel Oxide STI
WSi
SA-STI
0.25um
0.175um
0.13um0.10um
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That’s all Folks
Thanks for the fun semester.See you next Thursday
