Analysis and Modeling of Subthreshold Leakage ofRT-Components under PTV and State Variation

Domenik Helms1, Gunter Ehmen1, and Wolfgang Nebel21OFFIS Research Institute, 2University of Oldenburg

D - 26121 Oldenburg, Germany

helms@offis.de, ehmen@offis.de, nebel@offis.de

ABSTRACTIn this work we present a SPICE-based RTL subthreshold-leakage model analyzing components built in 70nm technol-ogy [1]. We present a separation approach regarding inter-and intra-die threshold variations, temperature, supply-vol-tage, and state dependence. The body-effect and differencesbetween NMOS and PMOS introduce a leakage state de-pendence of one order of magnitude[2, 3]. We show thatthe leakage of RT-components still shows state dependen-cies between 20% and 80%. A leakage model not regardingthe state can never be more accurate than this. The pro-posed state aware model has an average error of 6.7% forthe RT-components analyzed.

Categories and Subject Descriptors:B.8.2: Performance Analysis and Design Aids.

General Terms:Design.

Keywords:Leakage, Process Variation, State Dependence, Modeling.

1. INTRODUCTIONIn recent years, a leakage paper motivation would have

read like: leakage will become the most important source ofpower consumption. Today, leakage is the most importantcontributor to a system’s power consumption and withinthe last 3 years there was an incredible amount of scientificapproach in this area.

The physics of leakage are well understood and can beestimated with a sufficient accuracy at transistor level if thedevice geometry as the physical condition of the transistoris exactly known [4, 5].

Process variations randomly and unpredictably affectingthe geometry are identified being the major hurdle of accu-rate leakage and performance estimation. Results of ongoingresearch have to be implemented to the EDA tools [3, 6, 7].

A huge amount of anti-leakage techniques exist which canbe separated into 3 classes:

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• Always applicable techniques, which if available will beused for each design i.E. well engineering [4] or high-kgate oxide [8].

• Leakage-performance tradeoff techniques [9], enablingthe choice between fast and low leaking devices. Theusefulness of this tradeoff depends on the design.

• Power management techniques offering a high perfor-mance and a low leakage mode in which the componentis either slow or dysfunctional as power gating or adap-tive body biasing - both reviewed in [10]. Both tech-niques are implemented on lowest levels of abstractionbut have to be controlled system wide.

Both, the tradeoff and the power management techniqueshave to be evaluated at high level.

There are several approaches abstracting from accurateBSIM models [5] to much faster gate level models. Butas the impact of tradeoffs and power management has tobe evaluated at system level, gate level based models arestill too complex for system level tools which usually do noteven generate gate level details. Thus we developed two al-ternative RTL-leakage macromodels: The simulation basedbottom-up model, abstracting from transistor level to RTLis described in [11]. The top-down characterization basedmodel analytically describing the leakage of RT componentsis presented in this work.

Existing dynamic power, area and delay models for RTcomponents have typical estimation errors in the order of10%. To make leakage estimation accuracy comparable, ourleakage models will have to regard all known parametersinfluencing leakage [8].

In the bottom-up model, the dynamic parameters temper-ature, supply voltage, and body voltage, and the variationparameters of channel length, oxide thickness, and chan-nel doping are explicit input parameters. In the analyti-cal model, only supply voltage, temperature and componentstate directly enter the model. Bulk voltage, deviating dueto ABB indirectly enters our model by modifying the effec-tive threshold voltage. Modeling a huge number of transis-tors in one model, random process variations (intra-die vari-ations) only enter due to the non-linearity of the Ileak (Vth)relation which is captured inside the models as presented in[3, 7, 12]. Finally, the inter-die variations resulting in sys-tematic (not statistic) deviations of the threshold voltagecan be regarded by sequentially recomputing the models re-sulting in a probability density function of the leakage powerdistribution.

In this paper we will thus address the emerging leakageproblem by presenting an accurate leakage macro-model en-abling leakage aware RT-synthesis. The problem of mod-eling PTV variations is discussed in several publications asshown in Section 2. After presenting the simulation envi-ronment in Section 3, the separation approach itself is onlybriefly described in Section 4. In Section 5, the major con-tribution of this work, the state dependent leakage model isdeveloped and evaluation results are presented in Section 6.

2. RELATED WORKChen et al. [13] presented a subthreshold leakage estima-

tion methodology for computing lower and upper bounds byregarding the stacking effect. [14] then presented a first use-ful separation approach, dividing leakage current into tran-sistor count N , supply VDD, leakage per device Idev and aconstant k as

Ileak = k ·N · VDD · Idev, (1)

where k gives the average leakage current per device at nom-inal voltage. In our approach, we first introduce data depen-dency to the parameter k, then we show that k accuratelyseparates from the other parameters for the Berkeley Pre-dictive Technology Model (BPTM) 70nm technology, andfinally we introduce some corrections, as leakage does notperfectly separate into these 4 parts.

[2] analyses the leakage distribution for the 1 and 2 inputgates reporting a substantial state dependency. There aremany approaches at this level enabling accurate leakage cur-rent prediction if all relevant parameters are exactly knownper device [5]. But some parameters are not accurately pre-dictable on the lower levels. The effect of parameter varia-tions on leakage was analytically investigated in [15], where[16] regards the distribution of these variations.

From a system level view, the dominant leakage param-eters [8] described in Section 1 can be identified and pre-dicted. In [17], a flow for modeling the thermal depen-dence of the leakage was presented, and in [18, 19], ther-mally dependent leakage estimation was combined with achip-wide temperature prediction, thus also regarding theelectro-thermal back-coupling introduced by the subthresh-old current’s thermal dependence.

[12] analyses the impact of threshold voltage variations inorder to handle intra-die process variations. In [6] a method-ology is presented, estimating the probability density func-tion of the leakage current due to process parameter vari-ation. In [3] parameter sensitivity analysis is introduced,enabling estimation of the effect of a variation on the aver-age leakage. In [7] this sensitivity analysis regarding intra-and inter-die process variations is extended.

In order to combine the different parameters, an itera-tive approach is presented by [20], accurately modeling dy-namic power and leakage power by regarding the interactionbetween temperature, supply voltage, and power consump-tion. They introduce a thermal system model handling theelectro-thermal coupling as well as a supply-grid model han-dling the electro-electro coupling introduced by the finitecapacitance of the supply system. The most complete highlevel leakage model was presented by [21], regarding all PTVvariations, thus all parameters except for the state.

Best to our knowledge, the only other approach enablingPTV and state dependent RTL leakage analysis is our al-ternative approach, presented in [11]. As can be seen in the

evaluation section, the strengths of the analytical model areeasy model characterization and very fast model evaluation.The advantages of [11] are higher modeling accuracy andmore direct model parameters.

3. DESCRIPTION OF THE SIMULATIONENVIRONMENT

Since there is no reliable higher level leakage estimationtool available, this work is based on the Berkeley SPICEsimulator including the BSIM transistor model. The recentversion BSIM4.40 is able to model various leakage effectslike subthreshold current, gate tunneling and junction leak-age including the Drain Induced Barrier Lowering (DIBL)effect. Unfortunately, in our experiments the recent tran-sistor model failed to converge for several circuits as soonas they exceeded a size of 100-1000 transistors. The olderBSIM3.52 version does not show these convergency prob-lems, so we decided to use this version, even though it isnot capable of estimating other leakage effects than sub-threshold current. This limits the application of our modelto technologies where subthreshold leakage is the dominat-ing source of leakage. These are technologies down to 70nmstructure size and smaller technologies having applied high-k gate dielectrics.The MOSFET model was characterized using the BPTMcard for the 70nm NMOS and PMOS [1]. The model-cardswere created using the reference values for channel length,oxide thickness, threshold voltage and drain-source resis-tance.For model characterization and evaluation, we need to haveSPICE simulations of RT components, having each tran-sistor properly configured. Hence, we synthesize each RTcomponent using a commercial technology. Then we replaceeach gate of the component by a cloned SPICE version hav-ing the same behavior as the respective commercial gate.In Section 3.1 we present, how to clone a commercial tech-nology to SPICE, and in Section 3.2 we describe the flowcreating RTL SPICE.

3.1 Creation of a Generic SPICE LibraryA commercial technology offers several hundred gates in

different driving strengths. In order to limit the cloningeffort, we prune the relevant gates of the commercial tech-nology. As for instance, an AND gate has to be constructedusing a NAND gate and an inverter, we pruned all logic gateswhich can be constructed from other cells resulting in thesame transistor level description. The difference between anative AND gate and a constructed one is that the intercon-nect of the native one is optimized on layout level. But aslong as the interconnect seems not to show relevant leakageeffects, this pruning is valid for our work and reduces thecloning to 21 native gates in 4− 10 driving strengths.

As described in the next section, the gates of the SPICElibrary have to replace the gates of the commercial technol-ogy in a gate level description of an RT component. To makea replacement valid, our gates must have the same timingand power behavior. As accurate power figures for the com-mercial technology are not available, we can just ensure thesame timing behavior. Thus, we create timing-equivalentRT-components for our model validation.

The only degree of freedom left in the BPTM regardingthe timing is the transistor width and the sequence of serial

measuredelays

converged?

SPICEtestbench

commercial lib’spin delays

SPICElibrary

y

constraints:• use pruned part

of the library• write flat verilog• avoid tri-state

Design Compiler

RT componentin flat verilog

commerciallibrary

verilog2spice

SPICEgate list

RT componentin SPICE/BSIM

greedy widthadoption

n

for each gate in pruned library

for each RT component

leakagecurrents

Figure 1: Adopting width of the 70nm BPTM tech-nology transistors to generate gates having the sametiming behavior. Right: RT components in Verilogcan be simulated in SPICE using the SPICE libraryand the Verilog netlist.

transistors. Using a setup script interacting with SPICE andadopting transistor width of each transistor, we construct aSPICE sub-circuit for every pruned gate of the commerciallibrary having the same delay behavior and the minimaltotal size (rf. Fig. 1 left side).

3.2 Synthesis of RT-ComponentsAs presented on the right side of Fig. 1, we use Syn-

opsys Design Compiler to synthesize the components. Ascript limits the synthesis to the pruned gates, forces non-hierarchical output as it eases up the conversion to SPICE,and avoids tri-state logic as this eases up SPICE conver-sion. We obtain a Verilog gate-netlist, which is automati-cally converted to SPICE, but now instantiating our SPICElibrary instead of the commercial technology’s gates. Weend up with professionally designed RT-components havingthe same timing behavior as the commercial technology andgiving realistic leakage estimates.

4. PARAMETER SEPARATIONIn this work we regard the impact of process, temperature

and voltage variations (PTV-variations) together with statedependencies on leakage. This section will describe a separa-tion approach splitting the influences of process variations,temperature, and supply voltage.

4.1 Variation of the Threshold VoltageSince we will only regard sub-threshold currents, we re-

duce the process variations to the variation of the thresholdvoltage. We combine the separation approach [14] with astatistical process variation model [3]. For a transistor thatis off, the subthreshold leakage results as

Isub = kVT2W/L · exp (Vth/nVT ) (2)

where n = 1 + Cdm/Cox is the subthreshold slope resultingfrom the ratio of the capacitances of the depletion layer and

the oxide. VT = kBT/e is proportional to the absolute tem-perature T . Assuming that, due to process variations, thethreshold voltage is Gaussian distributed

p (Vth) =(σV√

2π)−1

exp

(− (Vth − µV )2

2σV 2

), (3)

the average leakage due to the threshold variation then re-sults as the expectation value E(x) =

∑ip(xi)xi

µI =

∫ ∞−∞dVth p (Vth) I (Vth)

=kVT

2W

LσV√

2π·∫ ∞−∞dVth e

(− (Vth−µV )2

2σV2 +

VthnVT

)

=kVT

2W

LσV√

2π·e

µVnVT

+σV

2

2n2VT2 ·∫ ∞−∞dVth e

−(Vth−µV +σV

2/(nVT ))2

2σV2

= kVT2W/L · e

µVnVT

+σV

2

2n2VT2 ·∫ ∞−∞dVth p

(Vth +

σV2

nVT

)= Isub (µV ) · fP (σV , T ) · 1. (4)

Due to the nonlinear relation between temperature, thresh-old voltage and leakage, the threshold voltage can not becompletely separated, but remains coupled with the tem-perature as

fP (σV , T ) = e(σV /nVT )2/2. (5)

4.2 Separation of the Supply VoltageIn first order, the supply voltage influences the subthresh-

old current linearly, but due to the drain induced barrierlowering effect (DIBL), the threshold voltage depends onthe supply voltage as

∆Vth (VDD) = − VDD2 cosh (L/lc)− 2

(6)

with lc being a technology constant. Thus, the supply volt-age also influences the correction term (5), preventing aneasy separation approach. We circumvent this by introduc-ing a second order Taylor approximation at nominal valuesbuilding an effective supply voltage function fV . Using thefact, that eα(x+δ) ≈ eαx · (1 + αδ) for small |δ|, the supplyvoltage dependence can be approximated as

fV (V, T ) = 1 + αV ·V − V ∗

T+ βV ·

(V − V ∗

T

)2

αV =T ∗

V ∗∂I

∂V

∣∣∣∣T∗,Vth∗,V ∗

, βV =T ∗2

2V ∗∂2I

∂V 2

∣∣∣∣T∗,Vth∗,V ∗

(7)

The fitting parameters αV and βV can be easily charac-terized having SPICE simulation results. For the 70nmBPTM, they resulted as αV ≈ 188.5KAV −2 and βV ≈8460K2A2V −3 (rf. Fig. 2).

4.3 Analysis of the Nonlinear Thermal Depen-dence

As can be seen in Table 1, the subthreshold leakage sig-nificantly depends on temperature, doubling with each 19K

0.5

1

1.5

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

supply voltage [V]

rela

tive

leak

age

I(V,T

) / I(

V*,T

)NMOS @ 300KNMOS @ 400Kmodel @ 300Kmodel @ 400K

Figure 2: Evaluation of the voltage separation func-tion fV (V, T ). Within typical limits of supply voltage(VDD > 0.4V ) and temperature (300K - 400K), theseparation error is below 1%

T INMOS IPMOS errorN errorP

[K] [nA/µm] [nA/µm] [%] [%]300 2.23 0.12 0.0 -13.3320 5.59 0.35 1.6 -6.1340 12.5 0.89 2.1 0.0360 25.7 2.05 1.9 5.0380 48.8 4.34 0.8 9.2400 86.6 8.56 -0.8 12.7

Table 1: Accuracy of the thermal leakage model forNMOS and PMOS devices. Negative errors meanan underestimation by the model.

(NMOS) and 16K (PMOS) of temperature increase. Aswe already handled the temperature-variation correlation inSection 4.1 and the temperature-voltage interaction in Sec-tion 4.2, the remainder of the thermal dependence of thesubthreshold leakage strictly follows the analytical expres-sion of Equation 2. The last two columns of Table 1 sum-marize the error, when trying to model subthreshold currentof equation 2 using a characterized value of n = 1.598, thusapproximating

fT (T ) = I0 · eVth/1.598VT . (8)

The subthreshold leakage’s thermal dependence of an NMOStransistor can be approximated with less than 2% error be-tween 300K and 400K. The PMOS modeling is a little worsethan this having a maximum error of 13% in this range. Butas the subthreshold leakage for PMOS is approximately oneorder of magnitude smaller, the expected overall error forlarge circuits remains below 2%.

4.4 Combination of the Separated ModelsThe total leakage power of a component having N tran-

sistors can be modeled as

Isub = I0 · kdata ·N · fP (σV , T ) · fV (VDD, T ) · fT (T ) (9)

Component N Ileak min. max. std.[nA] [%] [%] [%]

AddCla4 364 37.31 30.8 27.4 10.7AddCla8 610 62.49 24.8 18.5 7.0AddRpl4 330 34.50 35.2 29.6 14.2AddRpl8 656 76.63 33.6 22.7 7.8DecRpl4 54 8.18 31.9 56.5 22.1DecRpl8 214 29.06 53.0 75.6 25.6IncRpl4 56 8.48 62.6 36.8 28.9IncRpl8 156 20.63 39.4 22.9 9.5MultCsa4 758 73.09 17.5 21.1 6.9MultWall4 1034 110.14 29.9 32.5 14.7Mux2 4 50 13.06 65.1 86.7 51.1Mux2 8 98 26.38 65.8 83.0 51.6Mux3 4 104 10.26 71.0 68.9 40.2Mux3 8 208 20.82 70.8 65.6 39.8SubCla4 370 43.70 35.7 46.3 15.2SubCla8 696 77.14 34.1 36.0 9.8SubRpl4 274 32.92 36.3 39.2 13.9SubRpl8 802 80.85 25.5 38.5 8.1

Table 2: Number of transistors N , average sub-threshold leakage, percentage of deviation for mini-mum and maximum state and relative standard de-viation for RT components up to 1000 transistors.

where the remainder kdata models the state dependency andwill be discussed in the following section.

5. MODELING STATE DEPENDENCYIn this section, we will analyze the importance of state

dependent leakage modeling and develop a kdata model.

5.1 Analysis of the State DependenceHere, we perform a pure SPICE based minimum, maxi-

mum, and average leakage current analysis to evaluate theinfluence, the state has on the leakage of a huge RT struc-ture. In 5.2, we then develop a model describing this statedependence.

Determining minimum and maximum leakage current isnp-hard [22]. Hence, we limited our analysis to componentswith up to 17 inputs (2 times 8bit data plus 1 control) ex-cept for the multiplexers where minimum and maximum caneasily be determined due to their symmetry. In addition welimited the analysis to components with less than 1000 tran-sistors as simulation time in SPICE was reasonable then.Even with this limits, the total simulation time (for eval-uation) was 6 weeks on a 8xPentium4 System running at3GHz, as a single BSIM evaluation needs ≈ 2.5ms on oursystem and we had to perform 1.5 · 109 evaluations.1

In Table 2, we summarize our results: On average, theminimum and maximum leakage are 39.5% and 41.9% awayfrom the mean leakage. The average standard deviationwas 19.2%, but relative standard deviation is sinking withthe number of transistors. Monte Carlo simulations of a3490 transistor 8 bit Wallace tree multiplier show a relativestandard deviation of 4.3%.

1This high simulation effort was needed for detailed analysisof the state dependence. The final model is characterizablein a few seconds.

5.2 Development of a State ModelThe state dependency of leakage is the least important

one of all parameters introduced in Equation 9, but with19.2% on average, it still needs to be considered.

We develop our model, starting with an RT-level soft-macro modeling the leakage state dependence by simplify-ing the transistor level equation for fixed temperature andsupply, without variance and limiting the body effect to aneffective width2:

Isub (data) =

N−1∑i=0

si · (wpi Ip) + (1− si) · (wni In) , (10)

where wpi and wni are the effective widths (in µm) of the ithPMOS and NMOS device, si is the logic value and Ip andIn are PMOS and NMOS leakage for an inverter with 1µmwidth. In order to reduce the complexity we replace all wpiand wni by an average wp and wn:

Isub = NwpIp ·N−1∑i=0

si +NwnIn ·N−1∑i=0

(1− si)

Isub = NwnIn +

N−1∑i=0

si · (wpIp − wnIn)

= N (wnIn + pall(wpIp − wnIn)) = N (α∗ + β∗pall) (11)

where pall is the signal probability of all internal nodes.Assuming that the internal nodes are correlated to the in-puts and can be linearly approximated from the input signalprobability pinput, kdata can be modeled using

kdata = αD + βD · pinput, (12)

where the data dependence parameters αD and βD can befit by characterization. The number of transistors N re-sulted as a factor to the leakage, thus it can be separatedas suggested in Equation 9. As there is no proof, that statedependence also separates from other parameters, we exper-imentally determined the separability. The term

I(data, TA, VA)/I(data, TB , VB)

varies less than 0.1% when randomly selecting TA, TB , VAand VB and evaluating the term for each possible input state.

6. EVALUATIONThe set of characterization and the set of evaluation data

both are obtained as follows: We create the RT Componentsshown in Table 2 and perform SPICE simulations measur-ing the leakage of these components while varying all pa-rameters: Synthesizing the circuit, we randomly assign athreshold voltage variation between 0 ≤ σVth ≤ 50mV witha mean value of 0.2V and −0.22V . We supply this circuitwith a voltage randomly chosen from 0.6V ≤ VDD ≤ 1.0Vand set the ambient temperature to a random value from300K ≤ T ≤ 400K. Then we measure the subthresholdleakage of the component for different input states.

2In [11], we showed, that leakage reduction due to the body-effect can be accurately modeled with a state-dependent ef-fective transistor width.

Compon. w/o w/D Compon. w/o w/DAddCla4 10.9 3.83 AddCla8 7.35 6.63AddRpl4 14.4 7.40 AddRpl8 8.12 4.49DecRpl4 22.2 8.27 DecRpl8 25.7 11.4IncRpl4 29.0 18.1 IncRpl8 11.0 9.78MultCsa4 7.26 2.98 MultWall4 14.9 6.02SubCla4 15.4 4.60 SubCla8 10.1 3.00SubRpl4 14.1 4.36 SubRpl8 8.43 2.86

Average 14.2 6.69

Table 3: Evaluation of the relative standard devi-ation error of the parameter separation approachwith no data awareness (w/o) and the data awareapproach (w/D).

Component #gates std. [%] max. [%]AddCla4 83 4.11 12.9AddRpl8 151 2.90 11.6MultWall8 767 2.33 11.1

Table 4: Evaluation of the bottom-up model: Rel-ative standard deviation and maximum estimationerror of three 45nm RT components against statisti-cal SPICE simulation.

6.1 Analytical Model EvaluationWe compute the relative standard deviation for three mod-

els. To evaluate how accurate the parameter-data separationis, we fix the input state and just vary all the other param-eters. We characterize the separation function parametersusing random sampling points. The resulting model errorfor all components is between 2% and 3%. For the nextmodel, called ’w/o’ in Table 3, we vary the data and all pa-rameters. We do not characterize the data dependency butassume that kdata = 1. As the model error of the parameterseparation alone is very low, the resulting error of the ’w/o’model is dominated by the data-variance of the componentas presented in Table 2. The average error of the ’w/o’ modelis 14.1%. The final model, called ’w/D’ in Table 3 uses allparts of Equation 9. Except for the smallest components(incrementer and decrementer), the standard deviation isalways below 8%, the average error for all components is at6.7%.

In comparison to the SPICE simulation time, the modelevaluation time of each of our models is negligible as is is justevaluation of analytical functions. In order to characterizethe models, we took 3000 sampling points needing one hourcomputation time for all components together.

In this evaluation, we neglect the effect of electro-thermaland electro-electro back-coupling, described in Section 2.But as back-coupling aware modeling means iteratively eval-uating a model working at fixed parameters and recomput-ing these parameters afterwards, our model is well applicableto back-coupling approaches.

6.2 Comparison to the Bottom-Up ModelFor comparison to our alternative model, Table 4 shows

the evaluation results of the bottom-up model. As thismodel can estimate the effect of various parameter varia-tions, the error of a single prediction is computed in com-parison to a Monte Carlo SPICE simulation averaging over1000 settings for intra-die variation of the parameters.

As both models show comparable accuracy, it stronglydepends on the application, which is the better one. Asthe bottom-up model is characterized at transistor level, itavoids RTL spice simulation and directly models transis-tor geometry parameters (channel length and width, oxidethickness, channel doping) of which the variability is eas-ier to predict. But for characterization, several thousandspice simulations are needed and have to be saved insidethe model. The advantages of the top-down approach, pre-sented here, are a) the few number of characterization dataneeded characterizing the few model parameters and b) thefast model evaluation.

7. CONCLUSIONOn gate level, accurate leakage modeling is available, but

as design for low leakage has to start at system level, mod-els at higher abstraction are required. RTL models exist,but because state dependence has the smallest influence toleakage, it was not regarded so far on these higher levels.We showed that leakage can be modeled with 6.7% accu-racy many orders of magnitude faster than SPICE could do.Without regarding state dependency, the accuracy wouldonly be 14.1%. Even though, there are some further im-provements possible:

We are currently working at an extension to the top-downmodel enabling estimation for all 3 important sources ofleakage, subthreshold currents, gate leakage and junctionleakage due to BTBT. Also modeling gate and junction leak-age the variance of other parameters as oxide thickness andchannel doping are regarded, too. Further work may also an-alyze the effect of temperature and supply voltage variationsinside a component, as we assumed both being constant forall transistors inside one component.

Finally, the model proposed here has to be embedded intoa high level power estimation tool determining the input pa-rameters temperature and supply voltage by iteratively com-puting local energy consumption and the resulting thermalincrease and voltage drop. Having RT level leakage estima-tion is the key enabler for leakage aware RT synthesis.

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