Analog and Mixed-Signal Modeling with VHDL-AMS Abdulhadi Shoufan and Sorin Alexander Huss...

Analog and Mixed-Signal Analog and Mixed-Signal Modeling with VHDL-AMSModeling with VHDL-AMS

Abdulhadi Shoufan and Sorin Alexander Huss

21.04.23 EWME A. Shoufan Slide 1

ISS

CASEDCASED

SecureSecureThingsThings

SecureSecureServicesServices

Secure Secure DataData

Center for Advanced Security Research DarmstadtCenter for Advanced Security Research Darmstadt


OutlineOutline

Signal-flowSignal-flow&&

Physical Physical ModelingModeling

VHDLVHDLReviewReview

VHDL-AMSVHDL-AMS

IntroductionIntroductionintointo

VHDL-AMSVHDL-AMS

Mixed-SignalMixed-SignalModelingModeling

Mixed-domainMixed-domainModelingModeling

Modeling in Modeling in Frequency Frequency

DomainDomain

ModelModelExecutionExecution


Hardware: Essential FeaturesHardware: Essential Features

DealyReaction on

signal events

HardwareHardwareUnitUnit

ArchitectureInterface

OperationsSignals

ConnectionsComponents

Structure

Processing Time behavior

Function

SynchronousLogic

AsynchronousLogic

ParametersSignals


VHDL: A Hardware Description LanguageVHDL: A Hardware Description Language

Processing Time behavior

DealyReaction on

signal events

ConnectionsComponents

HardwareHardwareUnitUnit

ArchitectureInterface

OperationsSignals

StructureFunction

SynchronóusLogic

AsynchronousLogic

ParametersSignals

Event-conditional Assignment

Event-non-conditional Assignment

entityentity

architecture

process Instantiation

port/genericmap

componentAssignment

:=, <=

signal, variable +, -, and, or,…after clause

genericsport signals


OutlineOutline

Signal-flowSignal-flow&&



VHDL-AMSVHDL-AMS


VHDL-AMSVHDL-AMS




DomainDomain



Why VHDL-AMS?Why VHDL-AMS?

Time and Value Time and Value ContinuityContinuity

What characterizes an analog system?What characterizes an analog system?

AcausalityAcausality

Physical NaturePhysical Nature

Why can VHDL not model these characteristics?Why can VHDL not model these characteristics?


Why VHDL-AMS?Why VHDL-AMS?

)102sin(0.2)( 3ttV R=1 kΩ

Can you model this circuit is VHDL?Can you model this circuit is VHDL?


Sinusoidal Source Model in VHDL?Sinusoidal Source Model in VHDL?

)102sin(0.2)( 3ttV

?


Resistor Model in VHDL?Resistor Model in VHDL?

R=1 kΩ

Can to connect this model Can to connect this model to the source model?to the source model?


VHDl-AMS ModelsVHDl-AMS Models

R

Pr1

Pr2

Ir

Vr

Is

Ps1

Ps2

Vs


TestbenchTestbench

R

Pr1

Pr2

Ir

Vr

Ps1

Ps2

Vs

T

Is


OutlineOutline

Signal FlowSignal Flow&&



VHDL-AMSVHDL-AMS


VHDL-AMSVHDL-AMS




DomainDomain



From Signal-flow Model to Physical Model From Signal-flow Model to Physical Model

Controller SYSTEM+

-

Control ValueErrorSet Value Output Actual Value

Noise

-

+

t

I

deT

K

0

)(

dt

tdeKTD

)(

)(tKe

Control ValueSet Value

Acutal Value

Error

e(t)



R

R

R

R+-

R

C

+

-

R

R

R

R

+

-R

RC

+-

R

R

+

-

t

I

deT

K

0

)(

dt

tdeKTD

)(

)(tKe

Control ValueSet Value

Acutal Value

Error

e(t)



Signal Flow ModelSignal Flow ModelPhysical ModelPhysical Model

NaturesNatures

TerminalsTerminals

Across QuantitiesAcross Quantities

Through QuantitiesThrough Quantities

Port QuantitiesPort Quantities

Free QuantitiesFree Quantities


OutlineOutline




VHDL-AMSVHDL-AMS


VHDL-AMSVHDL-AMS




DomainDomain



Mixed-Signal ModelingMixed-Signal Modeling

AD InterfaceAD InterfaceDA InterfaceDA Interface

Q‘above(expression)Q‘above(expression)Break StatementsBreak Statements

Vin R

cS

S = 1S = 0

Vin R

cRon=0.1Ω

Vin R

cRoff=1MΩ

SV1

V2

if (V1‘above(V2)) thenif (V1‘above(V2)) then

S <= ´1´S <= ´1´

........

break on S;break on S;


Phase Locked LoopPhase Locked Loop


OutlineOutline




VHDL-AMSVHDL-AMS


VHDL-AMSVHDL-AMS




DomainDomain



Defining own NaturesDefining own Natures

naturenature nature_name nature_name is is

subtype_1 subtype_1 acrossacross

subtype_2 subtype_2 through through

reference_terminal_name reference_terminal_name referencereference;;


Mixed-Technology DC MotorMixed-Technology DC Motor

Source: The System Designer‘s Guide to VHDL-AMS, P. Ashenden et. Al. Source: The System Designer‘s Guide to VHDL-AMS, P. Ashenden et. Al.


OutlineOutline




VHDL-AMSVHDL-AMS


VHDL-AMSVHDL-AMS




DomainDomain



Modeling in the Frequency DomainModeling in the Frequency Domain

Source QuantitiesSource Quantities u(t) = 2.5sin(u(t) = 2.5sin(ωωt + t + ππ/2)/2)Example:Example:

Q‘ltf(num, den)Q‘ltf(num, den)


OutlineOutline




VHDL-AMSVHDL-AMS


VHDL-AMSVHDL-AMS




DomainDomain



Model ExecutionModel Execution

AnalysisAnalysis

ElaborationElaboration

ExecutionExecution

EquationSystem

Processes& Nets

Analog SolverDigital Kernelbreak

Q‘above(E)

universal time


Model ExecutionModel Execution


Summary: HintsSummary: Hints

1. Do not teach a hardware description language as a programming language.

2. Before representing a new language construct or aspect make a case for it.

3. Improve understanding the language by describing its semantics for the simulator, the synthesizer,...

4. HDL is a language. To learn it, students must speak it. Give them the chance to do it and help them to get their first program running.


Analog and Mixed-Signal Modeling with VHDL-AMS Abdulhadi Shoufan and Sorin Alexander Huss...

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