AN EFFICIENT CORDIC PROCESSOR FOR COMPLEX DIGITAL … · CORDIC algorithm was first developed by...

International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) Web Site: www.ijettcs.org Email: [email protected], [email protected]

Volume 2, Issue 2, March – April 2013 ISSN 2278-6856

Volume 2, Issue 2 March – April 2013 Page 306

Abstract—Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. This paper presents the design of pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver. The design of CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in proposed design can is achieved through optimization in the number of micro rotations. For better loop performance of first order complex DPLL and to minimize quantization error, the numbers of iterations are also optimized. Keywords— CORDIC, Digital Signal Processing, Pipelined Architecture, DPLL, Micro-rotation, Loop performance.

1. INTRODUCTION CORDIC algorithm was first developed by Jack E. Volder in 1959 [1]. CORDIC algorithm is extremely useful in efficient and effective implementation of DSP systems . This algorithm allows implementation of trigonometric functions like sine, cosine, magnitude and phase with great precision by using just simple shift and adding operations . Although the same functions can be implemented using multipliers, variable shift registers or Multiply Accumulator (MAC) units, but CORDIC can implement these functions efficiently. This paper designs first order complex DPLL using CORDIC which functions as a FSK demodulator [8]. In digital PLL, an adjustable local sine wave generator and phase detector is required. The sine and cosine terms can be calculated using polynomial approximation, e.g. Taylor series. But it requires a considerable amount of hardware space on the silicon substrate. Interpolation method using table look-up may be the other solution. But it also requires large number of gates and ROM memory. The CORDIC offers the opportunity to calculate the desired functions in a simple and efficient way. Due to the simplicity of the

involved operations, the CORDIC realization of complex DPLL is very well suited in VLSI hardware design and its implementation. This paper first describes the CORDIC algorithm and then pipelined architecture design [9]. Thereafter, implementation with adjustment of micro-rotation has been described. Finally CORDIC realization of a complex phase locked loop is described. 2. LITERATURE SURVEY

Generation of FM signal: Generation frequency modulation signal is two types i) Direct method ii) In direct method The basic principle involved in this is change in reactance of an oscillator circuit in accordance with the modulating voltage constitutes one of the methods of developing a frequency-modulated wave.

Recall that a multivibrator output consists of the fundamental frequency and all of its harmonics. Unwanted even harmonics are eliminated by using a SYMMETRICAL MULTIVIBRATOR circuit, as shown in figure 2-13. The desired fundamental frequency, or desired odd harmonics, can be amplified after all other odd harmonics are eliminated in the LCR filter section . A single frequency-modulated carrier is then made available for further amplification and transmission. Proper design of the multivibrator will cause the frequency deviation of the carrier to faithfully follow (referred to as a "linear" function) the modulating voltage. This is true up to frequency deviations which are considerable fractions of the fundamental frequency of the multivibrator. The principal design consideration is that the RC coupling from one multivibrator transistor base to the collector of the other has a time constant which is greater than the actual gate length by a factor of 10 or more. Under these conditions, a rise in base voltage in each transistor is essentially linear from cutoff to the bias at which the transistor is switched on. Since this rise in base voltage is a linear function of time, the gate length will change as an inverse function of the modulating voltage. This action will cause the frequency to change as a linear function of the modulating voltage.

3. FPGA and TOOL FLOW 3.1 FPGA Design Considerations FPGA demonstrates good performance and logic capacity

AN EFFICIENT CORDIC PROCESSOR FOR COMPLEX DIGITAL PHASE LOCKED

LOOP

Md nayazoor rahaman, Abdul Hafeez sajid

1M.Tech., 2M.Tech,AMISTE,HOD(ECE),Associate Prof.




by exploiting parallelism. At present single FPGA platform can play multi-functions, including control, filter and system. FPGA design flow is a three-step process consisting of design entry, implementation, and verification stages, as shown in Fig 3.1.The full design flow is an iterative process of entering, implementing, and verifying the design until it is correct and complete. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before Synthesis tools translate the design into real hardware (gates and wires). HDL describes hardware behavior. There are main differences between traditional programming languages and HDL. The Traditional languages are a sequential process whereas

HDL is a parallel process. HDL runs forever whereas traditional

programming language will only run if directed.

Fig 3.1: FPGA design flow 3.2 Evolution of Programmable Logic Devices The first device developed later specifically for implementing logic circuits was the Field-Programmable Logic Array (FPLA), or simply PLA for short. A PLA consists of two levels of logic gates: a programmable “wired” AND-plane followed by a programmable “wired” OR-plane. A PLA is structured so that any of its inputs (or their complements) can be AND’ed together in the AND-plane; each AND-plane output can thus correspond to any product term of the inputs. Similarly, each OR-plane output can be configured to produce the logical sum of any of the AND-plane outputs. With this structure, PLAs are well-suited for implementing logic functions in sum-of-products form.

Fig 3.2 Structure of a PAL

Field-Programmable Gate Arrays (FPGAs). Like MPGAs,

FPGAs comprise an array of uncommitted circuit elements, called logic blocks, and interconnect resources,

but FPGA configuration is performed through programming by the end user. An illustration of a typical FPGA architecture. As the only type of FPD that supports

very high logic capacity, FPGAs have been responsible for a major shift in the way digital circuits are designed.

Fig 3.3: structure of an FPGA

3.3 Spartan -3E Configuration

Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA’s configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of seven different modes • Master Serial from a Xilinx Platform Flash PROM. • Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash. • Slave Serial, typically downloaded from a processor. • Slave Parallel, typically downloaded from a processor. • Boundary Scan (JTAG), typically downloaded from a processor or system tester.

The Spartan-3E FPGA Select I/O interface supports many popular single-ended and differential standards.Spartan-3E FPGAs support the following single-ended standards: • 3.3V low-voltage TTL (LVTTL) • Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V. • 3V PCI at 33 MHz, and in some devices, 66 MHz. Spartan-3E FPGAs support the following differential standards: • LVDS. • Bus LVDS. • 2.5V LVPECL inputs. 4. FM MODEM IMPLEMENTATION-IV 4.1 Block Diagram: The proposed design consists of the reprogrammable, area optimized and low-power features. The modulator and demodulator contain a compressed direct digital synthesizer (DDS) for generating the carrier frequency with spurious free dynamic range. The demodulator has been implemented based on the digital phase locked loop



Volume 2, Issue 2 March – April 2013 08

(DPLL) technique. The same DDS has been used for demodulating the modulated signal. The proposed FM modem has been implemented and tested using Spartan 3e board as a target device. This Section describes the principle and architecture of FM modulator and FM demodulator. 4.2 Explanation of working blocks for FM Modulation: The main modules in the modulator are:

1. Accumulator 2.Phase accumulator 3.DDS

Figure 4.1 Block diagram of FM modulator

4.2.1 Accumulator/integrator: Accumulator block is a register where 8-bit input data is converted to 16 bit. This block consists of two registers and an adder. The output of one register is added with the output of another register. The output of the accumulator is given to multiplier. The other input to the multiplier is factor which is named as “k factor”. The value of the k factor is “001”. 4.2.2 Phase accumulator: The phase accumulator consists of phase increment register, adder and phase register. The phase increment register stores the instantaneous phase increment values resulting from frequency modulation control block. This is fed to a 8 bit adder as one of its input. The other input for adder is phase register output. The phase register holds the instantaneous phase for each clock pulse. The accumulated phase also is represented by 8 bits, which limits the maximum phase by 11111111, and addition by 1 to maximum value causes the phase to become 00000000 This is expected and desired since the Look Up Tables are programmed to consider 255 as highest phase value and phase increment by one results next cycle of waveform. Since 8 bits are used to represent the 0O to 360O the increment in digital phase value by one causes effective increment of 1.40625O (results by dividng 360O with 256 maximum possible combinations of 8 bits) . This also implies that outputs can’t have more that 256 samples for one cycle. 4.2.3 DDS: The basic block diagram of DDS implemented is shown in the below Figure. All the blocks are connected with common clock and reset signals. The delta phase value decides the phase increment for each clock pulse. Hence decides the resulting signal frequency. The Frequency modulating instantaneous value is added to the delta phase value which causes instantaneous change in frequency. Due to the digital nature of the modulator only at each clock tick the modulating signal value shall affect the resulting frequency. If the modulating signal is analog then an Analog Digital converter must be used to digitize the modulating signal which can be used in DDS.

Figure 4.2 Basic Block diagram of Direct Digital Frequency Synthesizer implemented in this project.

The phase accumulator produces accumulated phase value for each clock pulse. In case if the DDS is used for phase modulation then instantaneous phase modulating signal value is added to the phase output of phase accumulator. This resulting phase value is given to the four Look Up Tables. Each Look Up Table is configured to produce a specific waveform. The logic used to generate the Look Up Tables is discussed in the further sections. The outputs of four Look Up Tables are given to the input lines a 4 to 1 Multiplexer. This multiplexer connects one of the inputs to the output depending on the select lines. 4.3 Explanation of working blocks FM Demodulator: The main blocks in demodulator are:

1. DDS core 2.Filters 3.Arc tan estimator 4.Loop filter

Figure 4.3 Demodulation block diagram(dpll)

4.3.1 DDS: This block is used for carrier generation. The Block is same as explained in FM modulator. The increment word is given to this block is dependent on the main output (named as correction signal) and constant (ref_freq_word="00000010000000000000000000"). 4.3.2 Filter: The carrier waves (Cosine and Sine) that are generated by DDS core is given as input to the filter. The direct form of FIR filter is standard linear convolution, which described the output as convolution of input and impulse response of the filter. y[n] = x[n]*c[n] = ∑ x[k]c[n-k] = ∑ c[k]x[n-k]. Where c[n] values represent filter coefficients, and x[n] represents the input samples. The figure shows the direct form FIR structure




Figure 4.4: Direct form 6-tap FIR filter.

Finite impulse response (FIR) filters are the most popular type of filters implemented in software. This introduction will help you understand them both on a theoretical and a practical level. Filters are signal conditioners. Each functions by accepting an input signal, blocking prespecified frequency components, and passing the original signal minus those components to the output.

Frequency response: Simple filters are usually defined by their responses to the individual frequency components that constitute the input signal. There are three different types of responses. A filter's response to different frequencies is characterized as pass band, transition band, or stop band.

Figure 4.5 The response of a lowpass filter to various input frequencies

4.4 Finite impulse response:

Finite impulse response (FIR) filter is a filter structure that can be used to implement almost any sort of frequency response digitally. An FIR filter is usually implemented by using a series of delays, multipliers, and adders to create the filter's output. Figure 2 shows the basic block diagram for an FIR filter of length N. The delays result in operating on prior input samples. The hk values are the coefficients used for multiplication, so that the output at time n is the summation of all the delayed samples multiplied by the appropriate coefficients.

Figure 4.6. The logical structure of an FIR filter

The process of selecting the filter's length and coefficients is called filter design. The goal is to set those parameters such that certain desired stopband and passband parameters will result from running the filter. Most engineers utilize a program such as MATLAB to do their filter design. But whatever tool is used, the results of the design effort should be the same:

A frequency response plot, like the one shown in Figure 1, which verifies that the filter meets the desired specifications, including ripple and transition bandwidth.

The filter's length and coefficients.

In terms of the standard arc tan function, whose range is (−π/2, π/2), it can be expressed as follows:

Notes:

This produces results in the range (−π, π], which can be mapped to [0, 2π) by adding 2π to negative values.

Thus implementations of atan(y) will probably choose to compute atan2(y,1).The following expression derived from the tangent half-angle formula can also be used to define atan2.

This expression may be more suited for symbolic use than the definition above. However it is unsuitable for floating point computational use as it is undefined for y = 0, x < 0 and may overflow near these regions.

The formula gives an NaN or raises an error for atan2 (0, 0), but this is not an issue since atan2(0, 0) is not defined. A variant of the last formula is sometimes used in high precision computation. This avoids overflow but is always undefined when y = 0:

Figure 4.7 Atan2 round a circle




The diagram alongside shows values of atan2 at selected points on the unit circle. The values, in radians, are shown inside the circle. The diagram uses the standard mathematical convention that angles increase anticlockwise (counterclockwise), and zero is to the right. Note that the order of arguments is reversed; the function atan2(y, x) computes the angle corresponding to the point (x, y).

The diagram below shows values of atan2 for points on the unit circle. On the x-axis is the complex angle of the points, starting from 0 ( point (1,0) ) and going anticlockwise (counterclockwise), through points:

(0, 1) with complex angle π/2 (in radians),

(−1, 0) with complex angle π,

(−1, −1) with complex angle 3π/2,

to (1, 0) with complex angle 0 = (2nπ mod 2π).

The diagrams below show 3D view of respectively atan2(y, x) and arctan(y/x) over a region of the plane. Note that for atan2, rays emanating from the origin have constant values, but for atan lines passing through the origin have constant values. For x>0, the two diagrams give identical values. This module gives the frequency.

A proportional–integral–derivative controller (PID controller) is a generic control loop feedback mechanism (controller) widely used in industrial control systems – a PID is the most commonly used feedback controller. A PID controller calculates an "error" value as the difference between a measured process variable and a desired set point. The controller attempts to minimize the error by adjusting the process control inputs.

Figure 4.8 PID controller block diagram

A familiar example of a control loop is the action taken when adjusting hot and cold faucets (valves) to maintain the water at a desired temperature. This typically involves the mixing of two process streams, the hot and cold water. The person touches the water to sense or measure its temperature. Based on this feedback they perform a control action to adjust the hot and cold water valves until the process temperature stabilizes at the desired value. The sensed water temperature is the process value or

process variable (PV). The desired temperature is called the set point (SP). The input to the process (the water valve position) is called the manipulated variable (MV). The difference between the temperature measurement and the set point is the error (e) and quantifies whether the water is too hot or too cold and by how much. The transfer function of the PID controller looks like the following:

Kp = Proportional gain

KI = Integral gain

Kd = Derivative gain

The values are kp is "0000000000000010" -- 0.09375 with Q7 format ki is "0000000000000001" -- in Q7 format kd is "0000000000000010" -- 0.09375 with Q7 format

Tuning a control loop is the adjustment of its control parameters (gain/proportional band, integral gain/reset, derivative gain/rate) to the optimum values for the desired control response. Stability (bounded oscillation) is a basic requirement, but beyond that, different systems have different behavior, different applications have different requirements, and requirements may conflict with one another.

If the PID controller parameters (the gains of the proportional, integral and derivative terms) are chosen incorrectly, the controlled process input can be unstable, i.e. its output diverges, with or without oscillation, and is limited only by saturation or mechanical breakage. Instability is caused by excess gain, particularly in the presence of significant lag. Generally, stability of response is required and the process must not oscillate for any combination of process conditions and set points, though sometimes marginal stability (bounded oscillation) is acceptable or desired.

4.5 Effects of increasing a parameter independently The response from arctan estimator is given to Loop filter. This helps in minimizing the error. The output is given to filter block. 5. Simulation Results and Analysis-V The FM modem process and the developed architecture for the required functionality were discussed in the previous chapters. Now this chapter deals with the




simulation and synthesis results of the FM process. Here Modelsim tool is used in order to simulate the design and checks the functionality of the design. Once the functional verification is done, the design will be taken to the Xilinx tool for Synthesis process and the net list generation. 5.1 Simulation Results: The test bench is developed in order to test the modeled design. This developed test bench will automatically force the inputs and will make the operations of algorithm to perform.

5.2 Simulation Results from Model sim:

Figure 5.1: Simulation Results

5.3. Synthesis Report: Final Results RTL Top Level Output File Name: syn_top_fm_mod_and_demod.ngr 5.3.1. Device utilization summary: Selected Device: 3s500efg320-5 Number of Slices : 1905 out of 4656 40% Number of Slice Flip Flops : 3396 out of 9312 36% Number of 4 input LUTs : 3404 out of 9312 36% Number of IOs : 18 Number of bonded IOBs : 18 out of 232 7% Number of MULT18X18SIOs: 17 out of 20 85% Number of GCLKs : 1 out of 24 4% Timing Summary: Speed Grade: -5 Minimum period: 14.407ns (Maximum Frequency: 69.413MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 4.040ns Maximum combinational path delay: 2.655ns 6. CONCLUSION This paper presented the demodulation technique with a complex DPLL using CORDIC unit. The use of pipelined CORDIC computational architecture makes implementation of this kind of demodulator easier. Numbers of micro rotations have been adjusted so as to achieve better loop performance and speed of operation while minimizing angleapproximation error. CORDIC algorithm is used to achieve high throughput facilitating real time signal processing, especially in FSK demodulator, by using complex Digital Phase Locked Loop. The inherent issue of CORDIC i.e. overflow is quite appropriately resolved using proposed design. The property of good convergence of CORDIC is efficiently used in this application. REFERENCES [1] J.E. Volder. "The CORDIC Trigonometric Computing

Technique".IRE Transactions on Electronic Computing, vol EC-8, pp 330-334, Sept 1959.

[2] Y.H. Hu. "CORDIC-Based VLSI Architectures for Digital Signal Processing" IEEE Signal Processing Magazine, Vol. 9, No. 3, pp. 16- 35, 1992.

[3] Andraka R.A., "Survey of CORDIC Algorithms for FPGA Based Computers”, Proceedings of the 1998 ACM/SIGDA 6th International Symposium on FPGAs, pp 191-200, Monterey, California, Feb.22-24, 1998.

[4] S. Wang, V. Piuri, E. E. Swartzlander. Jr., "Granularly-pipelined CORDIC processors for sine and cosine generators”, IEEE International Conference on Acoustics, Speech, and Signal Processing ICASSP, vol. 6, pp. 3298-3301, 1996.




[5] Y.H. Hu. "The Quantization Effects of the CORDIC Algorithm" IEEE Trans. Signal Processing, vol. 40, No. 4, pp. 834-844, Apr. 1992.

[6] M. Chakraborty, A. S. Dhar and Moon Ho Lee, “A Trigonometric Formulation of the LMS Algorithm for Realisation of Pipelined CORDIC,” IEEE Trans. Circuits and Systems, vol. 52, no. 9, pp. 530-534, Sep.2005.

[7] Byron Edde, “Radar Principles, Technology, Applications” Pearson Education,Inc. ISBN 978-81-317-1383-9.

[8] Vuori J., “Implementation of a Digital Phase-Locked Loop Using CORDIC Algorithm”, IEEE International Symposium on Circuit and Systems, Atlanta, USA 1996, pp. IV-164-167.

AN EFFICIENT CORDIC PROCESSOR FOR COMPLEX DIGITAL … · CORDIC algorithm was first developed by...

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