AMP-microprocessor Engineeringc… · Web viewblock of linear memory. The only difference between...

PROGRAM 1

W.A.P to load a register AX with 4321H, BX with 5678H.Run using debug command.

Microsoft (R) Macro Assembler Version 5.00 -1

data segmentd1 dw 4321hd2 dw 5678hdata endscode segmentassume cs:code,ds:datastart:mov ax,datamov ds,axmov ax,d1mov bx,d2int 03hcode endsend start

Microsoft (R) Macro Assembler Version 5.00 Symbols-1

PROGRAM-2

W.A.P to add 30H and 50H store result in register BX examine the status of the flag.Run using debug command

Microsoft (R) Macro Assembler Version 5.00 Page 1-1

data segmentd1 db 30hd2 db 50hdata endscode segmentassume cs:code,ds:datastart:mov ax,datamov ds,axmov bh,00hmov bl,d2mov al,d1add bl,alint 03hcode endsend start


PROGRAM-3

W.A.P to subtract 50H from AX.Examine the flags.Run using Debug Command.


data segmentd1 db 55hdata endscode segmentassume cs:code,ds:datastart:mov ax,datamov ds,axsub ax,d1int 03hcode endsend start


PROGRAM-4

W.A.P. to get 8 bit number from keyboard print it on the screen using int 21H.

Microsoft (R) Macro Assembler Version 5.00 Page 1-1printstring macro msgmov ah,09hmov dx,offset msgint 21hendmdata segmentcr equ 0dhmsg1 db 'enter the 8 bit data:','$'str1 db 80 dup(0)data ends code segmentassume cs:code,ds:datastart:mov ax,datamov ds,axprintstring msg1

mov si,offset str1 l1:mov ah,08h int 21h mov [si],al mov ah,02h mov dl,al int 21h inc si cmp al,cr jnz l1 mov ax,4c00hint 21hcode ends end start

PROGRAM-5

W.A.P to add two 16-bit numbers. Store result in AX(lowerword) and DX(higher word) registers.Print the result on screen.


data segment d1 dw 0564h d2 dw 9457h data ends

assume cs:code,ds:data

code segment

start: mov ax,data mov ds,ax mov ax,d1 mov dx,0000h add ax,d2 jnc label1 inc dx label1:int 21h code ends end start


PROGRAM-6

W.A.P to subtract two 32-bit numbers.store result in AX(lower word) and DX(higher order) registers.print the result on screen.


data segment d1 dw 5454h d2 dw 9768h d3 dw 8979h d4 dw 8475h data ends assume cs:code,ds:datacode segment start: mov ax,data mov ds,ax mov ax,d2 sub ax,d4 mov dx,d1 sbb dx,d3 int 21h code ends end start


PROGRAM:7

W.A.P to multiply 8-bit bit numbers entered by using MUL instruction.


data segment d1 db 99h d2 db 99h data ends assume cs:code,ds:data code segment start: mov ax,data mov ds,ax mov ah,00h mov al,d1 mul d2 int 21h code ends end start

Microsoft (R) Macro Assembler Version 5.00 Symbols

W.A.P. to divide two 8-bit numbers entered by user using DIV instructions.


data segment d1 db 99h d2 db 99h data ends assume cs:code,ds:datacode segment start: mov ax,data mov ds,ax mov ah,00h mov al,d1 div d2 int 21h code ends end start

Microsoft (R) Macro Assembler Version 5.00 Symbols

PROGRAM-8

W.A.P to get 10 bytes from user.Find its average and display result on the screen.


data segment d1 db 01h,02h,03h,04h,05h,06h,07h,08h,09h,0Ah data ends assume cs:code,ds:data code segment start: mov ax,data mov ds,ax mov cx,000Ah xor ax,ax lea bx,d1 lable1: mov dl,[bx] add al,dl inc bx loop lable1 mov dl,000Ah div dl int 21h code ends end start


PROGRAM-9

W.A.P to find MAX number from an array of 10-bytes entered by user.Display result on screen.


data segment d1 db 25h,45h,30h,20h,21h,90h,47h,75h,09h data ends code segment assume cs:code,ds:data start: mov ax,data mov ds,ax mov cx,0009h lea bx,d1 mov al,[bx] l2: inc bx mov ah,[bx] cmp al,ah jnc l1 mov al,ah l1:loop l2 int 03h code ends end start


PROGRAM-10

W.A.P.to store any array of 10 bytes in ascending order.(bubble sort).


data segmentd1 db 20h,21h,19h,24h,18hdata endscode segmentassume cs:code,ds:datastart:mov ax,datamov ds,axmov cx,0004hmov ax,0000hlea bx,d1mov di,bxmov dx,0000hmain: mov si,di mov ah,[si] mov bx,cxloop1: inc si mov al,[si] cmp ah,al jc exc mov ah,al exc: dec bx jnz loop1 mov dl,[si] mov dh,[di] mov [si],dh mov [di],dl inc d

dec cx jnz main int 03h code ends end start


PROGRAM-11

W.A.P. to find factorial of N.display result on screen.


data segmentd1 dw 0007hdata endscode segmentassume cs:code ds:datastart:mov ax,datamov ds,axmov cx,d1mov ax,cxdec cxl1:mul cxloop l1int 03hcode endsend start


PROGRAM-12

W.A.P to reverse the string.


data segment d1 db 'assembly language','$' len equ ($-d1) d2 db 20 dup(0) data ends code segment assume cs:code,ds:data start: mov ax,data mov ds,ax mov bx,len dec bx mov si,offset d1 mov di,offset d2 l1: mov al,[si] mov [di+bx],al cmp al,'$' jz l2 dec bx inc si jmp l1 l2: int 03h code ends end start


PROGRAM-13

W.A.P.to check whether the entered string is palindrome or not? Display “string is palindrome” or :string is not palindrome”


enterstring macro msg mov ah,09h mov dx,offset msg int 21h data segment msg1 db 'malayalam' length equ ($-msg1) msg2 db 'string is pellindrome','$' msg3 db 'string is not pellindrome','$' data ends code segment assume cs:code,ds:data start: mov ax,data mov ds,ax mov ax,0000h mov al,_length mov bx,ax dec bx mov cl,02h div cl mov cl,al mov ch,00h mov si,offset msg1 mov di,si

l1: mov al,[si] mov ah,[di+bx] cmp al,ah jne l2 dec bx inc si loop l1 enterstring msg2 mov ah,09h mov dx,offset msg2 int 21h jmp l3 l2: enterstring msg3 mov ah,09h mov dx,offset msg3 int 21h l3: mov ax,4c00h int 21h code endsend start


PROGRAM-14

W.A.P to validate password.Display “password correct” or “password incorrect” depending on the result .

Microsoft (R) Macro Assembler Version 5.00 Page 1-1printstring macro msg mov ah,09h mov dx,offset msg int 21h endm data segment cr equ 0dh lf equ 0ah password db 'secret',cr msg1 db 'enter password:','$' msg2 db cr,lf,'enter password again:$' msg3 db cr,lf,'you are unathorized person','$' msg4 db cr,lf,'welcome to assembly language pro graming.$' str1 db 80 dup(0) code segment assume cs:code,ds:data start: mov ax,data mov ds,ax printstring msg1 mov ah,09h mov dx,offset msg1 int 21h nextattempt: mov si,offset str1 rdchar: mov ah,08h int 21h mov [si],al push ax mov ah,02h

mov dl,'*' int 21h code endsend start


DATE :

AIM: To Study of 80386 microprocessor.

•The Internal Architecture of 80386 is divided into 3 sections.•Central processing unit•Memory management unit•Bus interface unit•Central processing unit is further divided into Execution unit and Instruction unit•Execution unit has 8 General purpose and 8 Special purpose registers which are eitherUsed for handling data or calculating offset addresses.

80386 Architecture

•The Instruction unit decodes the opcode bytes received from the 16-byte instructionCode queue and arranges them in a 3- instruction decoded instruction queue.•After decoding them pass it to the control section for deriving the necessary controlSignals. The barrel shifter increases the speed of all shifts and rotate operations.• The multiply / divide logic implements the bit-shift-rotate algorithms to complete theOperations in minimum time.•Even 32- bit multiplications can be executed within one microsecond by the multiply and Divide logic.•The Memory management unit consists of a Segmentation unit and a Paging unit.•Segmentation unit allows the use of two address components, viz. segment and offset forRelocability and sharing of code and data.•Segmentation unit allows segments of size 4Gbytes at max.

•The Paging unit organizes the physical memory in terms of pages of 4kbytes size each.•Paging unit works under the control of the segmentation unit, i.e. each segment is furtherDivided into pages. The virtual memory is also organizes in terms of segments and pagesBy the memory management unit.•The Segmentation unit provides a 4 level protection mechanism for protecting andIsolating the system code and data from those of the application program.•Paging unit converts linear addresses into physical addresses.•The control and attribute PLA checks the privileges at the page level. Each of the pagesMaintains the paging information of the task. The limit and attribute PLA checks segmentlimits and attributes at segment level to avoid invalid accesses to code and data in theMemory segments.•The Bus control unit has a prioritizer to resolve the priority of the various bus requests.This controls the access of the bus. The address driver drives the bus enable and addressSignal A0 – A31. The pipeline and dynamic bus sizing unit handle the related controlSignals.•The data buffers interface the internal data bus with the system bus.Signal Descriptions of 80386•CLK2 :The input pin provides the basic system clock timing for the operation of 80386.•D0 – D31:These 32 lines act as bidirectional data bus during different access cycles.•A31 – A2: These are upper 30 bit of the 32- bit address bus.• BE0 toBE3 : The 32- bit data bus supported by 80386 and the memory system of 80386can be viewed as a 4- byte wide memory access mechanism. The 4 byte enable linesBE0 to BE3 , may be used for enabling these 4 blanks. Using these 4 enable signal lines,the CPU may transfer 1 byte / 2 / 3 / 4 byte of data simultaneously.•ADS#: The address status output pin indicates that the address bus and bus cycledefinition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective validsignals. The 80383 does not have any ALE signals and so this signals may be used forlatching the address to external latches.•READY#: The ready signals indicates to the CPU that the previous bus cycle has beenterminated and the bus is ready for the next cycle. The signal is used to insert WAITstates in a bus cycle and is useful for interfacing of slow devices with CPU.•VCC: These are system power supply lines.•VSS: These return lines for the power supply.•BS16#: The bus size – 16 input pin allows the interfacing of 16 bit devices with the 32bit wide 80386 data bus. Successive 16 bit bus cycles may be executed to read a 32 bitdata from a peripheral.•HOLD: The bus hold input pin enables the other bus masters to gain control of thesystem bus if it is asserted.

•HLDA: The bus hold acknowledge output indicates that a valid bus hold request hasbeen received and the bus has been relinquished by the CPU.•BUSY#: The busy input signal indicates to the CPU that the coprocessor is busy withthe allocated task.•ERROR#: The error input pin indicates to the CPU that the coprocessor hasencountered an error while executing its instruction.•PEREQ: The processor extension request output signal indicates to the CPU to fetch adata word for the coprocessor.•INTR: This interrupt pin is a maskable interrupt, that can be masked using the IF of theflag register.•NMI: A valid request signal at the non-maskable interrupt request input pin internallygenerates a non- maskable interrupt of type2.•RESET: A high at this input pin suspends the current operation and restart the executionfrom the starting location.•N / C : No connection pins are expected to be left open while connecting the 80386 inthe circuit.

Register Organization•The 80386 has eight 32 - bit general purpose registers which may be used as either 8 bitor 16 bit registers.•A 32 - bit register known as an extended register, is represented by the register namewith prefix E.•Example : A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc.•The 16 bit registers BP, SP, SI and DI in 8086 are now available with their extended sizeof 32 bit and are names as EBP,ESP,ESI and EDI.•AX represents the lower 16 bit of the 32 bit register EAX.• BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can be usedas independent 16 bit registers.•The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS.•The CS and SS are the code and the stack segment registers respectively, while DS, ES,FS, GS are 4 data segment registers.•A 16 bit instruction pointer IP is available along with 32 bit counterpart EIP.

•Flag Register of 80386: The Flag register of 80386 is a 32 bit register. Out of the 32

bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.Two extranew flags are added to the 80286 flag to derive the flag register of 80386. They are VMand RF flags.•VM - Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086 modewithin the protection mode. This is to be set only when the 80386 is in protected mode. Inthis mode, if any privileged instruction is executed an exception 13 is generated. This bitcan be set using IRET instruction or any task switch operation only in the protectedmode.•RF- Resume Flag: This flag is used with the debug register breakpoints. It is checked atthe starting of every instruction cycle and if it is set, any debug fault is ignored during theinstruction cycle. The RF is automatically reset after successful execution of everyinstruction, except for IRET and POPF instructions.•Also, it is not automatically cleared after the successful execution of JMP, CALL andINT instruction causing a task switch. These instruction are used to set the RF to thevalue specified by the memory data available at the stack.•Segment Descriptor Registers: This registers are not available for programmers, ratherthey are internally used to store the descriptor information, like attributes, limit and baseaddresses of segments.•The six segment registers have corresponding six 73 bit descriptor registers. Each ofthem contains 32 bit base address, 32 bit base limit and 9 bit attributes. These areautomatically loaded when the corresponding segments are loaded with selectors.•Control Registers: The 80386 has three 32 bit control registers CR0, CR2 and CR3 tohold global machine status independent of the executed task. Load and store instructionsare available to access these registers.•System Address Registers: Four special registers are defined to refer to the descriptortables supported by 80386.•The 80386 supports four types of descriptor table, viz. global descriptor table (GDT),interrupt descriptor table (IDT), local descriptor table (LDT) and task state segmentdescriptor (TSS).•Debug and Test Registers: Intel has provide a set of 8 debug registers for hardwaredebugging. Out of these eight registers DR0 to DR7, two registers DR4 and DR5 are Intelreserved.•The initial four registers DR0 to DR3 store four program controllable breakpointaddresses, while DR6 and DR7 respectively hold breakpoint status and breakpoint controlInformation.•Two more test register are provided by 80386 for page caching namely test control andTest status register.

•ADDRESSING MODES: The 80386 supports overall eleven addressing modes tofacilitate efficient execution of higher level language programs.•In case of all those modes, the 80386 can now have 32-bit immediate or 32- bit registeroperands or displacements.•The 80386 has a family of scaled modes. In case of scaled modes, any of the indexregister values can be multiplied by a valid scale factor to obtain the displacement.•The valid scale factor are 1, 2, 4 and 8.•The different scaled modes are as follows.•Scaled Indexed Mode: Contents of the an index register are multiplied by a scale factorthat may be added further to get the operand offset.•Based Scaled Indexed Mode: Contents of the an index register are multiplied by a scalefactor and then added to base register to obtain the offset.•Based Scaled Indexed Mode with Displacement: The Contents of the an index registerare multiplied by a scaling factor and the result is added to a base register and adisplacement to get the offset of an operand.

Real Address Mode of 80386•After reset, the 80386 starts from memory location FFFFFFF0H under the real addressmode. In the real mode, 80386 works as a fast 8086 with 32-bit registers and data types.•In real mode, the default operand size is 16 bit but 32- bit operands and addressingmodes may be used with the help of override prefixes.•The segment size in real mode is 64k, hence the 32-bit effective addressing must be lessthan 0000FFFFFH. The real mode initializes the 80386 and prepares it for protectedmode.

•Memory Addressing in Real Mode: In the real mode, the 80386 can address at the most1Mbytes of physical memory using address lines A0-A19.•Paging unit is disabled in real addressing mode, and hence the real addresses are thesame as the physical addresses.•To form a physical memory address, appropriate segment registers contents (16-bits) areshifted left by four positions and then added to the 16-bit offset address formed using oneof the addressing modes, in the same way as in the 80386 real address mode.•The segment in 80386 real mode can be read, write or executed, i.e. no protection isavailable.•Any fetch or access past the end of the segment limit generate exception 13 in realaddress mode.•The segments in 80386 real mode may be overlapped or non-overlapped.•The interrupt vector table of 80386 has been allocated 1Kbyte space starting from00000H to 003FFH.

Aim –To study of microprocessor 80486.

•The 32-bit 80486 is the next evolutionary step up from the 80386.•One of the most obvious feature included in a 80486 is a built in math coprocessor. Thiscoprocessor is essentially the same as the 80387 processor used with a 80386, but beingintegrated on the chip allows it to execute math instructions about three times as fast as a80386/387 combination.•80486 is an 8Kbyte code and data cache.•To make room for the additional signals, the 80486 is packaged in a 168 pin, pin gridarray package instead of the 132 pin PGA used for the 80386.

Pin Definitions•A 31-A2 : Address outputs A31-A2 provide the memory and I/O with the address duringnormal operation. During a cache line invalidation A31-A4 are used to drive themicroprocessor.•A20M3 : The address bit 20 mask causes the 80486 to wrap its address around fromlocation 000FFFFFH to 00000000H as in 8086. This provides a memory system thatfunctions like the 1M byte real memory system in the 8086 processors.•ADS : The address data strobe become logic zero to indicate that the address buscontains a valid memory address.•AHOLD: The address hold input causes the microprocessor to place its address busconnections at their high-impedance state, with the remainder of the buses staying active.It is often used by another bus master to gain access for a cache invalidation cycle.•BREQ: This bus request output indicates that the 486 has generated an internal busrequest.• 3 0 BE -BE : Byte enable outputs select a bank of the memory system when informationis transferred between the microprocessor and its memory and I/O.The BE3 signal enables D31 – D24 , BE2 enables D23-D16, BE1

enables D15 – D8 and BE0 enables D7-D0.•BLAST: The burst last output shows that the burst bus cycle is complete on the nextactivation of BRDY# signal.

•BOFF : The Back-off input causes the microprocessor to place its buses at their highimpedance state during the next cycle. The microprocessor remains in the bus hold stateuntil the BOFF# pin is placed at a logic 1 level.•NMI : The non-maskable interrupt input requests a type 2 interrupt.•BRDY : The burst ready input is used to signal the microprocessor that a burst cycle iscomplete.•KEN : The cache enable input causes the current bus to be stored in the internal.•LOCK : The lock output becomes a logic 0 for any instruction that is prefixed with thelock prefix.•W / R : current bus cycle is either a read or a write.•IGNNE : The ignore numeric error input causes the coprocessor to ignore floating pointerror and to continue processing data. The signal does not affect the state of the FERRpin.•FLUSH : The cache flush input forces the microprocessor to erase the contents of its8K byte internal cache.•EADS : The external address strobe input is used with AHOLD to signal that anexternal address is used to perform a cache invalidation cycle.•FERR : The floating point error output indicates that the floating point coprocessor hasdetected an error condition. It is used to maintain compatibility with DOS software.• 8 BS : The bus size 8, input causes the 80486 to structure itself with an 8-bit data bus toaccess byte-wide memory and I/O components.• 16 BS : The bus size 16, input causes the 80486 to structure itself with an 16-bit data bus

to access word-wide memory and I/O components.•PCHK : The parity check output indicates that a parity error was detected during aread operation on the DP3 – DP0 pin.•PLOCK : The pseudo-lock output indicates that current operation requires more thanone bus cycle to perform. This signal becomes a logic 0 for arithmetic coprocessoroperations that access 64 or 80 bit memory data.•PWT: The page write through output indicates the state of the PWT attribute bit in thepage table entry or the page directory entry.•RDY : The ready input indicates that a non-burst bus cycle is complete. The RDYsignal must be returned or the microprocessor places wait states into its timing until RDYis asserted.•M / IO : Memory / IO# defines whether the address bus contains a memory address oran I/O port number. It is also combined with the W/ R signal to generate memory andI/O read and write control signals.

EFLAG Register of The 80486•The extended flag register EFLAG is illustrated in the figure. The only new flag bit isthe AC alignment check, used to indicate that the microprocessor has accessed a word atan odd address or a double word boundary.•Efficient software and execution require that data be stored at word or double wordboundaries.

80486 Memory System•The memory system for the 486 is identical to 386 microprocessor. The 486 contains 4Gbytes of memory beginning at location 00000000H and ending at FFFFFFFFH.•The major change to the memory system is internal to 486 in the form of 8K byte cachememory, which speeds the execution of instructions and the acquisition of data.•Another addition is the parity checker/ generator built into the 80486 microprocessor.•Parity Checker / Generator : Parity is often used to determine if data are correctly readfrom a memory location. INTEL has incorporated an internal parity generator / decoder.•Parity is generated by the 80486 during each write cycle. Parity is generated as evenparity and a parity bit is provided for each byte of memory. The parity check bits appearon pins DP0-DP3, which are also parity inputs as well as parity outputs.•These are typically stored in memory during each write cycle and read from memoryduring each read cycle.•On a read, the microprocessor checks parity and generates a parity check error, if itoccurs on the PCHK# pin. A parity error causes no change in processing unless the userapplies the PCHK signal to an interrupt input.•Interrupts are often used to signal a parity error in DS-based computer systems. This issame as 80386, except the parity bit storage.•If parity is not used, Intel recommends that the DP0 – DP3 pins be pulled up to +5v.

•CACHE MEMORY: The cache memory system stores data used by a program and alsothe instructions of the program. The cache is organised as a 4 way set associative cache

with each location containing 16 bytes or 4 doublewords of data.•Control register CR0 is used to control the cache with two new control bits not presentin the 80386 microprocessor.•The CD ( cache disable ) , NW ( non-cache write through ) bits are new to the 80486and are used to control the 8K byte cache.•If the CD bit is a logic 1, all cache operations are inhibited. This setting is only used fordebugging software and normally remains cleared. The NW bit is used to inhibit cachewrite-through operation. As with CD, cache write through is inhibited only for testing.For normal operations CD = 0 and NW = 0.•Because the cache is new to 80486 microprocessor and the cache is filled using burstcycle not present on the 386.

80486 Memory Management

•The 80486 contains the same memory-management system as the 80386. This includes apaging unit to allow any 4K byte block of physical memory to be assigned to any 4K byteblock of linear memory. The only difference between 80386 and 80486 memorymanagementsystem is paging.•The 80486 paging system can disabled caching for section of translation memory pages,while the 80386 could not.

•If these are compared with 80386 entries, the addition of two new control bits isobserved ( PWT and PCD ).•The page write through and page cache disable bits control caching.•The PWT controls how the cache functions for a write operation of the external cachememory. It does not control writing to the internal cache. The logic level of this bit isfound on the PWT pin of the 80486 microprocessor. Externally, it can be used to dictatethe write through policy of the external caching.•The PCD bit controls the on-chip cache. If the PCD = 0, the on-chip cache is enabled forthe current page of memory.•Note that 80386 page table entries place a logic 0 in the PCD bit position, enablingcaching. If PCD = 1, the on-chip cache is disable. Caching is disable regard less ofcondition of KEN#, CD, and NW.

Cache Test Registers•The 80486 cache test registers are TR3, TR4, TR5.•Cache data register (TR3) is used to access either the cache fill buffer for a write testoperation or the cache read buffer for a cache read test operation.•In order to fill or read a cache line ( 128 bits wide ), TR3 must be written or read fourtimes.•The contents of the set select field in TR5 determine which internal cache line is writtenor read through TR3. The 7 bit test field selects one of the 128 different 16 byte widecache lines. The entry select bits of TR5 select an entry in the set or the 32 bit location inthe read buffer.•The control bits in TR5 enable the fill buffer or read buffer operation ( 00 )•Perform a cache write ( 01 ), Perform a cache read ( 10 )•Flush the cache ( 11 ).•The cache status register (TR4) hold the cache tag, LRU bits and a valid bit. Thisregister is loaded with the tag and valid bit before a cache a cache write operation andcontains the tag, valid bit, LRU bits, and 4 valid bits on a cache test read.•Cache is tested each time that the microprocessor is reset if the AHOLD pin is high for 2clocks prior to the RESET pin going low. This causes the 486 to completely test itselfwith a built in self test or BIST.

•The BIST uses TR3, TR4, TR5 to completely test the internal cache. Its outcome isreported in register EAX. If EAX is a zero, the microprocessor, the coprocessor andcache have passed the self test.•The value of EAX can be tested after reset to determine if an error is detected. In most ofthe cases we do not directly access the test register unless we wish to perform our owntests on the cache or TLB.

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