11th March 2008 AIDA FEE Report 1

AIDA Front end electronics

Report February 2008

11th March 2008 AIDA FEE Report 2

FEE – module spec• Readout 128 strips of DSSSD via 8 , 16 channel ASICs. • Module width : 8cm.• Data rate defined by 10Khz implantation rate in the Detector.• Timestamp readout data items based on the BUTIS distributed clock.• ASIC analogue data triggered by per channel discriminator.

– Energy– Timestamp

• ASIC preamp output digitised at 50Mhz – 14bits.– Leading Edge discriminator.– Energy (MWD) including Base Line Restore.– Waveform ( T(trig-pretrig) to T(trig+postrig) ) – max 20uS– T0 calculation based on the rising edge of Waveform.– Timestamp– Pile-up detection and ???

• Data items formatted and output using Gigabit Ethernet.• Output Fast OR of all 128 channel discriminators.

11th March 2008 AIDA FEE Report 3

Architecture• Based on the GREAT TDR. ( Operating in Jyvaskyla )• Timestamped data items. • Module divided between two identical boards. Each board has 4

ASICs – 64 channels – 1 FPGA ( $1,002.00 )• Cooling for the electronics with water cooled metal plates and

conformal heat conducting foam sheet. ( Based on AGATA digitiser )

• In the FPGA – Five data sources

• 4 ASIC analogue (16 channels each )• 1 Digital ( 64 channels )• Each source provides Single Time Ordered data stream (STO).

– Xilinx MicroBlaze soft processor running Linux ( under investigation ) controls acquisition.

– Gigabit Ethernet link with TCP/IP for control and transfer of Data items.

• The Five data sources to be merged by external processing.• ASICs mounted on mezzanine cards with connection to

detectors via “crate” mounted board and Kapton cable.

11th March 2008 AIDA FEE Report 4

Board block Diagram

Mezzaninecardconnector

16 channelASIC

9222ADFADC

9222ADFADC

16 bitADC

Singletodiffn.

16

1

2I C controls

16 discriminator outputs

Readout controlsClocksReset

10LVDS pppp20

10LVDS pppp20

4

- - AIDA FEE Support connections and parts for one chip

Power Supplies

Daughtercardconnector

16 channelASIC

9222ADFADC

9222ADFADC

16 bitADC

Single

todiffn.

16

1

2I C controls

N p ppppppppppppp ppppppp2

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercardconnector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Single

todiffn.

16

1

2I C controls

N p ppppppppppppp ppppppp2

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercardconnector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Single

todiffn.

16

1

2I C controls

N p ppppppppppppp ppppppp2

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercardconnector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Single

todiffn.

16

1

2I C controls

N p ppppppppppppp ppppppp2

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Xilinx 5 95XC VSX T-? 1136FF 640 I/O

344 4used forASICS

ContainsMIcroblaze processor

Readout State Machine

64 channels ofEnergy/Timing/Waveform

4 channels of ASIC readout

Timestamp logic

TEMACPHY

32MBSDRAM

FLASH for boot load of

LINUX

45RJ

Timestampexternalinterface

Consoleinterface

Oscillators

- -64AIDA FEE ( ) AAAA to DAQ block diagram

High speed Discr OR

JTAG

11th March 2008 AIDA FEE Report 5

Module construction

Water cooled metal

Water cooled metal

FPGA & FADCs

FPGA & FADCs

Water cooled metal

Water cooled metal

View A

Kapton Cable toto detector

Connector board View A

45RJGigabit

45RJGigabit

HDMIClock,SYNC,Reset

Power, Disc_out

HDMIClock,SYNC,Reset

Power

JTAG

JTAG

11th March 2008 AIDA FEE Report 6

FPGA outline block diagram

4One of

64One of

Microblaze runningLINUX

Max rate = ( 60K 8x )

+( 10k 2024 )x

=>20720000, ,bytes/sec

Include edge events=>

61200000, ,bytes/sec

SharedRAM

60Max rate K events/sec

SharedRAM

SharedRAM

SharedRAM

60Max rate K events/sec

pp6 0 K events/sec

60Max rate K events/secStatemachine

Q

ADC

ASIC16

channels

Timestamp

16 Discriminators

Sync/Pse/Res

ToDigital

Max rate 30K - 16events/sec bit dataStatemachine

Q 1024 x

(48 + 64 + 3)

Energy MWD

Leading Edgediscriminator

Slow in Fast out Waveform RAM "Circulating Buffer"

Timestamp

Sync/Pse/Res

1024 long (20uS ) Floating pointtime vernier

calc.

Q 10 36x

Energy

DMAMemorymanager

64DDRSDRAM

32 bit

FIFO 3072 16x

FPGA outline block diagram

11th March 2008 AIDA FEE Report 7

ASIC – Analogue• Expect 6 items per implant at 10Khz.

– 5 from implantation– 1 from decay

• Use “flip-flop” memory for item store.• Each item is two 32 bit words. ( GREAT format )• Use 4 BRAMs as two blocks of 1024 x 32• 512 items can be stored which is 512/6 = 85 implants.

Thus the maximum time that can be stored is 2 x 85 x 100uS = 17mS.

• The time to readout one store at a 32bit bus speed of 100Mhz is 1024 x 10nS = 10uS

• All four stores can be read in 40uS. • A CPU tick of 1mS will be fine

11th March 2008 AIDA FEE Report 8

ASIC Digital – 1 channel• Expect 3 items per implant at 10Khz. All in

different channels - on average.– 2 from edge of the implant.– 1 from decay.

• Item comprises Energy, Time , Ident, Quality, and Waveform ( size is WS ).

• Waveform is 20uS>WS>2uS• Incoming data is stored in a “circulating buffer”.• When LE discriminator and MWD logic agree

signal is sent to the Timestamp Queue.• Energy and quality is sent to its Channel Queue

and when available waveform is sent to a FIFO.

11th March 2008 AIDA FEE Report 9

Digital readout

•Readout Controller reads the Timestamp Q and transfers items for all the active channels to the SDRAM directly through a port in the MPMC. •Two ports are used.•The data for the waveform is transferred to the external SDRAM as 32 bits at 100Mhz so it takes 5uS for a 20uS waveform size.•An Item takes about 6uS to process including the floating point time vernier calculation. ( estimate )

CPU path Control/status

TimestampCounter

Timestamp Q1024 x 115

Digital

48

64

Pause/Resume

Buffer status

Global Clock, Sync and reset

Readout controller

SYNC

MPMC

Floating point time vernier calculator

To External SDRAM

11th March 2008 AIDA FEE Report 10

Time distribution and Power

• One box with a single BUTIS interface• Connects to each board using a standard HDMI

cable. ( High definition TV cable )• Differential signals – Clock, SYNC, Reset, Fast-

OR.• Power • One connector per module so 16 layer system

of 3 DSSSD per layer means 128 sockets.• Prototype will need only 4, so prototype box…

11th March 2008 AIDA FEE Report 11

Questions• Are the Rates correct ?

– Implants 10K => 60K(An) + 30K(Dig) per FPGA max (i.e. per ½ DSSSD side )

– But 1K max rate per channel?• Is the Waveform size range 20uS>WS>2us a reasonable range?• What is the Time vernier calculation?• Is battery backed up Master timestamp required?• Is a Leading Edge Discriminator OK?• Can you define the logical response to multiple hits in one

channel?– Define Pile-up and how to respond to it?

• GREAT buffer overflow is indicated by the Pause/Resume system. Is this OK ?

• The digital Channels will queue a maximum of 60uS of waveform data.– This can be treated as 3 x 20uS or 6 x 10uS or …– Is this too much ? Can I reduce it to 40uS max ?