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ADV784x EDID FEATUREOVERVIEW

What is an EDID? (VGA or HDMI)

Describes the capabilities of the sinkVideo resolutionColor SpacesMaximum Pixel Clock FrequencyAudio Format (PCM, DSD, DST, HBR) (HDMI Only) Audio Sampling Frequency (HDMI Only) Maximum Pixel Clock Frequency

EDID is generally stored in an external storage device

EDID storage device connected to the followingDDC port for HDMI SCL/SDA signals on VGA connector

EDID size for VGA application128 bytes (typical VGA EDID size)

EDID On HDMI Link

HDMI link

TMDS clock, data

SOURCE

SINK

HPD

5V

CEC

DDC

E-EDID

E-EDID On VGA link

VGA Cable

R, G, B channels

SOURCE

SINK

HS, VS signals

5V (Pin 9)

SCL (Pin 15)

SDA (Pin12)

E-EDID

SOURCE

ADV7844/2 Internal E-EDID Features

Up to 512 bytes of shared data for all HDMI/VGA Ports2 shared segments

Two configurations are availableSupports a single EDID up to 512 bytes HDMI EDID Supports two 256 byte EDIDs

Upper segment is for VGA EDID Information (up to 256 bytes) Lower segment is HDMI EDID Information ( 256bytes)

EDID data stored in an external 512 byte SPI EEPROM2K or 4K are external SPI EEPROMs are supported

Segment pointer supported for large EDID (HDMI Only) Required for EDID data bigger than 256 bytes

HDMI EDID Data Structure

EDID 1.3128 bytes

Block 1 – Segment 0

Map Block128 bytes

Block 2 – Segment 0

Mandatory

Optional

Mandatory

CEA Extensions ver. 3128 bytes

Block 3 - Segment 1

CEA Extensions ver. 3128 bytes

Block 3 - Segment 1

CEA Extensions ver. 3128 bytes

Block 3 - Segment 1

CEA Extensions ver. 3128 bytes

Block 3 - Segment 1

CEA Extensions ver. 3128 bytes

Block 4 - Segment 1

VGA E-EDID Data Structure

VGA EDID 1.3128 bytes

Block 1 – Segment 0

EDID Extension (optional) 128 bytes

Block 2 - Segment 0Optional

Mandatory

Internal EDID Controller

EDID ControllerThe EDID controller handles all I2C requests from the DDC and the

I2C portsDVDD is the supply for the EDID ControllerInternal clock oscillator generates clock for the EDID controller.This allows the EDID controller to be active in power down mode

Power On resetA power on reset circuitry generates a reset to the EDID controller

when DVDD is applied

The EDID controller can also be reset through I2C HDCP_REPT_EDID_RESET control.

LDO

HDMIPort A

HDMIPort B

HDMIPort C

HDMIPort D

+5V

+5V

+5V

+5V

+5V (TV supply)

10K

ADV7844/2

+3.3V

+1.8V

DVDDIOTVDD

DVDDCVDDPVDDAVDD

RXD_5V_DET

RXC_5V_DET

RXB_5V_DET

RXA_5V_DET

PWRDNB

SPIEEPROM

512byte(4kbit)

SPI interface4

VGA / HDMI External connections

VGAPort

+5V

LDO

LDO+2.5V

DVDDIO_SDRAM

Power Supply

+5V power supply from HDMI connector Each HDMI connector can source up to 50mA Current only flows from +5V signal toward the part Each supply on the ADV7844/2 must be supplied power when reading internal EDID

even in power down state

Main power supply Source all current when available Current always flows from main supply toward the part

PMOSFET Transistor Transistor is non conducting when the main supply is present Current is drawn from the HDMI connector in power down mode

SPI Interface

Clock speed is ~3MHz

The CPU reads the EEPROM when the supply is available In power down mode Normal power mode

2kb or 4kb EEPROMs supported from the following vendors ATMEL Thomson Microchip

EP_MISO has an internal pull-down

If not required - all pins can be left unconnected

Reading from/Writing to the SPI EEPROM

Reading from SPI EEPROM The CPU reloads the data from the SPI EEPROM to the internal EDID

RAM On reset (if powerdown pin is set low) EDID power-down mode When the self clearing bit LOAD_EDID is set

Storing data to SPI EEPROM In-system-programming of the SPI EEPROM

The internal CPU program the external SPI EEPROM with data from the internal EDID RAM

Steps1. Program the EDID RAM through the main I2C port2. Load the data from the EDID RAM into SPI EEPROM with bit STORE_EDID

Supporting EDID in Powerdown Chassis supply removed When powering the ADV784x from the cable the following requirements need

to be met. Power should be supplied to each of the supplies and the PSS sequence should be

adhered to. In order to ensure that the ADV784x goes into power down mode correctly

the following condition must be met. When entering power down mode, the RESET pin should go low at /or before the

PWRDNB pin. This ensures that the part is fully reset/powered down as EDID power down

mode is enabled.Not adhering to above recommendation will cause the ADV784x to drawn

more current than the 50mA HDMI Specification.

ADV784x EDID CircuitryChassis supply removed Circuitry to ensure that Reset and PWRDNB are pulled low at the same time.