ADSD Fall2011 09 Fixed Point Representation

8/3/2019 ADSD Fall2011 09 Fixed Point Representation

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Dr. Rehan Hafiz Lecture # 08

ADSD Fall 2011


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Course Website for ADSD Fall 2011

http://lms.nust.edu.pk/

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Lectures: Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm

Contact: By appointment/EmailOffice: VISpro Lab above SEECS Library

Acknowledgement: Material from the following sources has been consulted/used in theseslides:1. [CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti2. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan3. [STV] Advanced FPGA Design, Steve Kilts4. Ercegovacs Book: Digital Arithmetic 20045. Dr. Shoab A Khans CASE Lectures on Advanced Digital System Design

Material/Slides from these slides CAN be used with following citing reference:

Dr. Rehan Hafiz: Advanced Digital System Design 2010

Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/


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1 Introduction Outline & Introduction, Initial Assessment of students, Digital design

methodology & design flow2 Verilog+

Combinational Logic

Combinational Logic Review + Verilog Introduction, Combinational Building

Blocks in Verilog

3 Verilog + Sequential Logic Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS),

Sequential Logic in Verilog4 Synthesis in Verilog Synthesis of Blocking/Non-Blocking Statements5 Micro-Architecture

Design Partitioning + RISC Microprocessor + Micro architecture Document

6 Optimizing Speed Architecting Speed in Digital System Design: [Throughput, Latency, Timing]7 Optimizing Area Architecting Area in Digital System Design: [Area Optimization]8 FIR Implementation FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs10 CDC Issues Cross-Clock Domain Issues & RESET circuits11 Fixed-Point Arithmetic Arithmetic Operations: Review Fixed Point Representation12 Adders Adders & Fast Adders Multi-Operand Addition13 Multipliers Multiplication , Multiplication by Constants + BOOTH Multipliers13 CORDIC CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW14 Algorithmic

Transformations for

System DesignDFG representation of DSP Algorithms, Iteration Bound

& Retiming

15 Algorithmic

TransformationsUnfolding

Look ahead transformations16 Project Course Review & Project Presentations

17 Project Project Presentations


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Lecture Overview

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Algorithms, Arithmetic & Numbers

2s Complement Representation

Generating Overflow Flag

Fixed point / Floating point

Qn.m format

Truncating/ Rounding


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Algorithms in Hardware

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Primitives

Addition/subtraction

Multi operand addition

Logical and arithmetic shift

Multiplication by constant

Multiplication

Division Algorithms

Sequenced Composition of Primitives


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Numbers in hardware

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Number

SignedNumber

Positive

Number

NegativeNumber

UnsignedNumbers


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Representing Numbers

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n-bit unsigned Binary Numbers

B = bn-1, bn-2,.., b1, b0 with bi from {0,1}

Negative Number Representation

Signed Magnitude

Ones Complement

Twos Complement


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Signed Magnitude

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Designate left-most bit as a signbit with no arithmetic weight

1-> negative, 0-> positive.

Positive and negative zero (0000vs. 1000)

Difficult to add numbers ofdifferent sign or subtractnumbers of same sign(comparison)

Same sign bits Add and usesame sign

Different signsLogic to decideadd or sub & final sign

N-1 bits are available torepresent magnitude

Range of N-bit signed-magnitudenumber is:

-(2N-1 1) to (2N-1 1)

[CIL]


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Ones Complement

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Flipped bits as negative

number

Positive and negative zero

(0000 vs. 1000)

Subtraction is more

complicated than in 2s-

comp

Range of N-bit signed-

magnitude number is:

-(2N-1 1) to (2N-1 1)


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Twos Complement

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Unified Representation for both positive

& negative numbers in 2s Complement11

Equivalent unsigned representation

Example

For N=8, -10 b11110110

For N=5, -10 b10110

Paper & Pencil

conversion by

scanning from right

to left, leaving the

first one and flipping

all the remaining bits


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Twos Complement

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Arithmetic

+, -, *, / performed in hardware with a unit that cancarry out binary operations of addition and bitwisecomplement.

Addition: Same hardware as binary numbers butreduced dynamic range

Subtraction: Bitwise complements and addition of oneand a number !

Multiplication: Repeated additions Division involves repeated subtraction

Negative of a number : Complement & add 1


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Addition in 2s Complement13


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Addition/Subtraction in 2s

Complement14

Addition in 2s Complement (a+b)

Normal Binary Addition (a+b)

Subtraction in 2s Complement (a-b)

Equivalent to Normal Binary Addition with (a+(-b))

Rather than subtracting add the negative of the

number

Example: (-10)-(10) Drop the Carry outs


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Negating a number in HW

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Addition of number similar to unsigned binary addition

Flip all the bits & Add ONE

Problem Need a Carry Propagate Adder

Solution: Full Adders

Overflow issue due to asymmetric range

Example: Negative of 1000

dd / b f


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Adder/Subtractor for 2s

Complement16


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Knowing Overflow17


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Signed and Unsigned Integers

A Hardware Viewpoint

Hardware cannot distinguish between signed and

unsigned integers

YOU are solely responsible for using the correct

data type with each instruction

Verilog does not provide synthesizable signed

representation

Consider an adder adding two 2s complementnumbers


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Overflow Examples

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+3 0011 +5 0101 +5 0101

+4 0100 +6 0110 -6 1010

-------- -------- --------

+7 0111 +11 1011 -1 1111(signed overflow but not an unsigned overflow)

-5 1011 -3 1101 -5 1011

+6 0110 -4 1100 -6 1010

-------- -------- --------+1 0001 -7 1001 -11 0101

(unsigned & signed overflow)

overflow occurs when:

POS+POS=NEG or

NEG+NEG=POS


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Overflow and Carry Flags

A Hardware Viewpoint

Overflow Unsigned

Carry Out of MSB

2s Complement

Carryout does not indicate overflow

ADDITION

OF = (carry out of the MSB) XOR (carry into the MSB)

SUBTRACTON NEG the source and ADD it to the destination

OF = (carry out of the MSB) XOR (carry into the MSB)


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Knowing your 2s Complement Number for Corner Cases

(Because of the slightly asymmetric range, negation may lead to

overflow! )

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Corner Cases

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There is no equal opposite of -2N-1 in Nbits

2s complement representation

For example, while multiplying two ve

numbers like -4 x -4 , we can get16 and wecant represent this as a 5-bit 2s complement

No.


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Knowing if a number is Negative

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S(N-1) is the MSB of the Sum


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Generating the Flags

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Needs Correction


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Floating Point Numbers

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Representing Fixed Point Numbers

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Insert implicit binary point between two bits

bits to left of point have value 1

bits to right of point have value < 1

29 28 27 26 25 24 23 22 21 20(512) (256) (128) (64) (32) (16) (8) (4) (2) (1)

21 2223242526

(0.5)(0.25)

(0.125)(0.0625)

(0.03125)(0.015625)

0 1 0 0 0 0 1 1 0 1 0 1 1 1 1 0

269.46875

binary point

.


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Qn.m Format

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Qn.m format is a fixed positional number system

for representing floating-point numbers

Qn.msimply means thatN-bit binary number has

n bits to the left and m bits to the right of thebinary point

In case of signed-numbers the MSB is used for

sign


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There is NO Decimal in HW

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1. Define the total No. of bits to represent a No.

(Lets say 10 bits)

2. Fix a Decimal some where in the No.

(Lets say after 2 locations)

Note that there is no decimal in H/W.

FractionalBits

Zeroth Bit

SignBit

-21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8

Floating Point to Fixed Point


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Conversion

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In Qn.m format,

ndepends upon the range of our required integer

m depends upon how much precision we want in the

fractional part of our computation.

Example

Q3.13

1 bit for thesign and 2bits arereserved for

the integerpart

13 bits arereserved forthe fractionalpart



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Conversion31

The algorithm is analyzed for all set of inputs

Range of each variable is observed

Depending upon the precision required, n and m

are specified.

For implementation on programmable

processors, N=16, or 32

For Application Specific Hardware, an optimal

value of N is specified.

xamp e


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xamp eOptimization: Different blocks can have

different range/precision requirement32

AGC Filter

Compress

SpeechSamples

At every point,we check theranges

Q9.12 Format

Q1.17 Format

Q3.18 Format

O/p


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Arithmetic in Q Format33


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Addition in Q Format

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Adding 2 different Qn.m Format numbers we get

Q=QMax(n1,n2) + Max(m1.m2)


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If two numbers a and b of Qn1.m1 and Qn2.m2 formatsrespectively are added, the result is in Qn.m format, where n islarger of n1 and n2 and m is larger of m1 and m2.

Example

0111111001101110

0100Qn1.m1 =

Qn2.m2 =

Qn.m =

Q2.2

Q4.4

Q4.4

ImpliedDecimal


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Sign Extension

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We need to extend the sign bit to its left.

Copying the sign bit to its left doesnt change

the original value of the number


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If two numbers a and b of Qn1.m1 and Qn2.m2 formatsrespectively are added, the result is in Qn.m format, where n islarger of n1 and n2 and m is larger of m1 and m2.

Example

0111011001101110

011111Qn1.m1 =

Qn2.m2 =

Qn.m =

Q2.2 = - 2 + 1 + 0.5 = -0.5

Q4.4 = 1 + 2+ 4 + 0.25 + 0.125 = 7.375

Q4.4 = 2 + 4+ 0.5 + 0.25 + 0.125 = 6.875

ImpliedDecimal

May Require Extension of Fixed Point Numbers


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Bit Growth

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Due the demand for increased number ofbits effective Width of the words willincrease


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Multiplication in Q-Format

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c = a x b

Q n1.m1

Q n2.m2

( a )

( b )

Q (n1+n2) . (m1+m2) ( c )


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Rounding & Truncating

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Truncation

Simple Truncate

An operation similar to floor

Rounding

Or ADD a copy of bit after the truncation point to itself

Rounding Vs. Truncation

Rounding basically weighted truncation.

Algorithmically it is better to round and then truncate inH/W.

Resource-wise Rounding adds overhead


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Thanks

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ADSD Fall2011 09 Fixed Point Representation

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