Total Solution Requirements for Enabling Digital and Analog IP

Adoption

Somnath ViswanathArasan Chip Systems

San Jose, CA, USA

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Agenda

State of SoC Design Total IP Solution Case Study Conclusion

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Trends in IP based SoC design

SoCs of today were systems of yesterday Increasing feature integration and

resultant design complexity of SoCs translated to horizontal specialization viz EDA Companies, IP Companies, Fabs, etc

Design resources and in particular Program Management stretched

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Trends in IP based SoC design

Increasing complexity of SoCs resulting in pervasive use of 3rd party Bus IPs

Higher speeds necessitating an AFE (PHY) Requires a complete IP solution consisting

of RTL IP, PHY IP, vIP, Software stacks and Hardware Platforms for a successful experience

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Analog IP for Bus Interfaces

Trend in BUS Interfaces is increasing speeds Necessitates an Analog Front-end or PHY

• UHS II, USB 2.0, USB 3.0, MIPI D-PHY, M-PHY, PCIe ….

Analog IPs are ‘Hard Macros’ compared to digital ‘soft macros’, hence not easily portable

Silicon proof through Test Chips on different process nodes critical to IP acceptance by customers and to instill confidence

Hence a different kind of IP integration challenge

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Components of SoC Design

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Evolving IP Business

Requires a complete IP solution consisting of RTL IP, PHY IP, vIP, Software stacks and Hardware Platforms for a successful experience

RTL IP

PHY IP

EDA Scripts

Verification IP

Software Stack / Driver

Documentation

Customer Support

Traditional IP Providers Complete IP Providers

Hardware Dvlpt Kits

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…but takes much more

It starts with…

RTLIP Core

Apr 10, 2023 Proprietary Arasan Chip Systems

“A Total IP Solution”

Verification IPBFM, Test SuitesMonitor, Checker

ServicesCustomizationTech Support

PlatformsHDKs, HVPs

Analyzers

SoftwareFirmware, DriversSoftware Stacks

SoC SoC SoC SoC

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RTL IP Cores

3rd Party IP for standardized interfaces• Processors, Peripheral Buses, Internal Buses

RMM (spyglass) compliant Verilog RTL Silicon proven – FPGA or Test Chips Optimized for area and performance Customizable to fit user SoC environment

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verification IP

OVM Verification Environment BFMs (Bus Functional Model) Monitor / Checker Compliance Test Suite Test Vectors Suite

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Software And Services

Firmware and Drivers related to IP cores

Software Stack as a function of OS

Software development/porting services

IP customization & integration services

High quality technical support

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Hardware Platforms

Hardware Development Kits

(HDKs)

Hardware Validation Platforms

(HVPs)

Protocol Analyzers• Exercising & analysis of bus protocol

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MIPI SLIMbus Case Study

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MIPI SLIMbus Case Study

SLIMbus RTL IP & vIP for peripheral & application processors A portable software stack for creating reference designs and

validation of SLIMbus implementations for productization An HDK implementing an instance of host and device for

creating a complete reference designs to enable OEM/ODM’s to use SLIM enabled devices in end products

An analyzer and exerciser tool to help during development, test and integration of SLIM enabled products

Design Services and support to integrate into application and create end products

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Arasan Chip Systems

Founded in 1995• Headquarters in San Jose, California• 100+ Employees Worldwide

Profitable IP Solutions Company delivering highly integrated solutions

• Technology and Solutions Leader – Domain Expertise• Leveraging core competency in standards based compliant IP – Internally developed IP

solutions• Focused on mobile and portable multimedia interface standards, connectivity & bus

interfaces and storage memory controllers

Delivering on a promise to deliver a “Total IP Solution”• Standards Based IP, Verification IP, Hardware Development Kits, Hardware Validation

Platforms, Drivers/Stacks and ICs• Professional Design Services with focus on customization and IP integration into

system-level applications

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IP Portfolio

MIPI: Mobile Industry Processor Interface

• DSI• CSI2• SLIMbus• UniPro• HSI• DigRF 3G/4G• D-PHY: digital• D-PHY: mixed signal• M-PHY: digital• M-PHY: mixed signal• SMIA (not MIPI)

USB: Universal Serial Bus

• USB 3.0 Host• USB 3.0 Device• USB 3.0 Hub• USB 2.0 Host• USB 2.0 Device• USB 2.0 Hub• USB 2.0 OTG• USB 1.1 Host• USB 1.1 Device• USB 1.1 Hub

IP:Intellectual

Property

VIP:Verification IP

Customer Support:Design Services,

Consulting

Hardware:HDK, HVP, Chips

Software:Firmware, Drivers,

Stack

Memory Controllers• SD• SDIO• eMMC• UFS• UHS II• CF• xD• Memory Stick• Memory Stick Pro• CE-ATA• NAND Flash• Multi-Card Reader

* IP can be customized – native local bus, additional features / functions

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IP Portfolio

Controllers• 10/100 Ethernet• 10/100/1000 Ethernet• Gigabit Ethernet• 10 Gigabit Ethernet• 1588• PCI• PCIe• MiniPCI• CardBus• UART• I2C• I2S• SPI

Bus Interfaces• AHB• APB• AXI• BVCI• OCP• Avalon (Altera)• VLIO (Intel)• PIF (Tensillica)

Analog PHYs• DPHY• MPHY• USB 3.0 PHY• UHS II PHY

IP:Intellectual

Property

VIP:Verification IP

Customer Support:Design Services,

Consulting

Hardware:HDK, HVP, Chips

Software:Firmware, Drivers,

Stack

* IP can be customized – native local bus, additional features / functions

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Conclusion

Few design companies can do it all Horizontal specialization and the

establishment of IP business model Design companies can save effort and

improve quality by sourcing complete IP collateral – IP Cores, vIP, Software, HDK from a single vendor

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