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Transcript of Accurate modeling and parameter extraction method
www.elsevier.com/locate/sse
Solid-State Electronics 49 (2005) 1009–1016
Accurate modeling and parameter extraction methodfor organic TFTs
M. Estrada a,*, A. Cerdeira a, J. Puigdollers b, L. Resendiz a, J. Pallares c,L.F. Marsal c, C. Voz b, B. Iniguez c
a Seccion de Electronica del Estado Solido (SEES), Departamento de Ingenierıa Electrica, CINVESTAV, Av. IPN No. 2508,
Apto. Postal 14-740, 07300 DF, Mexicob Departament dEnginyeria Electronica, Universitat Politecnica de Catalunya, C/Jordi Girona, Modul C4, Barcelona 08034, Spain
c Departament dEnginyeria Electronica Electrica i Automatica, Universitat Rovira i Virgili, Avda. Paisos Catalans 26, 43007 Tarragona, Spain
Received 18 November 2004; received in revised form 14 February 2005; accepted 15 February 2005
Available online 31 March 2005
The review of this paper was arranged by Prof. A. Zaslavsky
Abstract
In this paper we demonstrate the applicability of the unified model and parameter extraction method (UMEM), previously devel-
oped by us, to organic thin film transistors, OTFTs.
The UMEM, which has been previously used with a-Si:H, polysilicon and nanocrystalline TFTs, provides a much rigorous and
accurate determination of main electrical parameters of organic TFTs than previous methods. Device parameters are extracted in a
simple and direct way from the experimental measurements, with no need of assigning predetermined values to any other model
parameter or using optimization methods. The method can be applied to both experimental and simulated characteristics of organic
TFTs, having different geometries and mobility. It provides a very good agreement between transfer, transconductance and output
characteristics calculated using parameter values obtained with our extraction procedure and experimental curves. Differences in
mobility behavior, as well as other device features that can be analyzed using UMEM are discussed.
� 2005 Elsevier Ltd. All rights reserved.
Keywords: Organic TFT; Parameter extraction; TFT modeling
1. Introduction
Simulation of devices requires both, an accurate
model to represent the behavior of the device and an
extraction method strictly related to this model to deter-
mine with precision the device parameters required by itand thus by simulation. Modeling of organic TFTs
(OTFTs) has been made, up to now, analytically or
numerically, mostly using the same expressions as for
0038-1101/$ - see front matter � 2005 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2005.02.004
* Corresponding author. Tel.: +52 55 50613786; fax: +52 55
50613978.
E-mail address: [email protected] (M. Estrada).
MOS crystalline devices. However, OTFTs present sev-
eral differences with respect to crystalline (MOSFETs),
amorphous, (a-Si:H TFTs) or polycrystalline Si (polySi
TFTs) devices. According to measured transfer and out-
put characteristics of organic TFTs, it has been observed
that mobility usually increases with gate voltage. It hasalso been reported that mobility increases with VDS
for a given value of VGS, in a more pronounced way
than the mobility of a-Si:H devices with similar geome-
try, [1–3]. This increase of mobility with VDS has been
related to hopping [4]; to a Frenkel–Poole type effect
associated to traps in the material, [5] as well as; to
the lowering of the emission barrier in traps located at
1010 M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016
the boundaries between crystals, since most materials
used to fabricate OTFTs are polycrystalline, [6,7].
OTFTs can present deformation at the origin of the
output characteristics, due to non-ohmic contacts at
drain and source [8–10]. They can also have leakage cur-
rent across the gate dielectric [11] and/or polarization ef-fects [8], which can be significant and have to be taken
into account.
In numerical simulations, the longitudinal field
dependence of the mobility has been introduced by
external models, [5], evaluated by Monte Carlo [1], or
simply not considered, [12].
Some authors have used simulation in SPICE using
the MOSFET model, to which some features as seriesand non-linear resistance at drain and source are some-
times added, [8,2]. The use of the model 15 for a-Si:H
devices in AIMSpice was reported in [13], with an addi-
tional treatment of the series and non-linear OTFTs
resistance. The non-linear OTFT resistance was also
treated in [14]. Although this last approach has some
advantages regarding previous, the method used
for parameter extraction is numerical and among itsdisadvantages are a relatively big number of fitting para-
meters, which can be determined by optimization
methods when using AIMSpice, or through graphical
or derivative methods which are troublesome and impre-
cise due to experimental errors. For example, with AIM-
Spice extractor, it is difficult to obtain the same group of
fitting parameters for all modeled transistor curves,
which also lack physical meaning. In addition, some ofthe extraction procedures, require to previously assume
values to some parameters in order to extract the rest of
them, that is, some parameters cannot be extracted inde-
pendently one from another [15].
In the last years, we have been applying our unified
model and parameter extraction method (UMEM) first
to a-Si:H, [15,16], to polycrystalline, [17] and recently
to nanocrystalline silicon transistors [18]. Among theadvantages of this method are that all above threshold
parameters are extracted from two transfer characteris-
tics, one in the linear and the other in the saturation re-
gion and from the output characteristic of the device
under study, using a single mathematical processing
involving and integral method that additionally reduces
experimental noise. The method can be used to compare
devices with different geometries and fabrication condi-tions under the same parameter extraction conditions.
This method uses analytical expressions for both model-
ing and parameter extraction, so calculations can be
made using any program for mathematical calculations.
In addition it was also implemented in AIMSpice [19].
In this paper we show that UMEM provides an excel-
lent tool for modeling OTFTs with different geometries,
dielectric materials and fabrication processes. We applyit to analyze and compare the mobility behavior of four
different types of pentacene TFTs.
Finally we present a complement to the UMEM in
order to consider, if necessary, the non-ohmic contact
at drain and source, sometimes present in OTFTs. For
this last treatment, analytical expressions are also pro-
vided for modeling this effect and for the extraction of
the required parameters.
2. Main features of unified model and parameter
extraction method (UMEM)
2.1. Summary of steps to extract model parameters
The mobility dependence with gate voltage is de-scribed as [15]:
lFET ¼ l0
ðV GS � V TÞV aa
� �ca¼ lFET0
� ðV GS � V TÞca ð1Þ
where lFET0is the a value of mobility for low perpendi-
cular and longitudinal electric field, VT the threshold
voltage and ca and Vaa are fitting parameters. l0 is usu-ally taken as the band mobility for the material of the
TFT under analysis. Since this parameter is usually esti-
mated, the fitting parameter Vaa is used to adjust lFET0
to the experimental value of the low field mobility for
the device being modeled. Parameter ca is related to
the conduction mechanism and can describe both an in-crease or decrease in mobility with VGS. In the first case,
ca > 0 and in the second ca < 0. The first behavior is typ-
ical of amorphous and nanocrystalline devices and is re-
lated to trap conduction mechanism, while a decrease in
mobility with gate voltage appears in polycrystalline
TFTs when surface scattering starts to be important.
In organic TFTs, as will be shown later, both behaviors
were observed. In this way, extracted fitting parameterscan be used nevertheless, to analyze physical mecha-
nisms that take place in the devices.
Drain current in the linear and saturation regions is
modeled as:
IDS ¼WL� Cdiel
lFET � ðV GS � V TÞ1þ R W
L � CdiellFET � ðV GS � V TÞ� �
� V DSð1þ k � V DSÞ
1þ V DS
V DSsat
h imh i1=m þ I0 ð2Þ
where W is the channel width, L is the channel length,
Cdiel is the gate capacitance, R is source plus drain resis-
tance, I0 is the leakage current and m and k are fitting
parameters related to the sharpness of the knee region
and to the channel length modulation respectively.
Parameter k describes the variation of conductance with
VDS in the saturation region.
The saturation voltage is defined through the satura-tion modulation parameter aS:
V DSsat ¼ aSðV GS � V TÞ ð3Þ
M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016 1011
For the extraction procedure in the above threshold
regime, we will use the same integral function H(VGS)
defined in [15]:
HðV GSÞ ¼R V GS
0IDSðxÞdx
IDSðV GSÞð4Þ
After substituting (1) in (2) and calculating H(VGS) from
(4), the following expression is obtained for above
threshold regime:
H aðV GSÞ ¼1
2þ caðV GS � V TÞ ð5Þ
k ¼ðIDS2ÞðV DS2Þ2
� ½1þ R � K � lFETðV GS1Þ � ðV GS1 � V TÞ� � 1þ V DS2
as�ðV GS1�V TÞ
h imh i1=mK � lFETðV GS1Þ � ðV GS1 � V TÞ
8><>:
9>=>;� 1
V DS2
; ð10Þ
The generalized parameter extraction procedure for dif-
ferent devices and operation regimes can be found in
[15–18]. The steps for the determination of the model
parameters VT, ca, aS Vaa, m and k are summarized
below.
Step no. 1: VT is obtained from the intercept, and cafrom the slope in expression (5).
Step no. 2: From the experimental data, calculate
ðIDSÞ1
1þca vs. (VGS � VT) and its slope Sl.
The value of Vaa is extracted as:
V aa ¼KV DS
Sl1þca
� �1=ca; ð6Þ
where K ¼ WL � l0 � Cdiel. In this form, the three parame-
ters that determine the effective change of the field effectmobility in the above threshold regime are extracted.
Step no. 3: Using the saturation current characteristic
for VDS P VGS � VT, calculate the slope
Ss in the linear region of I1=ð2þcaÞDSsat vs.
(VGS � VT). Parameter aS is extracted as:
aS ¼Ss2þcaV ca
aa
ffiffiffi2
p
Kð7Þ
Step no. 4: Parameter m, is calculated evaluating (2) at
VDSsat for a value of gate voltage near the
maximum measured, neglecting R and k:
m ¼ log 2= logK � lFETðV GSÞ
½1þ K � lFETðV GSÞ � ðV GS � V TÞ�
�
� aSðV GS1 � V TÞIDSsatðV DSsatÞ
�ð8Þ
To determine IDSsat(VDSsat) select a measured output
characteristic for VGS = VGS1, where VGS1 is a value near
the maximum gate voltage value you want to model.
Select a value of VDS in the saturation region, not too
far from the knee of the output selected curve for which
the drain current IDS1 is known frommeasurements. This
drain voltage value will be referred asVDS1 and should be
equal to:
V DS1 ¼ aS � ðV GS1 � V TÞ ð9ÞThis value of IDS1 corresponds to IDSsat(VDSsat) in
expression (8).
Step no. 5: Parameter k is then extracted from:
where VDS2 is selected not too far from the maximum
drain voltage measured in the characteristic to be mod-
eled. IDS2 is the measured drain current for the selected
drain voltage VDS2.
If the slope of the IDS–VGS curve in the linear region
is observed to decrease due to the presence of a series
resistance, the value of this resistance can be determinedas indicated in [15].
OTFT can show a non-linear contact at drain and
source. To model also this region, the following simple
and precise procedure can be used.
2.2. Modeling of OTFTs output characteristics when
non-ohmic contacts are present
If a non-ohmic contact is present at drain and source,
which is frequently observed in OTFTs, the external bias
applied, Vext, will fall part on the non-ohmic contact,
(diode), Vdiode and part on the transistor, VDS, including
its series resistance, that is:
V DSext ¼ V DS þ V diode
¼ IDS
GðV GS; V DSÞþ n � k � T
q� log IDS
Ido
� �
¼ IDS
GðV GS; V DSextÞ � nþ n � k � T
q� log IDS
Ido
� �; ð11Þ
where
GðV GS;V DSextÞ
¼ KlFETðV GSÞ � ðV GS � V TÞ � ð1þ k � V DSextÞ
ð1þ R � lFETðV GSÞ � ðV GS � V TÞÞ � 1þ V DSext
V DSsat
� mh i1=mð12Þ
1012 M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016
and n is a fitting parameter to account for the real volt-
age across the transistor when the diode resistance is
significant.
To model output characteristics presenting this effect,
after following steps 1–4 previously described, the diode
parameters must be determined. It must be indicatedthat for steps 1–4, the transfer curve selected must cor-
respond to a VDSext in the linear region, that at the same
time lies outside of the region affected by the deforma-
tion of the non-linear contact.
2.2.1. Extraction of diode parameters
After parameters VT, ca, aS, Vaa and m are deter-
mined, select an output characteristic with VGS = VGS2
where the non-ohmic contact effect is clearly seen. Plot
the curve log(IDS) vs. VDSext and determine the slope,
B, and the intercept, A, of this curve near the origin.
Using the normal procedure for a diode:
n ¼ log eB � k�Tq
ð13Þ
and
Ido ¼ 10A: ð14Þ
1 ATLAS is property of Silvaco International.
2.2.2. Extraction of fitting parameter nThe effect of the presence of this diode is to reduce the
drain current at small values of bias, when the diode
resistance is high. As the external bias is increased be-
yond the knee of the I–V characteristic of the diode,the drain current increases and starts to be determined
mainly by the transistor. This means that in the output
characteristic, near or after the maximum slope in this
region of deformation, most of the applied voltage starts
to fall across the transistor. For this reason, parameter nis determined as:
n ¼
IDSðV GS2; V ext2ÞG1ðV GS2Þ
� �� IDSðV GS2; V ext1Þ
G1ðV GS2Þ
� �� �
V DS2 � V DS1½ � ð15Þ
where IDS(VGS2,Vext2) and IDS(VGS2,Vext1) are the mea-sured current for the selected output characteristic at
two external bias Vext2 and Vext1 limiting an approxi-
mately linear region of the curve IDS vs. VDSext,, where
the maximum slope of this curve is included. VDS2,
(VDS1) are determined substituting Vext2, (Vext1) and its
corresponding IDS in (8).
G1(VGS2) is the conductance in the linear region eval-
uated for VGS = VGS2:
G1ðV GS2Þ ¼KlFETðV GS2Þ � ðV GS2 � V TÞ
ð1þ R � lFETðV GS2Þ � ðV GS2 � V TÞÞ: ð16Þ
R and lFET are extracted and calculated from extracted
parameters, respectively.
The effect of n is to provide the necessary displace-
ment and adjustment of the slope of the modeled curve
to the measured one, in the region of deformation.
After determining n, calculate k from (11) and (12),
solving for a value of drain voltage VDSext = VDS2 (and
its corresponding IDS = IDS2) not too far from the maxi-mum drain voltage measured in the selected output
curve for VGS2.
Finally, IDS vs. VDS is modeled substituting the
extracted parameters in (11).
3. Experimental part and results
Four different pentacene TFTs, T1, T2, T3 and T4
were studied. All of them are bottom gate pentacene
TFTs on glass substrate. Transistor T1 uses polymethyl
methacrylate (PMMA) as gate dielectric and were pre-
pared as indicated in [20]. The PMMA dielectric thick-
ness is 700 nm thick with a dielectric constant of 3.9.
Pentacene thickness was 160 nm. These devices have
L = 120 and W = 600 lm.T2 type transistors were fabricated by a process sim-
ilar as indicated in [21]. The gate dielectric is a 100 nm
polyvinylphenol (PVP) layer. Pentacene layer thickness
was of 30 nm, W = 500 lm and L = 50 lm.
Transistors T3 type correspond to devices previously
reported in [21], with 120 nm polyvinylphenol (PVP)
layer as gate dielectric, 30 nm of pentacene layer,
W = 500 lm and L = 50 lm.Transistor T4 corresponds to devices previously re-
ported in [22]. The gate dielectric was a 400 nm SiO2
layer. The thickness of the pentacene layer was 50 nm,
W = 220 lm and L = 20 lm. Since we did not have mea-
sured characteristics of T4 type devices, we used simu-
lated characteristics in ATLAS1 to compare with
output characteristics modeled using UMEM. Parame-
ters used for simulation were taken from [5], where itwas shown that they provide an excellent agreement
with measured curves for these devices.
Trap distribution was taken as:
gatailðEÞ ¼ gatail0 exp �ðEc � EÞEatail
� �ð17Þ
gdtailðEÞ ¼ gdtail0 exp �ðE � EVÞEdtail
� �ð18Þ
where gatail0 is the concentration of acceptor tail states at
conduction band Ec equal to1 2.5 · 1018 cm�3; gdtail0 in
the concentration of donor tail states at valence band
EV, equal to 1 · 1018 cm�3 and Eatail = 0.129 eV and
Edtail = 0.5 eV are the activation energy for acceptorand donor tail states respectively.
Table 1
Technological parameters of pentacene transistors
Transistor Pentacene layer [nm] Dielectric gate W [lm] L [lm] Reference
Type [nm]
T1 160 PMMA 700 600 120 [20]
T2 30 PVP 100 500 50
T3 30 PVP 120 500 50 [21]
T4 50 SiO2 400 220 20 [5,22]
Fig. 2. Measured and modeled output characteristics of T2 type
transistor.
M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016 1013
The energy gap was taken as 2.8 eV and permitivity
of ei = 3. The extended states concentration at valence
and conduction bands was taken as 2.88 · 1021 cm�3.
Pentacene is considered to be p-type with hole concen-tration of 5.75 · 1017 cm�3.
According to [5], externally it was added a field
dependence in the form of a � exp½b �ffiffiffiffiF
p�, where F is
the longitudinal electric field, a = 0.5 and b = 3 · 10�3
(V/cm)1/2, to account for the presence of a Frenkel–
Poole effect.
Table 1 shows the summary of the fabrication param-
eters for the four types of transistors.
3.1. Modeling of current–voltage characteristics
Figs. 1–4 show measured and modeled output charac-
teristics of the four types of transistors described. As can
be seen, all devices characteristics analyzed in this work
can be very well modeled using UMEM, without the
need of any additional term to consider Frenkel–Pooleeffect.
In some OTFTs, the dependence of the drain current
with drain voltage in the saturation region of the output
characteristic is more pronounced that the observed in
a-Si:H devices, however it can be still well modeled
through parameter k. This is also in agreement with
reported by [13].
Fig. 1. Measured and modeled output characteristics of T1 type
transistor.
Fig. 3. Measured and modeled output characteristics of T3 type
transistor.
Table 2 shows the summary of extracted parameters
for one transistor of each type of devices.
As we mentioned, one of the advantages of using
UMEM is the possibility of monitoring the behavior
of mobility, as well as to obtain distinguishing features
of each device. For example, from the extracted para-
meters indicated in Table 2, we can see that transistors
T1, T2 and T3 type are normally off, while T4 is nor-mally on. Series resistance reduces from T1 to T4. In this
later case it is so small that cannot be determined.
Fig. 4. Measured and modeled output characteristics of T4 type
transistor.
Fig. 5. Measured and modeled transfer characteristics of T1 type
transistor in the linear and in the saturation regions.
1014 M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016
Parameter as, which is related to the behavior of the out-put characteristic at the onset of saturation, is higher for
transistors T2 and T3 type, which is also observed in the
output characteristics in Figs. 2 and 3, where the linear
region is larger relative to the measured range of VDS.
Also parameter m, related to the knee of the curve at on-
set of saturation is approximately half the observed for
transistors T2, T3 and T4 type.
Fig. 5 shows agreement between modeled transfercurves for T1 type transistor for two values of VDS,
one in the linear region (VDS = �1 V) and the other in
saturation, (VDS = �40 V). As can be seen, the agree-
ment is excellent, using the same group of fitting param-
eters for both curves. This is really difficult to obtain
with other extraction procedures, while using UMEM
is easy, provided you correctly select the voltage range
in the linear and saturation region where the integralfunction H is evaluated. Table 2 also indicates the volt-
age range used for each case. In general, best results are
obtained when the voltage range in both regions is se-
lected near the maximum slope of the corresponding
Table 2
Extracted parameters
T1 T2
Linear region voltage range �(35–39) �(8–
Saturation region voltage range �(30–39) �(8–
Output characteristic VGS [V] �40 �14
VT [V] �4.1 �2.6
ca 1.9 0.6
Vaa [V] 1.7 · 103 106
lFET0[cm2/V s] 7.4 · 10�7 0.058
R [kX] 1.1 · 104 200
as 0.39 1.7
m 1.27 2.8
k [1/V] �3.5 · 10�3 �1.1
n – 8.9
I0 [A] – 1.9 ·n – 1.37
transfer curve, trying to cover the widest possible region
where function H(VGS) is linear with VGS.
Another feature worth to remark is the comparison
of the VT values obtained by our method and by the
standard method for crystalline devices based in theffiffiffiffiffiffiffiIDS
pvs. VGS. In Fig. 6 we plotted
ffiffiffiffiffiffiffiIDS
pand I ð1þcaÞ
DS vs.
VGS curves for one T1 type transistor. If VT is obtained
for this device using affiffiffiffiffiffiffiIDS
pvs. VGS curve, as is fre-
quently done by authors, the value obtained is around
�18 V. This will not correspond to what is observed
from measured output characteristics, where transistor
is clearly off for VGS around �4 V. The cause of this is
understood from Fig. 6, where it is clear that the curveffiffiffiffiffiffiffiIDS
pvs. VGS does not present any region where you
can assure that there is a linear behavior. However, with
the representation I ð1þcaÞDS vs. VGS, there is a wide linear
region, in which VT can be determined accurately. Say-
ing it in other words, OTFTs do not show the square
root behavior of drain current with drain voltage typical
T3 T4
11) �(10–20) �(60–100)
11) �(15–20) �(80–100)
�20 �40
�3.9 +12.3
0.15 �0.072
1.4 · 103 1.7 · 10�4
0.52 0.7
14 �0
1.4 0.935
2.97 2.8
· 10�2 9.6 · 10�5 �2 · 10�4
– –
10�8 – –
– –
0 5 100
5
15
IVGS-VTI [V]
IVGS-VTI [V]
Transistors T2, T3 and T4 type
T3
T2
T4
0 5 10 15 20 25 30 350
1x10-4
2x10-4
3x10-4
4x10-4
5x10-4
6x10-4
7x10-4
Transistor T1 type
µ FET/µ
FETo
[V]γ a
µ FET/µ
FETo
[V]γ a
(a)
(b)
Fig. 7. Relative behavior of mobility normalized to lFET0as function
of the gate overvoltage. (a) For transistors T2, T3, and T4. (b) For
transistor T1.
-10 0 10 20 30 400.00
0.05
0.10
0.15
0.20
0.25
0.30
-VGS [V]
I ID
SI1/
(1+γ
a)[µ
A]
[µA
]
1/(1
+γa)
T1 type transistorVDS= 40 Vγα = 3.07
0.00
0.02
0.04
0.06
0.08
IIDS I 1/2
1/2
Fig. 6. Comparison of the drain current dependence with gate voltage
if the present mobility model, (1), or the crystalline-like model is used.
M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016 1015
of crystalline devices. In fact, other amorphous devices,
as for example a-Si:H and nanocrystalline Si TFTs, do
not show this dependence either.
OTFTs can present significant VT shifts at room tem-
perature when a positive or negative gate voltage is ap-
plied. This situation must be considered when modeling
the current voltage characteristics. Since UMEM re-
quires measurements of transfer curves in linear and sat-uration regions as well as the output characteristic, in
order to extract the device parameters, measurements
must be done so that gate and drain voltage variations
start from the same initial value in the three measured
curves, usually in the sense of increasing its absolute
value.
UMEM can also be used to determine VT shifts as
was done in [23].UMEM also allows to extract subthreshold parame-
ters in a-Si:H, polycrystalline and Si nanocrystalline
TFTs, [16–18]. In the case of OTFTs, surface and gate
leakage currents can be significant, so subthreshold re-
gion is usually determined by them and not by traps.
For this reason, it has not been possible up to now to
deal with this region.
3.2. Mobility behavior
Regarding the mobility model, parameter ca is relatedto the dependence of mobility with VGS, while
lFET0¼ l0
V caaafits the modeled value of mobility to its mea-
sured value at low gate voltages slightly higher than VT.
Fig. 7a shows the relative behavior of mobility normal-
ized to lFET0for transistors T2, T3 and T4 type. As can
be seen transistor T4 shows a mobility decreasing with
VGS, resulting in a negative value for parameter ca. As
already indicated, the series resistance is very small for
T4 type devices and VT is positive and quite large, which
is not a typical behavior for these OTFTs. However, the
model can represent well their output characteristics
without adding any other dependence with the longitu-
dinal field as the one included in [5]. According to results
presented, it was perfectly possible to model the OTFTs
behavior of all OTFTs analyzed, with the common
expression (2), through parameter k.For the other three types of transistors, mobility in-
creases with VGS, resulting in positive values of ca. Thismobility dependence with VGS of transistors T2 and T3type is similar to the observed for a-Si:H TFTs. Mobility
for T2 type transistors depends much less with VGS than
for T3 type transistors, which can be associated to a
higher value of resistance, an order more. Transistor
T1 has much higher series resistance and lower effective
mobility compared to T2 and T3. The effective mobility
increases more rapidly with VGS, but remains at lower
absolute values, see Fig. 7b. This is supposed to be ob-tained because the pentacene layer in T1 was deposited
at lower temperature and directly on top of the dielec-
tric, which is expected to produce smaller grains.
With the above analysis of the four different types of
OTFTs, we have illustrated the applicability of UMEM
to modeling OTFTs, as well as its advantages in inter-
preting and comparing differences in their behavior
through the extracted parameters, which in this caseare not only fitting parameters. This advantage is not
trivial compared with other methods and is especially
1016 M. Estrada et al. / Solid-State Electronics 49 (2005) 1009–1016
important for modeling and analyzing OTFTs, where the
electrical characteristics of devices fabricated under dif-
ferent conditions and materials can be quite significant.
4. Conclusion
We presented the application of our unified model
and parameter extraction method, (UMEM), to organic
TFTs. The procedure for the extraction of the model
parameters was complemented to consider the presence
of non-ohmic contacts that frequently appear in these
devices. It was demonstrated that UMEM provides a
more precise modeling with simpler parameter extrac-tion method for a wide variety of organic TFTs, fabri-
cated under different conditions and having different
materials and geometries.
In the analysis of four different types of OTFTs, we
also demonstrated its advantages in interpreting and
comparing differences in the behavior of the devices
through the extracted parameters. This advantage is
not trivial compared with other methods and is speciallyuseful in characterizing OTFTs, where differences in the
behavior of devices fabricated under different conditions
and materials can be quite significant.
According to our results, it is perfectly possible to
model the OTFTs current–voltage characteristics with
the common expression (2), through parameter k.
Acknowledgements
We want to thank J. Deen, from McMaster Univer-
sity and M. Halik and H. Klauk from Infineon Technol-
ogies for providing OTFTs measurements, as well as for
valuable discussions.
This work was supported by CONACYT project
39708 in Mexico, by CICYT of the Spanish Governmentunder program TIC2002-04263 and TIC2002-04184, as
well as by the Generalitat de Catalunya in Spain under
program PICS2003-21.
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