ABCN&HCC Status

1

ABCN&HCC Status

• Joel de Witt, University of Santa Cruz, California.• M. Newcomer, N. Dressnandt, University of Pennsylvania.• Matt Warren, Samer Kilani, UCL.• Michelle Key-Charriere, RAL.• D. La Marra, University of Geneva.• F. Anghinolfi, J. Kaplon, CERN.• W. Dabrowski, K. Swientek, Akademia Górniczno-Hutnicza, Krakow.

AUW 2011 CERNABCN&HCC 130 nm Development

CERN AUW Week16/11/2011

iTK-SC Stave or Module

CERN AUW Week 2

Actual Stavelet Status (4 detectors, 8 hybrids, 160 ABCN)

128 ch ABCN 250 FE ASIC Back-end Tail (Signals, Power)

16/11/2011

iTK-SC Stave or Module

CERN AUW Week 3

Develop 256 ch.130nm CMOS FE chip (ABCN 130)

Develop 130nm CMOS Hybrid Controller chip (HCC)

16/11/2011

HCC Controller Chip 1.2V operation 130nm Process

CERN AUW Week 4

R3

Hybrid Controller

PLL

ABC Cmd

LCL CmdSR / SetupDCS RO

Data Concentrator

FiFo

Dat

a/C

LK E

ncod

e

DCS

BC/L1 phaseD

ata

II

L0_L1

Xon/off

Xon/off

Data Loop

Data Loop

BC ABC Beam Clock

R3s_L1

CMD_L0

St_Clk

CMD_BC

DRC Data Readout Clock

Hybrid @ bits V(temp), V(analog)

Hybrid (ABC130) side

Serv

ice

side

Bussed Signals o

n Hybrid

One serial Loop

Data I and Data II are separately enabled redundant outputs to the same Stave bus data pair.

Dat

a I

16/11/2011

Hybrid Controller Chip

R3

Hybrid Controller

DLL

ABC Cmd

LCL Cmd

SR / Setup

DCS RO

Dat

a/C

LK E

ncod

e

DCS

BC/L1 phase

Dat

a II

L0_L1

Xon/off

Xon/off

Data Loop

Data Loop

BC (Beam Clock 40MHz)

R3s_L1

CMD_L0St_Clk

DRC (Data Readout Clock 160MHz)

Hybrid bits One serial

Loop

Dat

a I

516/11/2011

ABC130 Chip

Direction (1-bit)

BidirectionalTransceivers160MHz

ReceiversDelay~2.5ns

DriversDelay ~1ns

HCC – ABC130 chip LVS communication 10 ABCN IN A ROW

Programmable current drive (4-bits)


Direction (1-bit)


CMD_BC

ABC130 Chip

inout

Receivers

BC

CMD_L0

R3s_L1

DRC

inoutinoutinoutinout

inoutinoutinout

inoutinoutinoutinout

CO

RE

Enable (1-bit)

Enable (1-bit)

Xon / Xoff

Data: 160Mbits/s)

Prog

ram

mab

le

dela

y ad

just

FIFO

/ D

ata

Con

cent

rato

r320 MHz

CERN AUW Week

ABCN 130 nm – Simplified block Diagram

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ABCN level block diagram.

Detector pads: 256 input pads

Front End x256

R3L1_Buffer

L1_DCL

R3_DCL

ReadOutBlock

Serial interface

L0_Buffer

Comparators

Adjacent chip

Command Decoder

COM/L0 R3/L1

Top_Logic

CERN AUW Week

Serves 2 rows of128 x 2cm strips

2 Levels of bufferingR3 (local readout, fast)L1 (full readout, slow)

16/11/2011

Buffer Size

• Buffers sizingL0 Latency“L0 Buffer (Pipeline)” 256 time slots = 6.4us max

L1 (R3) Latency“R3L1 Buffer” 256 events (768 Time slots) @ 1MHz Write rate = 256 us max

7CERN AUW Week16/11/2011

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ABCN130 Read Out Module

DCLR3

DCLL1

ThruDataIn

ControlStatusDCS

51

51

Local FiFO

Local FiFO

READOUT

1

Local MUX & Priority setting

Thru MUX & Priority setting

SERIALIZER ThruDataOut

(59 bits DataPacket)

1x118 bits

51

51

+ Typ(4) + ChipID(4) + Header(1) + Last bit (1)

nn Local FiFO

nn

thruFIFO

51

Priority Reg

nn Local FiFO

nn

Prio

rity

orde

r

High

Low

CERN AUW Week

Data Packet from adjacent chip

Data Packet To next chip

16/11/2011

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ABCN 130nm : 59-bit data packet per chip

L0_3BC Packet L0_1BC Packet R3 Packet

Start Bit Start Bit Start Bit

Chip_ID[3:0] Chip_ID[3:0] Chip_ID[3:0]

Type [3:0] Type [3:0] Type [3:0]

L0ID [7:0] L0ID [7:0] L0ID [7:0]

BCID [7:0] BCID [7:0] BCID [7:0]

clst1_ch[7:0] clst1_ch[7:0] clst1_pos[7:0]

clst1_hit0[2:0] nxtch[2:0] clst2_pos[7:0]

clst1_hit1[2:0] clst2_ch[7:0] clst3_pos[7:0]

clst1_hit2[2:0] nxtch[2:0] clst4_pos[7:0]

clst1_hit3[2:0] clst3_ch2[7:0] OvlF

SPARE[12:0] nxtch[2:0] STOP bit

STOP bit STOP bit

CERN AUW Week

4 clusters central hit position

3 clusters geom. patterns

Even

t ID

16/11/2011

Functional Code & Simulation Test Bench:SVN Repository Structure

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SVN | ----------------------------------------------------------------------------------------------------------------- | | | ABCN HCC TRIPLICATION --------------------|------------------------------------------------------------------------------ | |trunk branches | | -------------------------------------------------------------------------------- USC development branch | | | rtl scripts test ------- --------- ----------------------------------------- | | | |L0_L1_Buffer simulation scripts matlab TEST_BENCH R3_DCL | L1_DCL ------------------------------------ReadOut | |Top_Logic Post Processing v3commandController | | |integration DCL ReadOut Test vector generation

CERN AUW WeekSlide Courtesy : Michelle Key-Charriere/RAL16/11/2011

Simulation test benches

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//`include "timescale.inc"`timescale 1ns/1psmodule ABCN13 (//bottom edge signals CLK_padP, CLK_padN, BC_padP, BC_padN, COM_LZERO_padP, COM_LZERO_padN, LONERTHREE_padP, LONERTHREE_padN, RST_padP, RST_padN, ID,//data from the detector DIN,//left edge signals XOFFL, XOFFLB, DATL, DATLB,//right edge signals XOFFR, XOFFRB, DATR, DATRB);

#SIM_OPTS = +define+logThruFIFODEPTH=4 +define+logLocalFIFODEPTH=5 +define+logCSRFIFODEPTH=3 +define+PACKETWIDTH=54 +define+PW=53 #customer didn't like this approach???#for vcs sim, no gui#VERILOG = vcs #for ncverilog sim, simvision#add +ncsimargs+-gui +gui_sync to COMMON_DEFINES if gui-driven simulation is desired#change +access+r to +access+w to COMMON_DEFINES if SEU test scripts has to be runVERILOG = ncverilogCOMMON_DEFINES = +define+TEST=test +define+TB=tb +access+rVLOG_OPS = +v2k +libext+.v VLOG_LIBS = -y ../rtl/ABCNmodules -y ../rtl/TBmodules -y ../../trunk/rtl/Pipeline_InReg -y ../rtl/Top_Logic -y ../../trunk/rtl/L1_DCL -y ../../trunk/rtl/R3_DCL -y ../../trunk/rtl/L0_L1 -y $IBM_PDK/ibm_cmos8rf/std_cell/relDM/verilog -y $IBM_PDK/ibm_cmos8rf/short_io/relDM/verilog -y ../../trunk/rtl/WatchDogTOP_MODULES = ../rtl/ABCNmodules/ABCN13.v ../../trunk/rtl/L0_L1/veri_globals_v2.v ../../trunk/rtl/L0_L1/pipecontrollerandL0ID.v ../../trunk/rtl/L0_L1/ROAddressSelect.v#GATE_LEVEL_MODULES = commandControl.vg readOut.vg readReg.vg#GATE_LEVEL_MODULES = ../rtl/synthesized_rtl/reg32.vgTEST_COMPONENTS = $VERILOG $VLOG_OPS $VLOG_LIBS $COMMON_DEFINES $TOP_MODULES $GATE_LEVEL_MODULES

#these are verilog simulation targets for development/experimental tests.#log files are produced but self-checking does not occur.#f(CLK)/f(BCCLK)=4TB1_DEV_TESTS = tb1test0 tb1test1 tb1RegTest tb1InputRegTest tb1PipeLineL1 tb1PipeLineR3

ABCN13.v Makefile (run simulation)

CERN AUW WeekTop Level and Makefile by Joel de Witt/UCSC16/11/2011

Cadence IC6 Simulation Environment

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Packets transmitted

Serial data logged to file for post processing

CERN AUW WeekSlide Courtesy : Michelle Key-Charriere/RAL16/11/2011

Matlab Post Processing Scripts• To check the accuracy of the data transmission, run the post processing script:

.\abcnasic\abcn\trunk\test\Matlab\PostProcessing\ReadOut\packet_analyser.m

>> packet_analyserAll of the loop 1 packets were recovered successfully.Percentage packet loss (%):0All of the loop 2 packets were recovered successfully.Percentage packet loss (%):0

• A bit level verification script for the Data Compression Logic (DCL) is available:.\abcnasic\abcn\trunk\test\Matlab\PostProcessing\DCL\DCL_verification.m

• This requires the matlab models L1_DCL.m and R3_DCL.m to be ‘bit true’ relative to the verilog implementations of the L1_DCL and R3_DCL blocks

More work is required to complete this verification tool.

13CERN AUW WeekSlide Courtesy : Michelle Key-Charriere/RAL16/11/2011

Chip 2 Packet-Type=1000 SEU-Flag=0 Register-Address=20 CSR=00000f01Chip 2 Packet-Type=1000 SEU-Flag=0 Register-Address=23 CSR=00000005Chip 2 Packet-Type=1000 SEU-Flag=0 Register-Address=22 CSR=00000002Chip 2 Packet-Type=0010 Trigger-ID= 0 Bunch-ID= 89 C1: add= 0 C2: add= 0 C3: add= 0 C4: add= 0 Ovfl=0Chip 2 Packet-Type=0011 Trigger-ID= 1 Bunch-ID=169 C1: add=254 C2: add= 0 C3: add= 0 C4: add= 0 Ovfl=0Chip 2 Packet-Type=0011 Trigger-ID= 2 Bunch-ID=181 C1: add=253 C2: add= 0 C3: add= 0 C4: add= 0 Ovfl=0Chip 2 Packet-Type=0011 Trigger-ID= 3 Bunch-ID=193 C1: add=252 C2: add= 0 C3: add= 0 C4: add= 0 Ovfl=0Chip 2 Packet-Type=0110 Trigger-ID= 1 Bunch-ID=169 C1: add=255 bits=000 C2: add=255 bits=000 C3: add=255 bits=000Chip 2 Packet-Type=0110 Trigger-ID= 2 Bunch-ID=181 C1: add=254 bits=000 C2: add=254 bits=000 C3: add=254 bits=000Chip 2 Packet-Type=0110 Trigger-ID= 5 Bunch-ID=217 C1: add=248 bits=000 C2: add=248 bits=000 C3: add=248 bits=000

Data Packet Analyzer

14

1 event empty2nd event 1 hit @ channel 255 3rd event 1 hit @ channel 2544th event 1 hit @ channel 2525th event 1 hit @ channel 248

R3

L1

Register Read

Read R3 Events 0 1 2 Read L1 Events 1 2 5Read R3 Event 3

Commands


Overall layout• Max width 7.5 mm• FE pads

• Only and no GND pads alongside• Span as wide as chip

• Data/Token• Chip-to-chip on air• Return pair underneath• 4 pairs of traces to MCC

• Clock, command, etc. on side– Bus traces underneath– Maximizing spacing between pairs,

no redunancy• Ground, power and chip ID on

bottom

• In the next pages, discuss the FE pads and pads to hybrid…

7.5 mm

FE bonds only (4 rows of 64)

Token and

Data (2 pairs)

Token and

Data (2 pairs)

BCO, L1, Com

, Clk, Reset (5 pairs)

Ground, Power, Chip ID

15CERN AUW WeekSlide Courtesy : Y. UNNO/KEK16/11/2011

Front End • Would like FE bond

pads to take full width of ASIC– Ground pads if needed

below FE connections• Ground pads would

have to bond to the side, use same pad shape as for BE

• Would like ~50x200 mm pads with 100 mm spacing between rows

200

mm

100

mm

Ground (if needed)

1100

mm

16CERN AUW WeekSlide Courtesy : A. Greenhall/Liverpool16/11/2011

“ABCN 130” SEU strategies

17

• Simple ideas and proposals

• Assumptions based on :

• Tentative to limit the triplications where strictly needed

• In criticality order

Criticality Method Example

Very critical triplication Critical Commands

Very critical ECC (Hamming)

Sequencers

Less Tricks FIFO controls

Low DICE Baseline every where else (?)


Dice Cell

18

S. BonaciniCERN

Double DFF with interleaved subblocks to separate redundant nodes(IBM standard cell type layout currently under development, Filipe Sousa)

4.5um

CERN AUW Week

The DICE cell may be an “easy” and power effective way to protect efficiently against SEU most part of the circuit

16/11/2011

IRRADIATIONS PLANS

• Front-End Prototype– Xray at low temperature– Low dose rate irradiation– “Beam” hit test vs. special ESD protection (P)

• RAM block SEU cross section (P)

• SEU standard Logic cross section (with and w/o TRM) (Going on)


ABCN Front-End Prototype

20

Jan Kaplon (Design)/Matt Noy (Measurements)Full set of measurements in backup slides

32 channelsLayout

10 channelsaccess


Noise performance

21

Markers show measured data points, lines are theoretical calculationsNo excess noise visible (Γ excess noise factor equal to 1).


Fast Track Trigger Optionin ABCN

22CERN AUW Week

Slides by Mitch Newcomer

16/11/2011

Trigger Primitives for Commissioning & Innovation

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Event Time

BC Syncronous L0

fixed Latency ~6-10µS

Challenge: Provide cluster information within a few BC of Event Time to seed first level trigger beam syncronous trigger with

high PT track enhanced triggers.

This kind of prompt trigger wasquite useful during commissioning of the TRT and for triggering the Inner Detector after the LHC accident.


IT-SC Fast Clustering Conceptual Block Diagram

24

Pipeline Data out

BC

• Store Data as two banks of 128 strips at BC time. One buffer register per bank.• Perform clustering algorithm in multiple steps @ 160Mhz using tightly restricted acceptance rules (next page) • Send Fixed Length Cluster information at a fixed #BC (4) after

the event to each dedicated LVDS output.• Due to low strip occupancy it is allowable to allocate several BC

each time a cluster is located.

256 Channel Analog

Front End Data

128

Stri

ps

128

Stri

ps

Bank 1 Data Bank 2 Data

Cluster ? Cluster ?

Pipeline

Separately enabled block

Data from Pipeline Input


CERN AUW Week 25

Proposed ABC130 Powering Options

ABC130

Analog 1.2V LDO

Digital Variable LDO

Analog Front End

Digital CoreRC filter

RC filterAn LDO In Dig LDO InVref Dig

(1)

(1)

(2)(2)

Power Loss Direct connection LDO DCDC

1.3 to .9 47% (Dig @ 1.3V) 30% 10-15%

1.2 to .9 37% 25% 10-15%

• 1 single power domain for hybrid

• No DC/DC on chip

16/11/2011

ABCN 130 Status• Progress on specs• Functional model and simulation test bench on going• Digital Synthesis has started• FloorPlan will start soon, incl RAM block developed by

CERN/PH/ME• SEU protections to be finalized• Issues on STD CELLS (Dice?)


HCC Status

27CERN AUW Week

• Specifications on going• Resources for code development are well defined for the

coming year• Resources for Floorplan/Final Layout have still to be defined

• Co-submission with ABCN 130 planned for End Q3-2012

16/11/2011

Backup Slides


Matching of the front end gains

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Mean 83 – 88mV/fCRMS 3 – 4mV/fC


Matching of discriminator offsets

30

Mean ~ 0mVRMS 8 – 13mV

Pk-Pk value < 80mVWith 5 bit DAC the step will be 1.5 – 2 mV (gain 85 mV/fC)


AC parameters of the input stage

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Intrinsic

transistor gain

Open loop gain

Gain Bandwi

dth Produc

t

Input impedance for frequencies

<1MHz

Input impedance at

25 MHz

Phase

margin

PSRR at low

frequencies

PSRR worst

case (at 25MHz

)

30 V/V 80 dB 2 GHz 30 Ω 330 Ω 90⁰ 78 dB 3 dB

Input transistor bias 80uA Cross talk signal is less than 3% for detector capacitance 1.5 pF to bulk + 2x

1.6 pF to neighbor


Parameters of the full chain

32

Detector capacitance range

Current/power consumption per channel

Pulse gain

Peaking

time

Dynamic range/ Linear range

Time walk

0 to 10pF 160 to 240uA190 to 290uW

85 mV/fC

22 ns 6.5/4.5fC 12.5 ns

Time walk defined for signals 1.2 and 10fC with discriminator threshold set to 1fC.


Command Decoder

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Command Packet

Class Header4 bits

TYP 3b +Parity

ChipID4 bits

Mode/Address8 bits

R/W

Data 32 bits

RESET 1010 000P to 101P

0000 $00 0 `5h000

MODE 1010 1100 aaaa $00 to $FF

0 `5h000

ACSR (Read)

1010 1111 aaaa $00 to $FF

0 `5hxxx

ACSR (Write)

1010 1111 aaaa $00 to $FF

1 `5h00 to `5h1FF

53 bitsCERN AUW Week16/11/2011

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ABCN 130 nm – Block Diagram

Event Address

Pipeline(SRAM)

L1 buffer (SRAM)

DCLL1

RR

Data Flow Control

BC

WA RA WA RA

At L0: RA=WA-L0Lat

WAgen RAgen

At BC : WA=WA+1

L0 latency (6.4us) L1 latency (up to 500us ?)

R3W

R3L0ID

R

L0ID

Event AddressL1

W

L1L0ID

R

256 256

DCLR3

256

25620

20

Local FiFO

Local FiFO

Readout

RR

Command DecoderCLK

L0-COM

R3-L1BC


ABCN Design Picture

Expected 264 bw x 256 al will translate into 5 times 64 bw (320 bits) and 2 times al (256 depth)Size : 5 x 150um in Y and 900um in X : 0.9mm x 0.75mm

(L0Buffer, pipeline)

Unit size : 450x 150 um 128 addresses in X and 64 word bits in Y

L0 pipeline :

320 bits word by 256 addresses

82Kbits memory

0.9 mm

0.75mm


ABCN Design Picture(L0ID Buffer)

L0ID Buffer :

320 bits word by 728 addresses 233Kb memory

2.7 mm

0.75mm

Expected 272 bw x 728 al will translate into 5 times 64 bw (320 bits) and 6 times al (728 depth)Size : 5 x 150um in Y and 2700um in X : 2.7mm x 0.75mm


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Hybrid readout through the GBT system

HCC 1 HCC 6 HCC 12

HCC 13 HCC 18 HCC 24

E-link 1 – 80-160MHz-clkE-link 2 – RXDATA : COME-link 3 – RXDATA : L0/L1

E-link 1 – TXDATA (80MHz)

E-link 6 – TXDATA (80MHz)

E-link 12 –TXDATA (80MHz)

E-link 1 – 80-160MHz-clkE-link 2 – RXDATA : COME-link 3 – RXDATA : L0/L1

E-link 13 – TXDATA



GBTX

E-link 4 – RXDATA : R3

E-link 4 – RXDATA : R3

1 pe

r hyb

rid


ABCN&HCC Status

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Transcript of ABCN&HCC Status