A Short Introduction to VHDL - epfl.wikispaces.com · 11/17/2005 3 Brief Intro zModeling IC with...

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A Short Introduction to VHDL

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Motivation for VHDL

Hardware Description Languages (HDLs) are unavoidable in the development of large Integrated Circuit (IC) designsTypical hw behaviour (concurrent execution of processes) is fundamentally different to sequential behaviour of high level (sw) languages like C and C++VHDL is a versatile and powerful HDL which is useful for modelling electronic systems at various levels of design abstraction HDL language

IEEE standardAlternative language: Verilog HDL

VHDL supports three steps of hw design:DocumentationSimulation of the behavior of the circuitSynthesis – automatic generation of net lists

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Brief Intro

Modeling IC with VHDLBasic idea - Component based design using abstract/refined implementations of the components.Entity – defines the interface with the exterior of a component

Interface = input and output portsCommunication among the entities assured by signals (equivalent to wires)Architecture – specifies the functionality of a component

Behavioral - A process with sequential operations; Control flow instructions - if, while, for loops, etcData Flow - concurrent statements Structural – entities + interconnections

Process – unit of concurrencyprocess instructions are sequentialStore values in process variables

Describe timing and delay: e.g. used in simulation; it supports both the concurrency and delay observed in digital electronic systems.

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Module Outline

Introduction

VHDL Design Example

VHDL Model Components

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VHDL

Acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description LanguageIEEE standard (IEEE 1076-1993) for describing digital hardware used by industry worldwide.Product of a US Government (DoD) request for a new means of describing digital hardware

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VHDL’s History

Very High Speed Integrated Circuit (VHSIC) Program

Launched in 1980Aggressive effort of US Government (DoD) to advance state of the art in VLSI technologyNeed for common descriptive language

Woods Hole WorkshopHeld in June 1981 in MassachusettsDiscussion on VHSIC goalsComprised of members of industry, government, and academia

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VHDL’s History (Cont.)

July 1983 - a team of Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDLInfluenced from ADAAugust 1985 – release of final version of the language under government contract: VHDL Version 7.2December 1987 - VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standardSeptember 1993 - VHDL was restandardized to clarify and enhance the language (IEEE Standard 1076-1993): handling and more consistent syntax VHDL has been accepted as a Draft International Standard by the IEC

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Reasons for Using VHDLIEEE standard used by industry worldwide

Allows for various design methodologies:Modelling from system level to gate level; delay of detail.

Mix descriptions: behavioural with gate level description.VHDL provides a mechanism for reusable design documentationFormal Specification of the algorithms that govern the behaviour of the digital circuitTesting & Validation using simulationFormal verification of correctness of a design: require mathematical statement of the required functions of the systemAutomatic synthesisPerformance prediction

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Module Outline

Introduction

VHDL Design Example


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Design Entity

Basic element for the VHDL model - design entity. It could represent a whole system, an IC, a Printed Circuit Board (PCB) or a logic gate.

A VHDL entity can be implemented at different abstraction levels - behavioral, dataflow, structural

The focus of VHDL is design for RTL (Register Transfer Level) synthesis: it means that logic is treated as if were combinational logic in between registers

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Entity Declaration

Specifies the interface with the external environment.Format:

Example:

ENTITY entity_name IS [GENERIC (generic list);][PORT (port list);]END [entity_name];

ENTITY entity_name IS [GENERIC (generic list);][PORT (port list);]END [entity_name];

or_gatea

cb

ENTITY or_gate IS PORT (a, b : IN BIT;

c : OUT BIT);END nor_gate;

ENTITY or_gate IS PORT (a, b : IN BIT;

c : OUT BIT);END nor_gate;

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Example - Single Bit Half Adder

SpecificationsInputs and outputs are each one bit.When enable is high, result gets LSB of x+y.When enable is high, carry gets MSB of x+y.Outputs are zero when enable input is low.

xy

enable

carry

resultHalf Adder

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Example - Single Bit Half Adder Entity Declaration

Describes the interface of the componentinput and output ports are declared

x

y

enable

carry

resultHalf

Adder

ENTITY half_adder IS

PORT( x, y, enable: IN BIT;carry, result: OUT BIT);

END half_adder;

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Example - Single Bit Half AdderBehavioural Specification

High level descriptionAbstract construct more readable modelSequential statements inside a processCloser to the way we are used to program - with control flowWill involve more effort in compilation for the synthesis

The model can then be simulated to verify correct functionality of the component.

ARCHITECTURE half_adder_a OF half_adder ISBEGIN

PROCESS (x, y, enable)BEGIN

IF enable = ‘1’ THENresult <= x XOR y;carry <= x AND y;

ELSEcarry <= ‘0’;result <= ‘0’;

END IF;END PROCESS;

END half_adder_a;

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Example - Single Bit Half AdderData Flow Specification

Use logic equations to develop a data flow descriptionConcurrent signal assignment statements.Again, the model can be simulated at this level to confirm the logic equations.Easy to map to logic gates

ARCHITECTURE half_adder_b OF half_adder ISBEGIN

carry <= enable AND (x AND y);

result <= enable AND (x XOR y);END half_adder_b;

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Example - Single Bit Half AdderStructural Specification

Structural description can be created from pre-defined componentsThese gates can be taken from a library of components.

xy

enablecarry

result

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Example - Single Bit Half AdderStructural Specification (Cont.)

ARCHITECTURE half_adder_c OF half_adder IS

COMPONENT and2PORT (in0, in1 : IN BIT;

out0 : OUT BIT);END COMPONENT;

COMPONENT and3PORT (in0, in1, in2 : IN BIT;


COMPONENT xor2PORT (in0, in1 : IN BIT;


FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a);FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);

-- description is continued on next slide

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Example - Single Bit Half AdderStructural Specification (Cont.)

-- continuing half_adder_c description

SIGNAL xor_res : BIT; -- internal signal-- Note that other signals are already declared in entity

BEGIN

A0 : and2 PORT MAP (enable, xor_res, result);A1 : and3 PORT MAP (x, y, enable, carry);X0 : xor2 PORT MAP (x, y, xor_res);

END half_adder_c;

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Module Outline

Introduction

VHDL Design Example

VHDL Model ComponentsMore Features of VHDLTiming ModelReactive BehaviorGenerate StatementsTestbench

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Lexical ElementsComments on a line

two dashes --

VHDL identifierletter ( “_” | letter | digit )*

Signal assignment: signal <= operandVariable assignment: var := operandInteger and floating point numbers:

0, 1, 98E-30.0, 1.0, 9.8E+4

Characters & Strings‘A’, “VHDL”

Bit constant values: ‘0’, ‘1’Bit vectors: B"00000000“, …

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Features of VHDL ModelPackages are used to provide a collection of common declaration, constants, and/or subprograms to entities and architectures.

Generics provide a method for parameterizing an entity – e.g. the no of bits of an input. They are passed through the entity construct.

Ports provide the mechanism for a device to communicate with its environment. A port declaration defines the names, types directions and possible default values for the signals in a component’s interface.

Configuration instruction - used to bind the component instances to a specific architecture of a design entity.

Bus is a group of signals or a particular method of communication.

Driver is a source for a signal - it provides values to be applied to the signal.

Attribute is a VHDL object’s additional information.

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Putting It All Together

Architecture Architecture Architecture

ConcurrentStatements

Sequential Statements

ConcurrentStatements

Package

Generics Ports

Process

Entity

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Fundamental unit for component behaviour description is the process.

Processes are packaged in architectures and may be defined explicitly (behavioural) or implicitly (data flow)

Primary communication mechanism is the signalProcess executions result in new values being assigned to signals Signals are accessible to other processesSimilarly, a signal may be accessed by a process in another architecture by connecting the signal to ports in the the entities associated with the two architecturesExample signal assignment statement :

Output <= My_id + 10;Output <= My_id + 10;

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Entity Declarations: example

enable

carryresult

x

y HalfAdder

ENTITY half_adder IS

GENERIC(prop_delay : TIME := 10 ns);

PORT( x, y, enable : IN BIT;carry, result : OUT BIT);

END half_adder;

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Entity DeclarationsPort Clause

PORT clause declares the interface signals of the object to the outside world

Three parts of the PORT clauseNameModeData typeSignal’s initial value (optional)

Example PORT clause:

Note port signals (i.e. ‘ports’) of the same mode and type or subtype may be declared on the same line

PORT (signal_name : mode data_type);PORT (signal_name : mode data_type);

PORT ( input : IN BIT_VECTOR(3 DOWNTO 0);ready, output : OUT BIT );

PORT ( input : IN BIT_VECTOR(3 DOWNTO 0);ready, output : OUT BIT );

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Entity DeclarationsPort Clause (cont.)

The port mode of the interface describes the direction in which data travels with respect to the component

The five available port modes are: In - data comes in this port and can only be readOut - data travels out this portBuffer - data may travel in either direction, but only one signal driver may be on at any one timeInout - data may travel in either direction with any number of active drivers allowed; requires a Bus Resolution FunctionLinkage - direction of data flow is unknown

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Signals VS Variables

Signals are declared inside the Architecture declarative part and can be used to communicate results across processesNote: The processes execute concurrently and may read/write to the same signal at the same time. This can result in unpredictable behavior during simulation

Variables are declared and used only inside processesOne process has no way to access the variables of another processVariables work in the same way as variables in the C language

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Entity DeclarationsGeneric Clause

Parameterization of an entity - similar to template in C++

Constants that are passed into the entity declaration.Reuse designGeneric clause syntax :

If optional default_value is missing in generic clause declaration, it must be present when component is to be used (i.e. instantiated)

Generic clause example :

The generic My_ID can be referenced by any architecture of the entity with this generic clauseThe default can be overridden at component instantiation

GENERIC (generic_name : type [:= default_value]);GENERIC (generic_name : type [:= default_value]);

GENERIC (My_ID : INTEGER := 37);GENERIC (My_ID : INTEGER := 37);

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Architecture BodiesDescribe the operation of the componentThere can be many different architecture for each entity, however for each instantiation of the entity one must be selectedConsist of two parts :

Declarative part -- includes necessary declarationse.g. type declarations, signal declarations, component declarations, subprogram declarations

Statement part -- includes statements that describe organization and/or functional operation of component

e.g. concurrent signal assignment statements, process statements, component instantiation statements

ARCHITECTURE half_adder_d OF half_adder ISSIGNAL xor_res : BIT; -- architecture declarative partBEGIN -- begins architecture statement part

carry <= enable AND (x AND y);result <= enable AND xor_res;xor_res <= x XOR y;

END half_adder_d;

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Packages and LibrariesUser defined constructs declared inside architectures and entities are not visible to other VHDL components

Scope of subprograms, user defined data types, constants, and signals is limited to the VHDL components in which they are declared

Packages and libraries provide the ability to reuse constructs in multiple entities and architectures

Items declared in packages can be used (i.e. included) in other VHDL componentsVHDL provides the package mechanism so that user-defined types, subprograms, constants, aliases, etc. can be defined once and reused in the description of multiple VHDL components.VHDL libraries are collections of packages, entities, and architectures. The use of libraries allows the organization of the design task into any logical partition the user chooses (e.g. component libraries, package libraries to house reusable functions and type declarations).

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A package contains a collection of user-defined declarations and descriptions that a designer makes available to other VHDL entities with a useclause. Packages consist of two parts

Package declaration -- contains declarations of objects defined in the packagePackage body -- contains necessary definitions for certain objects in package declaration

e.g. subprogram descriptionsExamples of VHDL items included in packages :

Basic declarationsTypes, subtypesConstantsSubprogramsUse clause

Signal declarationsAttribute declarationsComponent declarations

Packages

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PackagesDeclaration

An example of a package declaration :

Note some items only require declaration while others need further detail provided in subsequent package body

for type and subtype definitions, declaration is sufficientsubprograms require declarations and descriptions

PACKAGE my_stuff ISTYPE binary IS ( ON, OFF );CONSTANT PI : REAL := 3.14;CONSTANT My_ID : INTEGER;PROCEDURE add_bits3(SIGNAL a, b, en : IN BIT;

SIGNAL temp_result, temp_carry : OUT BIT);END my_stuff;

PACKAGE my_stuff ISTYPE binary IS ( ON, OFF );CONSTANT PI : REAL := 3.14;CONSTANT My_ID : INTEGER;PROCEDURE add_bits3(SIGNAL a, b, en : IN BIT;

SIGNAL temp_result, temp_carry : OUT BIT);END my_stuff;

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PackagesPackage Body

The package body includes the necessary functional descriptions needed for objects declared in the package declaration

e.g. subprogram descriptions, assignments to constants

PACKAGE BODY my_stuff ISCONSTANT My_ID : INTEGER := 2;

PROCEDURE add_bits3(SIGNAL a, b, en : IN BIT;SIGNAL temp_result, temp_carry : OUT BIT) IS

BEGIN -- this function can return a carrytemp_result <= (a XOR b) AND en;temp_carry <= a AND b AND en;

END add_bits3;END my_stuff;

PACKAGE BODY my_stuff ISCONSTANT My_ID : INTEGER := 2;

PROCEDURE add_bits3(SIGNAL a, b, en : IN BIT;SIGNAL temp_result, temp_carry : OUT BIT) IS

BEGIN -- this function can return a carrytemp_result <= (a XOR b) AND en;temp_carry <= a AND b AND en;

END add_bits3;END my_stuff;

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PackagesUse Clause

Packages are made visible to a VHDL description through the use of the USE clause.

This statement comes at the beginning of the entity or architecture file and makes the contents of a package available within that file.This normally implies that the compilation of the file

containing the package must occur prior to that of the top level design that uses the package

USE clause is analogous to the uses/include statement in Pascal/C.

The USE clause can select all or part of a particular package. In the first example above, only the binary data type and add_bits3 procedure are made visible. In the second example, the full contents of the package are made visible by use of the keyword ALL in the use clause

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PackagesUse Clause

Packages must be made visible before their contents can be used

The USE clause makes packages visible to entities, architectures, and other packages

-- use only the binary and add_bits3 declarationsUSE my_stuff.binary, my_stuff.add_bits3;

... ENTITY declaration...

... ARCHITECTURE declaration ...

-- use all of the declarations in package my_stuffUSE my_stuff.ALL;

... ENTITY declaration...

... ARCHITECTURE declaration ...

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LibrariesEfficient design calls for reuse of components when applicable and revision of library components when necessary. VHDL uses a library system to maintain designs for modification and shared use.

VHDL refers to a library by an assigned logical name.The current design unit is compiled into the Work library by default; Work is implicitly available to the user with no need to declare it. Similarly, the predefined library STD does not need to be declared before its packages can be accessed via use clauses. The STD library contains the VHDL predefined language environment, including the package STANDARD which contains a set of basic data types and functions and the package TEXTIOwhich contains some text handling procedures.

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Libraries

Analogous to directories of filesVHDL libraries contain analized (i.e. compiled) VHDL entities, architectures, and packages

Facilitate administration of configuration and revision control

E.g. libraries of previous designsLibraries accessed via an assigned logical name

Current design unit is compiled into the Work libraryBoth Work and STD libraries are always availableMany other libraries usually supplied by VHDL simulator vendor

E.g. proprietary libraries and IEEE standard libraries

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Module Outline

Introduction

VHDL Design Example

VHDL Model ComponentsMore Features of VHDLTiming ModelReactive BehaviorGenerate StatementsTestbench

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Timing Model Any signal assignment statement will incur a delay: understanding of how delay works in a process is key to designing with VHDL

When a signal assignment statement is executed, the signal maintains its original value until the time for the scheduled update to the new value.

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Delay Types

Inputdelay

Output

All VHDL signal assignment statements specify an amount of time that must elapse before the signal assumes its new value

The delay can be have one of the following types:Transport -- specifies propagation delay onlyInertial -- specifies propagation delay and minimum input pulse widthDelta -- the default if no delay time is explicitly specified

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Transport Delay

Transport delay is the simplest oneThe value of the output signal updates after the specified transport/propagation delay from the moment the input signal value changed.

No restrictions are specified on input pulse widths.

We can model an ideal device with infinite frequency response

Transport delay must be explicitly specifiedI.e. keyword “TRANSPORT” must be used

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Transport DelaySignal will assume its new value after specified delay

Inv: process(input) isbegin-- TRANSPORT delay exampleOutput <= TRANSPORT NOT Input AFTER 10 ns;End process Inv;

Inv: process(input) isbegin-- TRANSPORT delay exampleOutput <= TRANSPORT NOT Input AFTER 10 ns;End process Inv;

Input Output

0 5 10 15 20 25 30 35

Output

Input

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Inertial Delay

Real electronic circuits don’t have infinite frequency responsedevices have inertia (output delay) they do not respond to input pulses shorter than their output delayit is not appropriate to model them using transport delay.

Specified through INERTIAL keyword in the signal assignment statement

It may be left out because inertial delay is used by default in VHDL signal assignment statements which contain “after” clauses.

The REJECT construct is optional: if it is not used, the specified delay is then used as both the ‘inertia’ (i.e. minimum input pulse width requirement) and the propagation delay for the signal.

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Inertial Delay

Provides for specification propagation delay and input pulse width, i.e. ‘inertia’ of output:

Inertial delay is default and REJECT is optional :Output <= NOT Input AFTER 10 ns;-- Propagation delay and minimum pulse width are 10ns

Output <= NOT Input AFTER 10 ns;-- Propagation delay and minimum pulse width are 10ns

Output

0 5 10 15 20 25 30 35

OutputInput

target <= [REJECT time_expression] INERTIAL waveform;target <= [REJECT time_expression] INERTIAL waveform;

Input

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Inertial Delay (cont.)

Example of gate with ‘inertia’ smaller than propagation delay

e.g. Inverter with propagation delay of 10ns which suppresses pulses shorter than 5nsNote REJECT construct can only be used with the keyword INERTIAL

Output <= REJECT 5ns INERTIAL NOT Input AFTER 10ns;Output <= REJECT 5ns INERTIAL NOT Input AFTER 10ns;

Output

Input

0 5 10 15 20 25 30 35

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Default signal assignment propagation delay if no delay is explicitly specified

Delta is an “infinitesimal” VHDL time unitIn a delta cycle the VHDL simualtor

first evaluates all currently activated processesthen updates the (output) signals

Supports a model of concurrent VHDL process execution

Order in which processes are executed by simulator does not affect simulation output

Delta Delay

Output <= NOT Input;-- Output assumes new value in one delta cycle

Output <= NOT Input;-- Output assumes new value in one delta cycle

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Delta DelayAn Example without Delta Delay

Assume we update the output ports of a process immediately after the execution of the processBefore executing another active process

The behaviour of C is related to the execution order of active processes

1

IN: 1->0A

B

C

NAND gate evaluated first:IN: 1->0A: 0->1B: 1->0C: 0->0

NAND gate evaluated first:IN: 1->0A: 0->1B: 1->0C: 0->0

AND gate evaluated first:IN: 1->0A: 0->1C: 0->1B: 1->0C: 1->0 glitch

AND gate evaluated first:IN: 1->0A: 0->1C: 0->1B: 1->0C: 1->0 glitch

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Delta DelayAn Example with Delta Delay

The behaviour is always independent of the execution order of active processes

IN: 1->0

1

A

B

C

Using delta delay schedulingUsing delta delay schedulingTime Delta Event0 ns 1 IN: 1->0

eval INVERTER2 A: 0->1

eval NAND, AND3 B: 1->0

C: 0->1eval AND

4 C: 1->01 ns

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Timing Model

VHDL uses the following simulation cycle to model the stimulus and response nature of digital hardware

Start SimulationStart Simulation

Update SignalsUpdate Signals Evaluate Active ProcessesEvaluate Active Processes

End SimulationEnd Simulation

Delay

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Timing Model • At the start of a simulation, signals with default values are assigned

those values. • In the first execution of the simulation cycle, all processes are

executed until they reach their first wait statement. These process executions will include signal assignment statements that assign new signal values after prescribed delays.

• After all the processes are suspended at their respective wait statements, the simulator will advance simulation time just enough so that the first pending signal assignments can be made (e.g. 1 ns, 3 ns, 1 delta cycle).

• After the relevant signals assume their new values, all processes examine their wait conditions to determine if they can proceed. Processes that can proceed will then execute concurrently again until they all reach their respective subsequent wait conditions.

• This cycle continues until the simulation termination conditions are met or until all processes are suspended indefinitely because no new signal assignments are scheduled to resume any waiting processes.

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The Wait Statement

The wait statement causes the suspension of a process statement or a procedure

wait [sensitivity_clause] [condition_clause] [timeout_clause ] ;sensitivity_clause ::= ON signal_name { , signal_name }WAIT ON clock;

condition_clause ::= UNTIL boolean_expressionWAIT UNTIL clock = ‘1’;

timeout_clause ::= FOR time_expressionWAIT FOR 150 ns;

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The Wait StatementThe condition_clause: an expression which must evaluate to TRUE in order for the process to proceed past the wait statement. If no condition_clause is given, a TRUE value is implied when there is an event on a signal in the sensitivity_clause.The timeout_clause: specifies the maximum amount of time the process will remain suspended at this wait statement. If no timeout_clause is given, STD.STANDARD.TIME'HIGH STD.STANDARD.NOW (effectively until the end of simulation time)is assumed.

Wait statements assist the modeling process by synchronizing concurrently executing processes, implementing delay conditions into a behavioral model, or establishing event communications between processes. Sometimes, wait statements are used to sequence process execution relative to the simulation cycle.

Processes in VHDL are actually code loops. every process must have at least one wait statement or a sensitivity list

Sensitivity is actually an implied wait statement.

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“wait until” and “wait for”

What do these do?

Summation: PROCESSBEGINSum <= A XOR B XOR Cin;WAIT UNTIL A = ‘1’;

END PROCESS Summation;

Summation: PROCESSBEGINSum <= A XOR B XOR Cin;WAIT UNTIL A = ‘1’;


The first process above executes once at the beginning of the VHDL simulation and then suspends until the input A is assigned a value of ‘1’ before it executes again.

This cycle continues in that the process executes every time A is assigned a value of ‘1’.

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“wait until” and “wait for”

What do these do?

Summation: PROCESSBEGINSum <= A XOR B XOR Cin;

WAIT FOR 100 ns;END PROCESS Summation;


WAIT FOR 100 ns;END PROCESS Summation;

The second process also executes once at the beginning of the VHDL simulation

It then waits for 100ns of simulation time and executes again.

This cycle continues with the process executing every 100ns of simulation time.

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Equivalent Processes

“Sensitivity List” vs “wait on”

Summation:PROCESS( A, B, Cin)BEGINSum <= A XOR B XOR Cin;


Summation:PROCESS( A, B, Cin)BEGINSum <= A XOR B XOR Cin;



WAIT ON A, B, Cin;END PROCESS Summation;


WAIT ON A, B, Cin;END PROCESS Summation;

=

If you put a sensitivity list in a process, you can’t have a wait statement!

If you put a wait statement in a process, you can’t have a sensitivity list!

VHDL Standard prohibition

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Clock Synchronization

To synchronize a process to a global clock’s signalRising edge we use:

WAIT UNTIL CLK’EVENT AND CLK=‘1’Falling edge

WAIT UNTIL CLK’EVENT AND CLK=‘0’

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Generate StatementStructural descriptions of large, but highly regular

structures can be tedious.

VHDL provides the GENERATE statement to create well-patterned structures easily

Some structures in digital hardware are repetitive in nature (e.g. RAMs, adders): some common examples include the instantiation and connection of multiple identical components such as half adders to make up a full adder, or exclusive or gates to create a parity tree.

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Generate Statement

A VHDL GENERATE statement can be used to include as many concurrent VHDL statements (e.g. component instantiation statements) as needed to describe a regular structure easily

Any VHDL concurrent statement may be included in a GENERATE statement, including another GENERATE statement

Specifically, component instantiations may be made within GENERATE bodies

VHDL provides two different schemes of the GENERATE statement, the FOR-scheme and the IF-scheme.

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Generate StatementFOR-Scheme

The FOR-scheme is reminiscent of a FOR loop used for sequence control in many programming languages.The FOR-scheme generates the included concurrent statements the assigned number of times. In the FOR-scheme, all of generated concurrent statements must be the same: all objects created are similar .The loop variable is created in the GENERATE statement and is undefined outside that statement (i.e. it is not a variable or signal visible elsewhere in the architecture).The GENERATE parameter must be discrete. Loop cannot be terminated early

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Generate StatementFOR-Scheme

The syntax for the FOR-scheme GENERATE statement.

The loop variable in this case is N.

The range can be any valid discrete range.

After the GENERATE keyword, the concurrent statements to be generated are stated.

The GENERATE statement is closed with END GENERATE

name : FOR N IN 1 TO 8 GENERATE concurrent-statements

END GENERATE name;

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FOR-Scheme Example-- this uses the and_gate component from beforeARCHITECTURE test_generate OF test_entity IS

SIGNAL S1, S2, S3: BIT_VECTOR(7 DOWNTO 0);BEGIN

G1 : FOR N IN 7 DOWNTO 0 GENERATEand_array : and_gateGENERIC MAP (2 ns, 3 ns)PORT MAP (S1(N), S2(N), S3(N));

END GENERATE G1;END test_generate;

S2(7:0)S1(7:0)

S3(7:0)

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FOR-Scheme Example

The lust slide shows an example of the FOR-scheme.

The code generates an array of AND gates. In this case, the GENERATE statement has been named G1 and instantiates an array of 8 and_gate components. The PORT MAP statement maps the interfaces of each of the 8 gates to specific elements of the S1, S2, and S3 vectors by using the FOR loop variable as an index.

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Generate StatementIF-Scheme

The second form of the GENERATE statement: IF-scheme.

This scheme allows for conditional generation of concurrent statements.

One difference between this scheme and the FOR-scheme:all the concurrent statements generated do not have to be the same.

While this IF statement may seem reminiscent to the IF-THEN-ELSE constructs in programming languages, note that the GENERATE IF-scheme does not provide ELSE or ELSIF clauses.

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Generate StatementIF-Scheme

Syntax of the IF-scheme GENERATE statement.The boolean expression of the IF statement can

be any valid boolean expression. Allows for conditional creation of components

Cannot use ELSE or ELSIF clauses with theIF-scheme

name : IF (boolean expression) GENERATE concurrent-statements

END GENERATE name;

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ARCHITECTURE test_generate OF test_entitySIGNAL S1, S2, S3: BIT_VECTOR(7 DOWNTO 0);

BEGING1 : FOR N IN 7 DOWNTO 0 GENERATE

G2 : IF (N = 7) GENERATEor1 : or_gateGENERIC MAP (3 ns, 3 ns)PORT MAP (S1(N), S2(N), S3(N));

END GENERATE G2;

G3 : IF (N < 7) GENERATEand_array : and_gateGENERIC MAP (2 ns, 3 ns)PORT MAP (S1(N), S2(N), S3(N));

END GENERATE G3;

END GENERATE G1;END test_generate;

IF-Scheme Examples

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IF-Scheme Examples

The example here uses the IF-scheme GENERATE statement to make a modification to the and_gate array such that the seventh gate of the array will be an or_gate.

Another example use of the IF-scheme GENERATE is in the conditional execution of timing checks.

Timing checks can be incorporated inside a GENERATE IF-scheme. For example, the following statement can be used:Check_time : IF TimingChecksOn GENERATEThis allows the boolean variable TimingChecksOn to enable timing checks by generating the appropriate concurrent VHDL statements in the description.This parameter can be set in a package or passed as a generic

and can improve simulation speed by shutting off this computational section.

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Testbench

In order to simulate a VHDL model to see if it behaves accordingly to the specification we write a tester unit (a testbench) which feeds our model (called Unit Under Test – UUT – or DUT – Design Under Test) with stimuli.The testbench should be meaningful:

The test vectors should resemble the real inputs of the UUT when operating in the final environmentAll the functionalities of the UUT should be explored

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Errors That I Perform with VHDL in ModelSim

Forgetting to save the edited file before compiling itCompile error:

Wait statements are not allowed in a process with a sensitivity list.

It seems that the port names in the entity definition and in theentity declaration (with the component keyword followed by port map) have to be the same

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Module Outline

Introduction

VHDL Design Example


Basic VHDL Constructs

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Data Types

The concept of type is very important when describing data in a VHDL model

The type of a data object defines the set of values that an object can assume as well as the set of operationthat can be performed .

VHDL is a strongly typed language: every object may only assume values of its nominated type

The aim of strong typing is to allow detection of errorsat an early stage of the design process.

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Data Types

The three defined data types in VHDL areScalar types: are atomic units of information: a scalar objects can hold only a single, indivisible value at time.Composite types: are arrays and/or records; each object of this data type can hold more than one valueAccess types: are akin to pointers in other programming languages

In addition, subtypes and predefined types will also be introduced

Note that VHDL 1076-1987 defined a fourth data type, file, but files were reclassified as objects in VHDL 1076-1993.

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Data Types

All declarations of VHDL ports, signals, and variables must specify their corresponding type or subtype

Types

Access

Scalar

Array Record

Real Enumerated PhysicalInteger

Composite

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VHDL Data TypesScalar Types: Integer

Integer Assignments within a simulator-specific rangeMinimum range for any implementation as defined by standard: - 2,147,483,647 to 2,147,483,647Example assignments to a variable of type integer :

ARCHITECTURE test_int OF test ISBEGIN

PROCESS (X)VARIABLE a: INTEGER;

BEGINa := 1; -- OKa := -1; -- OKa := 1.0; -- illegal

END PROCESS;END test_int;

ARCHITECTURE test_int OF test ISBEGIN

PROCESS (X)VARIABLE a: INTEGER;

BEGINa := 1; -- OKa := -1; -- OKa := 1.0; -- illegal

END PROCESS;END test_int;

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ARCHITECTURE test_real OF test ISBEGIN

PROCESS (X)VARIABLE a: REAL;

BEGINa := 1.3; -- OKa := -7.5; -- OKa := 1; -- illegala := 1.7E13; -- OKa := 5.3 ns; -- illegal(->ns)

END PROCESS;END test_real;

ARCHITECTURE test_real OF test ISBEGIN

PROCESS (X)VARIABLE a: REAL;

BEGINa := 1.3; -- OKa := -7.5; -- OKa := 1; -- illegala := 1.7E13; -- OKa := 5.3 ns; -- illegal(->ns)

END PROCESS;END test_real;

VHDL Data TypesScalar Types: Real

Real Minimum range for any implementation is defined by standard: -1.0E38 to 1.0E38Example: assignments to a variable of type real :

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VHDL Data TypesScalar Types : Enumerated

EnumeratedThis data type allows a user to specify the list of legal values that a variable or signal of the defined type may be assignedUser defined: the user specifies list of possible valuesex: type colour is (red, green, blue);As an example, this data type is useful for defining the various states of a FSM with descriptive names. Predefined enumerated :

type bit is ( ‘0’ , ’1’ );type boolean is (false, true);type character is …type severity level is …

The designer first declares the members of the enumerated type.

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TYPE binary IS ( ON, OFF ); --where?... some statements ...ARCHITECTURE test_enum OF test ISBEGIN

PROCESS (X)VARIABLE a: binary;

BEGINa := ON; -- OK... more statements ...a := OFF; -- OK... more statements ...

END PROCESS;END test_enum;

TYPE binary IS ( ON, OFF ); --where?... some statements ...ARCHITECTURE test_enum OF test ISBEGIN

PROCESS (X)VARIABLE a: binary;

BEGINa := ON; -- OK... more statements ...a := OFF; -- OK... more statements ...

END PROCESS;END test_enum;

VHDL Data TypesScalar Types (Cont.)

Example: declaration and usage of enumerated data type :

Note : VHDL is not case sensitive.

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Physical Data TypesUsed for values which have associated unitsRange and name must be specified and then the unitExample of physical type declaration :

Time is the only physical type predefined in VHDL standardThe line after the Units line states the base unit of the type

TYPE resistance IS RANGE 0 TO 10000000-- no “;” between TYPE and UNIT statementUNITSohm; -- ohm, unit of the typeKohm = 1000 ohm; -- i.e. 1 KΩMohm = 1000 kohm; -- i.e. 1 MΩ END UNITS;

TYPE resistance IS RANGE 0 TO 10000000-- no “;” between TYPE and UNIT statementUNITSohm; -- ohm, unit of the typeKohm = 1000 ohm; -- i.e. 1 KΩMohm = 1000 kohm; -- i.e. 1 MΩ END UNITS;

VHDL Data TypesScalar Types (Cont.)

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VHDL Data TypesComposite Types

Array Used to group elements of the same type ( including arrays ) into a single VHDL objectRange may be unconstrained in declaration

Range would then be constrained when array is usedThe Array is declared in a TYPE statementMultiple dimensional array, ex:

Predefined array types:type string is array (positive range <> ) of charactertype bit-vector is array ( natural range <> ) of bit;

type twoDtype is array ( 0 to 4, 0 to 40 ) of real;type twoDtype is array ( 0 to 4, 0 to 40 ) of real;

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TYPE data_bus IS ARRAY(0 TO 31) OF BIT;TYPE data_bus IS ARRAY(0 TO 31) OF BIT;

VARIABLE X : data_bus;VARIABLE Y : BIT;...Y := X(12); -- Y gets value of element at index 12

-- the thirteen element from left

VARIABLE X : data_bus;VARIABLE Y : BIT;...Y := X(12); -- Y gets value of element at index 12

-- the thirteen element from left

0 310 1

...element indices...

...array values...

VHDL Data TypesComposite Types

Example declaration for one-dimensional array : vector of 32 bits

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Example one-dimensional array using DOWNTO :

DOWNTO keyword must be used if leftmost index is greater than rightmost index

e.g. ‘Big-Endian’ bit ordering

TYPE reg_type IS ARRAY(15 DOWNTO 0) OF BIT;TYPE reg_type IS ARRAY(15 DOWNTO 0) OF BIT;

VARIABLE X : reg_type;VARIABLE Y : BIT;

Y := X(4); -- Y gets value of element at index 4

VARIABLE X : reg_type;VARIABLE Y : BIT;

Y := X(4); -- Y gets value of element at index 4

15 00 1

...element indices...

...array values...

VHDL Data TypesComposite Types (Cont.)

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VHDL Data TypesComposite Types : Records

Records Used to group elements of possibly different types into a single VHDL objectElements are indexed via field namesA record element may be of any data type, including another record.A TYPE declaration is used to define a record. The types of a record's elements must be defined before the record is definedThere is no semi-colon after the word RECORD. The RECORD and END RECORD keywords bracket the field names. After the RECORD keyword, the record's field names are assigned and their data types is specified

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TYPE binary IS ( ON, OFF );TYPE switch_info IS

RECORDstatus : BINARY;IDnumber : INTEGER;

END RECORD;...VARIABLE switch : switch_info;switch.status := ON; -- status of the switchswitch.IDnumber := 30; -- e.g. number of the switch

TYPE binary IS ( ON, OFF );TYPE switch_info IS

RECORDstatus : BINARY;IDnumber : INTEGER;

END RECORD;...VARIABLE switch : switch_info;switch.status := ON; -- status of the switchswitch.IDnumber := 30; -- e.g. number of the switch

VHDL Data TypesComposite Types: Records

Examples of record declaration and usage : a record type, switch_info, is declared. This example makes use of the binary enumerated type declared previously. Note that values are assigned to record elements by use of the field names.

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VHDL Data TypesAccess Type

AccessAnalogous to pointers in other languages

Allows for dynamic allocation and deallocation of storage space to the object

Useful for implementing queues, fifos buffer , etc. , abstract data structures where the size of of the structure may not be known at the compile time

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SubtypeAllows for user defined constraints on a data type

e.g. a subtype based on an unconstrained VHDL typeconstraints take the form of range constraints or index constraints

A subtype may include entire range of base typeAssignments that are out of the subtype range are illegal

Range violation detected at run time rather than compile time because only base type is checked at compile time

Subtype declaration syntax :

Subtype example :

SUBTYPE name IS base_type RANGE <user range>;SUBTYPE name IS base_type RANGE <user range>;

VHDL Data TypesSubtypes

SUBTYPE first_ten IS INTEGER RANGE 0 TO 9;SUBTYPE first_ten IS INTEGER RANGE 0 TO 9;

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VHDL Data TypesSummary

All declarations of VHDL ports, signals, and variables must include their associated type or subtype Three forms of VHDL data types are :

Access -- pointers for dynamic storage allocationScalar -- includes Integer, Real, Enumerated, and PhysicalComposite -- includes Array, and Record

A set of built-in data types are defined in VHDL standard

User can also define own data types and subtypes

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VHDL Objects

Object in a VHDL model: named item with a value of a specified typeThere are four types of objects in VHDL (1076-1993)

ConstantsVariablesSignalsFiles (not discussed)

Declaration and use of constants, variables (and files) are like their use in other programming languages

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VHDL ObjectsThe scope of an object is as follows :

Objects declared in a package are available to all VHDL descriptions that use that packageObjects declared in an entity are available to all architecturesassociated with that entityObjects declared in an architecture are available to all statements in that architectureObjects declared in a process are available only within that process

Simple scoping rules determine where object declarations can be used.

This allows the reuse of identifiers in separate entities withinthe same model without risk of inadvertent errors.

For example, a signal named data could be declared within the architecture body of one component and used to interconnect its underlying subcomponents. The identifier data may also be used again in a different architecture body contained within the same model

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VHDL ObjectsConstants

Constant: Name assigned to a specific value of a type.VHDL constants are objects whose values can not be changed after they are created.Allow for easy update and readabilityDeclaration of constant may omit value so that the value assignment may be deferred (deferred constants) (e.g.: in a package body)

Facilitates reconfigurationDeclaration syntax :CONSTANT constant_name:type_name[:=value/expression];

Declaration examples :

CONSTANT PI : REAL := 3.14;CONSTANT SPEED : INTEGER;CONSTANT N : INTEGER := 8*SPEED;

CONSTANT PI : REAL := 3.14;CONSTANT SPEED : INTEGER;CONSTANT N : INTEGER := 8*SPEED;

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VHDL ObjectsVariables

Provide convenient mechanism for local storage E.g. loop counters, intermediate values

Scope is process in which they are declaredVHDL ‘93 provides for global variables, shared variables ( discussion deferred )

All variable assignments take place immediatelyNo delta or user specified delay is incurred (as in the case of signals). This feature allows the sequential execution of statements within VHDL processes where variables are used as placeholders for temporary data, loop counters, etc.

Declaration syntax:VARIABLE variable_name : type_name [:= value];Assignment syntax[label:] name := expression ;

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VHDL ObjectsVariables

The initialisation expression in optional: the default initial value assumed by the variable when it is created depends on the type.

For scalar types: the default initial value is the leftmost value of the type ( for integers is the smallest representable integer).

Declaration examples :

VARIABLE opcode : BIT_VECTOR(3 DOWNTO 0) := "0000";VARIABLE freq : INTEGER;

VARIABLE opcode : BIT_VECTOR(3 DOWNTO 0) := "0000";VARIABLE freq : INTEGER;

VARIABLE start : time := 0 ns;VARIABLE finish : time := 0 ns;-- equivalent toVARIABLE start, finish : time := 0 ns;

VARIABLE start : time := 0 ns;VARIABLE finish : time := 0 ns;-- equivalent toVARIABLE start, finish : time := 0 ns;

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VHDL ObjectsSignals

Used for communication between VHDL components: signals are used to pass information directly between VHDL processes and entities. Real, physical signals in system often mapped to VHDL signalsALL VHDL signal assignments require either delta cycle or user-specified delay before new value is assumed: a signal may have aseries of of future values with their respective timestamps pending in the signal’s waveform.The need to maintain a waveform results in a VHDL signal requiring more simulator resources than a VHDL variableDeclaration syntax :

SIGNAL signal_name : type_name [:= value]Declaration and assignment examples :

SIGNAL brdy : BIT;brdy <= ‘0’ AFTER 5ns, ‘1’ AFTER 10ns;

SIGNAL brdy : BIT;brdy <= ‘0’ AFTER 5ns, ‘1’ AFTER 10ns;

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Signals and Variables

This example highlights the difference between signals and variables

ARCHITECTURE test1 OF mux ISSIGNAL x : BIT := '1';SIGNAL y : BIT := '0';

BEGINPROCESS (in_sig, x, y)BEGINx <= in_sig XOR y;y <= in_sig XOR x;

END PROCESS;END test1;


BEGINPROCESS (in_sig, x, y)BEGINx <= in_sig XOR y;y <= in_sig XOR x;


ARCHITECTURE test2 OF mux IS SIGNAL y : BIT := '0';

BEGINPROCESS (in_sig, y)VARIABLE x : BIT := '1';

BEGINx := in_sig XOR y;y <= in_sig XOR x;



BEGINPROCESS (in_sig, y)VARIABLE x : BIT := '1';

BEGINx := in_sig XOR y;y <= in_sig XOR x;


Assuming a 1 to 0 transition on in_sig, what are the resulting values for y in the both cases?

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Signals and Variables(2)Signal assignments require that a delay be incurred before the signals assume their new values: at least a delta delay


BEGINPROCESS (in_sig, x, y) -- in_sig 1->0BEGINx <= in_sig XOR y; -- in_sig=0, y=0, x=1 actually

-- x will be 0 after the next delta cycley <= in_sig XOR x; -- in_sig=0, x=1, y=0

-- y will be 1 ...END PROCESS;

END test1;


BEGINPROCESS (in_sig, x, y) -- in_sig 1->0BEGINx <= in_sig XOR y; -- in_sig=0, y=0, x=1 actually

-- x will be 0 after the next delta cycley <= in_sig XOR x; -- in_sig=0, x=1, y=0

-- y will be 1 ...END PROCESS;

END test1;

The example leads to x and y swapping values in delta time while in_sig has a value of ‘0’

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Signals and Variables

This example highlights the difference between signals and variables


BEGINPROCESS (in_sig, y) -- in_sig 1->0VARIABLE x : BIT := '1';

BEGINx := in_sig XOR y; -- in_sig=0, y=0, x=0 y <= in_sig XOR x; -- in_sig=0, x=0, y=0 actually

-- y=0 the next delta cycleEND PROCESS;

END test2;


BEGINPROCESS (in_sig, y) -- in_sig 1->0VARIABLE x : BIT := '1';

BEGINx := in_sig XOR y; -- in_sig=0, y=0, x=0 y <= in_sig XOR x; -- in_sig=0, x=0, y=0 actually

-- y=0 the next delta cycleEND PROCESS;

END test2;

This example does not perform the swapping

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VHDL ObjectsSignals vs Variables

A key difference between variables and signals is the assignment delay

ARCHITECTURE sig_ex OF test ISPROCESS (a, b, c, out_1)BEGINout_1 <= a NAND b;out_2 <= out_1 XOR c;

END PROCESS;END sig_ex;

ARCHITECTURE sig_ex OF test ISPROCESS (a, b, c, out_1)BEGINout_1 <= a NAND b;out_2 <= out_1 XOR c;

END PROCESS;END sig_ex;

Time a b c out_1 out_2

0 0 1 1 1 01 1 1 1 1 0

1+d 1 1 1 0 01+2d 1 1 1 0 1

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Time a b c out_3 out_4

0 0 1 1 1 01 1 1 1 0 0

1+d 1 1 1 0 1

VHDL ObjectsSignals vs Variables (Cont.)

ARCHITECTURE var_ex OF test ISBEGIN

PROCESS (a, b, c)VARIABLE out_3 : BIT;BEGINout_3 := a NAND b;out_4 <= out_3 XOR c;

END PROCESS;END var_ex;

ARCHITECTURE var_ex OF test ISBEGIN

PROCESS (a, b, c)VARIABLE out_3 : BIT;BEGINout_3 := a NAND b;out_4 <= out_3 XOR c;

END PROCESS;END var_ex;

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VHDL ObjectsSignals vs Variables (Cont.)

The first example requires 2 delta cycles and two process executions to arrive at its quiescent state following a change to aI the second variables are used to achieve the same functionality as in the first one.

out_3 is visible only inside the processthe order in which the statements appear within the process is important because the two statements are executed sequentially

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VHDL ObjectsFiles

Files provide a way for a VHDL design to communicate with the host environmentFile declarations make a file available for use to a designFiles can be opened for reading and writing

In VHDL87, files are opened and closed when their associated objects come into and out of scopeIn VHDL93 explicit FILE_OPEN() and FILE_CLOSE()procedures were added

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VHDL ObjectsFiles

Files may be opened in read or write modeOnce a file is opened, its contents may only be accessed sequentially. A detailed description of the use of file objects is beyond this moduleThe package STANDARD defines basic file I/O routines for VHDL typesThe package TEXTIO defines more powerful routines handling I/O of text files

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Operators(overview)Shift Operator

There are three basic forms of shift: Shift Logical Left (SLL), Shift Logical Right (SLR), and Shift Arithmetic Right (SAR).In addition, some Shift instructions will store shifted bits in the Carry or Overflow bits, to be used in conjunction with other instructions such as conditional branches or rotates.The "Logical" in "Shift Logical Left" and "Shift Logical Right" refers to the fact that the sign bit of the number is ignored --the number is considered to be a sequence of bits that is eitheran unsigned quantity or a non-numeric quantity such as a graphic. When a number is shifted in this manner, the sign bit is not preserved. Logical shifts always bring in '0's in the bitpositions being "shifted in".The "Arithmetic" in "Shift Arithmetic Right" refers to the fact that the sign-bit is replicated as the number is shifted, thereby preserving the sign of the number. This is referred to as "sign extension", and is useful when dividing signed numbers by powers of 2.

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OperatorsOperators can be chained to form complex expressions, e.g. :

Can use parentheses for readability and to control the association of operators and operands

The list of predefined operators in VHDL :Defined precedence levels in decreasing order :

Miscellaneous operators -- **, abs, notMultiplication operators -- *, /, mod, remSign operator -- +, -Addition operators -- +, -, &Shift operators -- sll, srl, sla, sra, rol, rorRelational operators -- =, /=, <, <=, >, >=Logical operators -- AND, OR, NAND, NOR, XOR, XNOR

res <= a AND NOT(B) OR NOT(a) AND b;res <= a AND NOT(B) OR NOT(a) AND b;

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OperatorsThe logical and relational operators are similar to those in other languages. The concatenation operator ( ‘&’ ) will be discussed in the next slide: it joins two vectors together. Both vectors must be of the same type. The example given in the next slide performs a logical shift left for a four bit array. The mod operator returns the modulus of the division and the rem operator returns the remainder.For the exponentiation operator ** from the package STD, the exponent must be an integer; no real exponents are allowed. Negative exponents are allowed only with real numbers.

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OperatorsExamples

The concatenation operator &VARIABLE shifted, shiftin : BIT_VECTOR(0 TO 3);...shifted := shiftin(1 TO 3) & '0';

VARIABLE shifted, shiftin : BIT_VECTOR(0 TO 3);...shifted := shiftin(1 TO 3) & '0';

1

1 2 3

The exponentiation operator **.

SHIFTIN

SHIFTED

x := 5**5 -- 5^5, OKy := 0.5**3 -- 0.5^3, OKx := 4**0.5 -- 4^0.5, Illegaly := 0.5**(-2) -- 0.5^(-2), OK

x := 5**5 -- 5^5, OKy := 0.5**3 -- 0.5^3, OKx := 4**0.5 -- 4^0.5, Illegaly := 0.5**(-2) -- 0.5^(-2), OK

0

0 0 1

0 0 1 0

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Simulation Cycle RevisitedSequential vs Concurrent Statements

VHDL is inherently a concurrent languageAll VHDL processes execute concurrentlyConcurrent signal assignment statements are actually one-line processes

VHDL statements execute sequentially within a process

Concurrent processes with sequential execution within a process offers maximum flexibility

Supports various levels of abstraction

Supports modelling of concurrent and sequential events as observed in real systems

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Concurrent StatementsBasic granularity of concurrency is the processMechanism for achieving concurrency :

Processes communicate with each other via signalsSignal assignments require delay before new value is assumedSimulation time advances when all active processes completeEffect is concurrent processing

I.e. order in which processes are actually executed by simulator does not affect behaviour

Concurrent VHDL statements include :Block, Process, Signal assignment, Procedure call, Component instantiation

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Sequential StatementsStatements in a VHDL process are executed sequentially. A process may also include a sensitivity list which is declared

immediately after the PROCESS word. The process executes when there is a transition on any of the specified signals. Alternatively, a process would include at least one wait statement

to control when and where a process may suspend so that signals with pending signal assignments may assume their new values. Actually, a sensitivity list is equivalent to a wait statement at the bottom of a process which suspends execution until there is a transition on one of the signals on the sensitivity list.

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Sequential Statements

Statements inside a process execute sequentially

ARCHITECTURE sequential OF test_mux ISBEGIN

select_proc : PROCESS (x,y)BEGINIF (select_sig = '0') THEN

z <= x;ELSIF (select_sig = '1') THEN

z <= y;ELSE

z <= "XXXX";END IF;END PROCESS select_proc;

END sequential;

ARCHITECTURE sequential OF test_mux ISBEGIN

select_proc : PROCESS (x,y)BEGINIF (select_sig = '0') THEN

z <= x;ELSIF (select_sig = '1') THEN

z <= y;ELSE

z <= "XXXX";END IF;END PROCESS select_proc;

END sequential;

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Sequential StatementsHow!!!! the data may be manipulated within processesSequential Statement are executed in sequenceModify the state of objects and control the flow of execution of models.

Variable assignmentIf statement

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Variable Assignment

A variable is given a new value using an assignment statement

variable_assignment_statement <= [label:](name|aggregate):= expression

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IF Statement: Syntax Rule

if_statement <=[if_label : ]if boolean_expression then

{ sequential_statement }{ elsif boolean_expression then

{sequential_statement }}[else

{ sequential_statement }]

end if [if_label];

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IF Statement: Example

if mode=immediate thenoperand:=immed_operand;

elsif opcode=load or opcode=add or opcode=subtract thenoperand:=memory_operand;

elseoperand:=address_operand;

end if;

if mode=immediate thenoperand:=immed_operand;

elsif opcode=load or opcode=add or opcode=subtract thenoperand:=memory_operand;

elseoperand:=address_operand;

end if;

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CASE Statement: Syntax Rulecase_statement <=[case_label : ]case expression is

( when choices =>{sequential_statement })

{ … }end case [case_label];

choices <= ( simple_expression| discrete_range| others) { |… }

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CASE Statement: ExampleType alu_func is (pass1, pass2, add, subtract);--case func is

when pass1 => result:=operand1;


when add=> result:= operand1+operand2;

when subtract=> result:= operand1-operand2;

end case;

Type alu_func is (pass1, pass2, add, subtract);--case func is



when add=> result:= operand1+operand2;

when subtract=> result:= operand1-operand2;

end case;

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NULL StatementWhen we need to state that when some condition arises no action is to be performed: the null statement has no effect

Syntax:null_statement <= [label : ] null ;

CASE opcode ISWHEN add =>

Acc := Acc + operand;WHEN subtract =>

Acc:= Acc - operand;WHEN nop =>

null ;END CASE;

CASE opcode ISWHEN add =>

Acc := Acc + operand;WHEN subtract =>

Acc:= Acc - operand;WHEN nop =>

null ;END CASE;

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Loop StatementsWhen we need to write a sequence of statements that is to be

repeatedly executed;VHDL has a basic loop statement, which can augmented to form

the usual loop statement of other programming languages;The simplest of loop loop repeats a sequence of statement indefinitely

loop_statement <=[loop_label : ]loop

{sequential_statement }end loop [loop_label];

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Loop Statement:exampleentity counter is

port( clk: in bit; count : out natural);end entity counter;------------------------------------------------------------------------architecture behaviour of counter is begin

incr: process isvariable cont_value: natural := 0;

begin count<= count_value;loop

wait until clk=‘1’;count<= count_value:=(count_value +1) mod 16;count<=count_value;

end loop;end process incr;

end architecture behaviour;

entity counter isport( clk: in bit; count : out natural);

end entity counter;------------------------------------------------------------------------architecture behaviour of counter is begin



wait until clk=‘1’;count<= count_value:=(count_value +1) mod 16;count<=count_value;

end loop;end process incr;


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Loop Statementexit statement

Usually we need to exit the loop when some condition arises.We can use an exit statement to exit to a loop.Syntaxexit_statement <=

[label : ] exit [loop_label] [when boolean_expression];When this statement is executed, any remaining statements in the loop are skipped: the control is transferred to statement after the “end loop” keyword

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Loop Statement:example(2)

entity counter isport( clk, reset : in bit; count : out natural);




loopwait until clk=‘1’ or reset =‘1’;exit when reset =‘1’;count<= count_value:=(count_value +1) mod 16;

entity counter isport( clk, reset : in bit; count : out natural);




loopwait until clk=‘1’ or reset =‘1’;exit when reset =‘1’;count<= count_value:=(count_value +1) mod 16;

Previous counter model including a reset input

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Loop Statement:example(2)---------------- <-- previous page

count<=count_value;end loop;count_value = ‘0’; -- reset = ‘1’count<=count_value;wait until reset=‘0’;

end loop ;end process incr;


---------------- <-- previous page count<=count_value;

end loop;count_value = ‘0’; -- reset = ‘1’count<=count_value;wait until reset=‘0’;

end loop ;end process incr;


When the process is waiting for reset to return to ‘0’, any change s on the clock input are ignoredwhen reset changes to ‘0’ process resume: the outer loop repeatthe exit statement causes control to be transferred out of the inner loop only

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Loop Statementnext statement

When next statement is executed, the current iteration of the loop is completed without executing any further statement, and the next iteration is begun.

Syntaxnext_statement <=

[label : ] next [loop_label] [when boolean_expression];Complicated loop/next structures ca be confusing, making the model hard to read, understand and reusing

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Loop Statementswhile loop

While loop test a condition before each iteration, including the first: if the condition is true, iteration proceeds, if not the loop is terminatedSyntax loop_statement <=[loop_label : ]while condition loop

{sequential_statement }end loop [loop_label]; In absence of exit statement, the while loop terminates only when condition becomes false.We must make sure that the condition eventually become false, orthat an exit statement will exit the loop: otherwise for an infinite loop is better use a simple loop statement

i

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Loop Statementsfor loop

For loop include specification of how many times the body of the loop is to be executed Syntax

loop_statement <=[loop_label : ]for identifier in discrete_range loop


discrete_range <= simple_expression ( to | downto) simple_expression ;

A discrete range can be specified using a discrete type or subtype

i

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Loop Statementsfor loop

for count_value in 0 to 127 loop count_out <= count_value;

wait for 5 ns;end loop ;

for count_value in 0 to 127 loop count_out <= count_value;

wait for 5 ns;end loop ;

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Summary of Loop Statements

Syntax

loop_statement <=[loop_label : ][while condition | for identifier in discrete_range ] loop


i

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Assertion Statement

One of the reasons for writing model of computer systems is to check that a design functions correctly.We can partially test a model applying sample inputs and checking that the outputs meets our expectations.This task can be made easier using assertion statement that check that expected condition are met within the model

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Assertion Statement: Syntax RuleAn assertion statement is used to verify a specifiedcondition and to report if the condition is violated

Syntax:assertion_statement ::=assert condition

[report expression][severity expression]

note: type severity_level is (note, warning, error, failure)

An assertion statement can be included anywhere in a process body

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Assertion Statement

during simulation, the simulator reports if an assertion violation arises during synthesis the condition is assumed to be true and the circuit is optimized on this informationduring formal verification the condition may be interpreted as a condition to be proven by the verifier

Assert initial_value <= max_valuereport “initial value too large”

severity error ;

Assert initial_value <= max_valuereport “initial value too large”

severity error ;

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Assertion Statement :exampleentity SR_flipflop is

port( S,R: in bit; Q: out bit);end entity SR_flipflop ;------------------------------------------------------------------------architecture checking of SR_flipflop is begin

set_reset: process (S,R) isbegin

assert S=‘1’ nand R=‘1’;if S = ‘1’ then

Q<= ‘1’;end if;if R=‘1’ then

Q<=‘0’;end if;

end process set_reset;end architecture checking;

entity SR_flipflop isport( S,R: in bit; Q: out bit);

end entity SR_flipflop ;------------------------------------------------------------------------architecture checking of SR_flipflop is begin

set_reset: process (S,R) isbegin

assert S=‘1’ nand R=‘1’;if S = ‘1’ then

Q<= ‘1’;end if;if R=‘1’ then

Q<=‘0’;end if;

end process set_reset;end architecture checking;

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Concurrent Statements

Basic granularity of concurrency is the processConcurrent VHDL statements include :

Block, Process, Signal assignment, Procedure call, Component instantiation

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VHDL Processes

The process is the key structure in behavioral VHDL modeling. A process is the only means by which the executable functionality of a component is defined. In fact, for a model to be capable of being simulated, all components in the model must be defined using one or more processes.Statements within a process are executed sequentially (although care needs to be used in signal assignment statements since they do not take effect immediately). Variables are used as internal place holders which take on theirassigned values immediately.All processes in a VHDL description are executed concurrently. That is, although statements within a process are evaluated and executed sequentially, all processes within the model begin executing concurrently.

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VHDL Processes

A VHDL process statement is used for all behavioral descriptionsExample simple VHDL process:

ARCHITECTURE behavioral OF clock_component ISBEGINPROCESSVARIABLE periodic: BIT := ‘1’;

BEGINIF en = ‘1’ THENperiodic := not periodic;

END IF;ck <= periodic;WAIT FOR 1 us;

END PROCESS;END behavioral;

ARCHITECTURE behavioral OF clock_component ISBEGINPROCESSVARIABLE periodic: BIT := ‘1’;

BEGINIF en = ‘1’ THENperiodic := not periodic;

END IF;ck <= periodic;WAIT FOR 1 us;

END PROCESS;END behavioral;

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VHDL Processes

In the example process given here, the variable periodic is declared and assigned the initial condition '1'. As long as en is '1', periodic changes value leading to a

potentially new value (called a transaction) to be scheduled for ck by the simulator.The process then suspends for one microsecond of simulation time. The signal ck actually assumes its new value one delta cycle after the process suspends . After the one microsecond suspension, the process once again executes beginning with the IF statement. Note that only variables can be declared in a process, and signals (of a process) are used primarily for control (e.g., en in this case), inputs into a process, or outputs declared outside from a process (e.g., ck in this case).

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Process Syntax

[ process_label : ] PROCESS [( sensitivity_list )]

process_declarations

BEGIN

process_statements

END PROCESS [ process_label ] ;

[ process_label : ] PROCESS [( sensitivity_list )]

process_declarations

BEGIN

process_statements

END PROCESS [ process_label ] ;

NOSIGNAL

DECLARATIONS!

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Process Syntax

The use of process_label at the beginning and end of a process is optional but recommended to enhance code readability.The sensitivity_list is optional in that a process may have either a sensitivity_list, or it must include WAIT statements. However, a process cannot include both a sensitivity_list and WAIT statements. WAIT statements will be covered in a subsequent section.The process_declaration includes declarations for variables, constants, aliases, files, and a number of other VHDL constructs.The process_statements include variable assignment statements, signal assignment statements, procedure calls, wait statements, if statements, while loops, assertion statements, etc.The use of functions and procedures enables code compaction, enhances readability

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Let’s Write a VHDL Model ...

ENTITY full_adder ISPORT ( A, B, Cin : IN BIT;

Sum, Cout : OUT BIT );END full_adder;

ENTITY full_adder ISPORT ( A, B, Cin : IN BIT;

Sum, Cout : OUT BIT );END full_adder;

A

B

Cin

Sum

Cout

Can we build the Full Adder’s architecture using these gates?

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Full Adder Architecture

A B Cin Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

for Sum:Cin (I.e. Carry In):

A B 0 10 0 0 10 1 1 01 1 0 11 0 1 0

for Cout (I.e. Carry Out):Cin (I.e. Carry In)

A B 0 10 0 0 00 1 0 11 1 1 11 0 0 1

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Two Full Adder Processes

A

B

Cin

Sum

Cout

Summation:PROCESS( A, B, Cin)BEGIN

Sum <= A XOR B XOR Cin;END PROCESS Summation;

Summation:PROCESS( A, B, Cin)BEGIN


Carry:PROCESS( A, B, Cin)BEGIN

Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);

END PROCESS Carry;

Carry:PROCESS( A, B, Cin)BEGIN


END PROCESS Carry;

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Complete Architecture

ARCHITECTURE example OF full_adder IS-- Nothing needed in declarative block...

BEGIN

Summation: PROCESS( A, B, Cin)BEGIN


Carry: PROCESS( A, B, Cin)BEGIN


END PROCESS Carry;

END example;

ARCHITECTURE example OF full_adder IS-- Nothing needed in declarative block...

BEGIN

Summation: PROCESS( A, B, Cin)BEGIN


Carry: PROCESS( A, B, Cin)BEGIN


END PROCESS Carry;

END example;

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ProcessWe put the entire architecture together. The two process defined on the previous slide are placed in the same architecture. Note that the Sum and Carry processes execute concurrently.This model does not use explicit time (that is, there are no AFTER phrases or “wait for” statements. Thus, this model is purely functional. If timing is important, delay phrases (i.e., AFTER clauses) to the signal assignment statements, or “WAIT FOR” statements can be added in the processes. Note that if WAIT statements are used in a process, the process cannot have a sensitivity list.Alternatively, the Carry output could have been described using programming language constructs instead of the logic equations shown previously. Here, a set of nested if-then-else statements is used to implement the table lookup method. A case statement could also be used.

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Alternate Carry Process

Carry: PROCESS( A, B, Cin)BEGINIF ( A = ‘1’ AND B = ‘1’ ) THEN

Cout <= ‘1’;ELSIF ( A = ‘1’ AND Cin = ‘1’ ) THEN

Cout < = ‘1’;ELSIF ( B = ‘1’ AND Cin = ‘1’ ) THEN

Cout <= ‘1’;ELSE

Cout <= ‘0’;END IF;

END PROCESS Carry;

Carry: PROCESS( A, B, Cin)BEGINIF ( A = ‘1’ AND B = ‘1’ ) THEN

Cout <= ‘1’;ELSIF ( A = ‘1’ AND Cin = ‘1’ ) THEN

Cout < = ‘1’;ELSIF ( B = ‘1’ AND Cin = ‘1’ ) THEN

Cout <= ‘1’;ELSE

Cout <= ‘0’;END IF;

END PROCESS Carry;

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VHDL Sequential Statements

Sequential statements are used within processes and are executed in a top-down fashion. The illustrative (but incomplete) list shown on the next slide includes many of the commonly used forms. The VHDL Language Reference Manual provides a complete list.Many of these statement types will be explained in further sections of this module. Some of you may note that these control structures operate almost exactly like their counterparts in Adaexcept for the assert and sequential signal assignment statements.

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VHDL Sequential Statements

Assignments executed sequentially in processesSequential statements

{Signal, variable} assignmentsFlow control

IF <condition> THEN <statements> [ELSIF <statements] [ELSE <statements>] END IF;FOR <range> LOOP <statements> END LOOP;WHILE <condition> LOOP <statements> END LOOP;CASE <condition> IS WHEN <value> => <statements>

{WHEN <value> => <statements>}[WHEN others => <statements>]

END CASE;WAIT [ON <signal>] [UNTIL <expression>] [FOR <time>] ;ASSERT <condition> [REPORT <string>] [SEVERITY <level>] ;

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A Design Example 2-bit Counter

ENTITY count2 ISGENERIC(prop_delay : TIME := 10 ns);PORT (clock : IN BIT;

q1, q0: OUT BIT);END count2;

ARCHITECTURE behavior OF count2 ISBEGIN

count_up: PROCESS (clock)VARIABLE count_value: NATURAL := 0;

BEGINIF clock='1' THEN

count_value := (count_value+1) MOD 4;q0 <= bit'val(count_value MOD 2) AFTER prop_delay;q1 <= bit'val(count_value/2) AFTER prop_delay;

END IF;END PROCESS count_up;

END behavior;

ENTITY count2 ISGENERIC(prop_delay : TIME := 10 ns);PORT (clock : IN BIT;

q1, q0: OUT BIT);END count2;

ARCHITECTURE behavior OF count2 ISBEGIN

count_up: PROCESS (clock)VARIABLE count_value: NATURAL := 0;

BEGINIF clock='1' THEN

count_value := (count_value+1) MOD 4;q0 <= bit'val(count_value MOD 2) AFTER prop_delay;q1 <= bit'val(count_value/2) AFTER prop_delay;

END IF;END PROCESS count_up;

END behavior;

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A Design Example : 2-bit CounterIn this example, we show a model for a simple 2-bit counter which counts clock pulses. The component has clock as an input, and two outputs which represent the LSB and MSB of a two-bit unsigned number.Several of the constructs used above have not been shown before in this series of educational modules. For example, bit'val(count_value mod 2) is a function which returns a value of type bit; count_value is a natural number (i.e. an integer greater than, or equal to, zero); count_value mod 2 returns the LSB value of the counter value; but the LSB value is of type natural. Since we want the LSB to be of type bit instead, we cast it by using the 'val (read as "tic val") attribute on the type bit.Also note the use a a generic parameter used to facilitate the assignment of delays in the signal assignment statements.

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Mix and Match

Within an architecture we have two signals and the following process

DoSomething: PROCESSBEGIN

WAIT ON TheirSignal;

OurSignal <= ‘1’;WAIT FOR 10 ns;

OurSignal <= ‘0’;WAIT UNTIL (TheirSignal = ‘1’);

OurSignal <= ‘1’;

END PROCESS DoSomething;

DoSomething: PROCESSBEGIN

WAIT ON TheirSignal;

OurSignal <= ‘1’;WAIT FOR 10 ns;

OurSignal <= ‘0’;WAIT UNTIL (TheirSignal = ‘1’);

OurSignal <= ‘1’;

END PROCESS DoSomething;

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Mix and MatchWe show here how wait statements can be used to synchronize the execution of the process, and also how to sensitize a process to signal changes in another.In this example, the process does not execute until TheirSignal changes value. Then we schedule a transaction to ‘1’ on OurSignal and wait for 10 ns. Note, however, that since there is no AFTER clause in the assignment for OurSignal, it will assume its new value in one delta cycle.After waiting 10 ns, DoSomething assigns a value of '0' to OurSignal; Again, OurSignal will actually take on the new value after one delta cycle. Execution of DoSomething is then suspended until TheirSignal becomes '1'. When execution resumes, OurSignal is set to '1' and the process immediately repeats from the top.

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Blocks and GuardsBlocks are concurrent statementsBlocks provide a mechanism to partition an architecture description

Items declared in declarative region of block are visible only inside the block, e.g. :

signals, subprogramsBlocks may be nested to define a hierarchicalpartitioning of the architectural descriptionBlock may be used to group together signal assignments and other concurrent statements which may share some common locally declared objects.

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Blocks and GuardsUnique to blocks is the GUARD construct

A conditional GUARD can be included in the BLOCK declaration. If such a GUARD expression exists, then any signal assignment statement in the block which has the keyword GUARDED will disconnect the corresponding signal driver if the GUARD expression evaluates to false. This is one mechanism which can be used to guarantee that there be only one active driver onExample

ARCHITECTURE guarded_assignments OF n_1_mux ISBEGIN

bi: FOR j IN i’RANGE GENERATEbj: BLOCK (s(j)=‘1’ OR s(j)=‘Z’)BEGIN

x <= GUARDED i(j);END BLOCK;

END GENERATE;END guarded_assignments;

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Block Statement: Syntax RuleThe submodules in an architecture body can be

described as block:

block_statement <=[block_label : ]block [(guard_expression)]

block_headerblock_declarative_part

beginblock_statement_part

end block [block_label]

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ARCHITECTURE stuff OF my_entity ISSIGNAL ThisBit : BIT;SIGNAL ThisBitVector : BIT_VECTOR(1 TO 5);SIGNAL ThisInteger : INTEGER;SIGNAL ThisString : STRING(1 TO 4);

BEGINThisBit <= ‘1’;ThisBitVector <= “10010”;ThisInteger <= 567 AFTER 10 ns;ThisString <= “VHDL” AFTER 10 ns,

“ is ” AFTER 20 ns, “fun!” AFTER 30 ns;

END stuff;

ARCHITECTURE stuff OF my_entity ISSIGNAL ThisBit : BIT;SIGNAL ThisBitVector : BIT_VECTOR(1 TO 5);SIGNAL ThisInteger : INTEGER;SIGNAL ThisString : STRING(1 TO 4);

BEGINThisBit <= ‘1’;ThisBitVector <= “10010”;ThisInteger <= 567 AFTER 10 ns;ThisString <= “VHDL” AFTER 10 ns,

“ is ” AFTER 20 ns, “fun!” AFTER 30 ns;

END stuff;

Signal Assignment Statements

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Signal Assignment Statements

•The structure of signal assignment statement allows some flexibility.• The signal type of the result on the right hand side must match the type of the signal being assigned. This is illustrated in the first two signal assignment statements•The third assignment shows the use of a single after clause used to control how much simulation time must pass before the assigned signal takes on its new value. •As seen in the fourth example, multiple assignments can be made in a single statements by separating them with commas. This sequence of assignments is called a "waveform".•If a signal assignment statement has no after clause, a clause equivalent to "after 1 delta cycle" is implied. •Delta cycles are key to the VHDL timing model and have been previously discussed .

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SubprogramsSimilar to subprograms found in other languages

Allow repeatedly used code to be referenced multiple times without rewritingBreak down large blocks of code into small, more manageable parts

The use of functions and procedures enables code compaction, enhances readability, and supports hierarchy by allowing code sequences that are used frequently to be defined and subsequently reused easily.

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SubprogramsVHDL provides functions and procedures

Functions return a value Functions can be used in signal and variable assignment statements:

e.g. A <= abs(-1); -- where abs() returns absolute value

Procedures do not have return values Procedures can manipulate the signals or variables passed to them as parameters:

e.g. absolute(A);“absolute()” here is a procedure that directly assigns A

its absolute value

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Functions

Produce a single return value: Functions must have a return value and a return statement

Called by expressionsThey are called in statements where a value is needed (e.g. assignment statements, conditional tests). Note that only one value can be returned by a function call.

Cannot modify the parameters passed to themRequire a RETURN statementA function can have multiple Return statements;

the simulator will exit the function when it encounters the first return statement in the execution of the function

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Functions

Produce a single return valueCalled by expressionsCannot modify the parameters passed to themRequire a RETURN statement

FUNCTION add_bits2 (a, b : IN BIT) RETURN BIT ISVARIABLE result : BIT; -- variable is local to function

BEGINresult := (a XOR b);RETURN result; -- the two functions are equivalent

END add_bits2;

FUNCTION add_bits2 (a, b : IN BIT) RETURN BIT ISVARIABLE result : BIT; -- variable is local to function

BEGINresult := (a XOR b);RETURN result; -- the two functions are equivalent

END add_bits2;

FUNCTION add_bits (a, b : IN BIT) RETURN BIT ISBEGIN -- functions cannot return multiple values

RETURN (a XOR b);END add_bits;

FUNCTION add_bits (a, b : IN BIT) RETURN BIT ISBEGIN -- functions cannot return multiple values

RETURN (a XOR b);END add_bits;

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Functions

Functions must be called by other statementsParameters use positional association

ARCHITECTURE behavior OF adder ISBEGIN

PROCESS (enable, x, y)BEGINIF (enable = '1') THENresult <= add_bits(x, y);carry <= x AND y;

ELSEcarry, result <= '0';

END PROCESS;END behavior;


PROCESS (enable, x, y)BEGINIF (enable = '1') THENresult <= add_bits(x, y);carry <= x AND y;

ELSEcarry, result <= '0';

END PROCESS;END behavior;

FUNCTION add_bits

(a, b : IN BIT)s

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FunctionsThis example illustrates the use of a function call in a signal assignment statement where the value returned by the function add_bits() is assigned to the signal result. Also note that the parameters passed to the function during the call are associated either by position (as in the example above) or by name. In this example, x is associated with parameter a, and y is associated with parameter b.

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Procedures

May produce multiple output valuesAre invoked by statementsMay modify the parameters

PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT;SIGNAL temp_result, temp_carry : OUT BIT) IS

BEGIN -- procedures can return multiple valuestemp_result <= (a XOR b) AND en;temp_carry <= a AND b AND en;

END add_bits3;

PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT;SIGNAL temp_result, temp_carry : OUT BIT) IS

BEGIN -- procedures can return multiple valuestemp_result <= (a XOR b) AND en;temp_carry <= a AND b AND en;

END add_bits3;

Do not require a RETURN statement

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ProceduresUnlike functions, procedures may modify multiple signals and variables in a single call. Procedures can operate on their parameters and are able to make assignments to signals and variables in their parameter lists that are of mode OUT or INOUT.A procedure call, therefore, is itself a complete VHDL statement.. May produce multiple output valuesParameter types and modes must be compatible with the signals in the parameter list during a procedure call.Actually, procedure overloading is achieved by defining multiple procedures (or functions, for that matter) with different parameter types to distinguish among them in procedure (or function) calls.

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Procedures (Cont.)

With parameter passing, it is possible to further simplify the architecture


PROCESS (enable, x, y)BEGINadd_bits3(x, y, enable,

result, carry);END PROCESS;

END behavior;

PROCEDURE add_bits3

(SIGNAL a, b, en : IN BIT;SIGNAL temp_result, temp_carry : OUT BIT)

The parameters must be compatible in terms of data flow and data type

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Attributes

Attributes provide information about certain items in VHDL

E.g. types, subtypes, procedures, functions, signals, variables,constants, entities, architectures, configurations, packages, components

General form of attribute use :

VHDL has several predefined, e.g :X'EVENT -- TRUE when there is an event on signal XX'LAST_VALUE -- returns the previous value of signal XY'HIGH -- returns the highest value in the range of YX'STABLE(t) -- TRUE when no event has occurred on signal X in the past ‘t’ time

name'attribute_identifier -- read as “tick”name'attribute_identifier -- read as “tick”

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Attributes

Attributes can return various types of information.

For example, an attribute can be used to determine the depth of an array, its range, its leftmost index, etc. Additionally, the user may define new attributes to cover specific situations. This capability allows user-defined constructs and data types to use attributes.

An example of the use of attributes is in assigning information to a VHDL construct, such as board location, revision number, etc.

, such as board location, revision number, etc.

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AttributesRegister Example

The following example shows how attributes can be used to make an 8-bit registerSpecifications :

Triggers on rising clock edgeLatches only on enable highHas a data setup time of x_setupHas propagation delay of prop_delay

ENTITY 8_bit_reg ISGENERIC (x_setup, prop_delay : TIME);PORT(enable, clk : IN qsim_state;

a : IN qsim_state_vector(7 DOWNTO 0); b : OUT qsim_state_vector(7 DOWNTO 0));

END 8_bit_reg;

qsim_state type is being used : includes logic values 0, 1, X, and Z

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AttributesRegister Example (Cont.)

ARCHITECTURE first_attempt OF 8_bit_reg ISBEGIN

PROCESS (clk)BEGINIF (enable = '1') AND a'STABLE(x_setup) AND

(clk = '1') THEN -- clk may<- X,Zb <= a AFTER proper_delay;

END IF;END PROCESS;

END first_attempt;

The following architecture is a first attempt at the registerThe use of 'STABLE is to used to detect setup violations in the data input

What happens if a does not satisfy its setup time requirement of x_setup?

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What happens if a does not satisfy its setup time requirement of x_setup?

If the setup requirement is not met, the body of the IF statement will not execute, and the value on a will not be assigned to b.

The process checks that clk and enable are ‘1’ to store the data, it does not does not consider the possibility that clk may have transitioned to ‘1’ from either ‘X’ or ‘Z’.

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ARCHITECTURE behavior OF 8_bit_reg ISBEGIN

PROCESS (clk)BEGINIF (enable = '1') AND a'STABLE(x_setup) AND

(clk = '1') AND (clk'LAST_VALUE = '0') THENb <= a AFTER delay;

END IF;END PROCESS;

END behavior;

The following architecture is a second and more robust attempt The use of 'LAST_VALUE ensures the clock is rising from a value of ‘0’

An ELSE clause could be added to define the behaviour when the requirements are not satisfied

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Signal resolution and BusesVHDL normally allows one driver for a signalIn many digital systems, buses are used to connecta number of output drivers to a common signal

Open-drain; wired-or/and; pull-up; tri-state drivers

To model signals with multiple drivers VHDL uses the notion of resolved types for signalsA resolved type includes in its definition a resolution function

It takes the values of all the drivers contributing to a signal and combines them to dertermine the final signal value

SyntaxSubtype_indication::= [resolution_function_name]

Type_mark[contraint]

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Signal resolution and Buses: example

Type logic_level is (L,Z, H);

Type logic_array is array(integer range <>)of logic_level;

Function resolve_logic(drivers: in logic_array) return logic_level;

Subtype resolved_level is resolve_logic logic_level;

Type logic_level is (L,Z, H);

Type logic_array is array(integer range <>)of logic_level;

Function resolve_logic(drivers: in logic_array) return logic_level;

Subtype resolved_level is resolve_logic logic_level;

<> (box) place-holders for the index range, which be filled in later when the array type is used

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Signal resolution and Buses: example

Function resolve_logic(drivers:in logic_array) return

logic_level;

begin

for index in drivers‘range loop

if drivers(index)= L then

return L;

end if;

end loop;

return H;

end resolve logic;

Function resolve_logic(drivers:in logic_array) return

logic_level;

begin

for index in drivers‘range loop

if drivers(index)= L then

return L;

end if;

end loop;

return H;

end resolve logic;

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IEEE Standard LogicObject defined in package IEEE are „visible“when:Library IEEE;

USE IEEE.STD_LOGIC_1164.all

There are 2 version:Std_logicStd_ulogic: the unresolved version of std_logicResolved types:

U: unitialized W: weak unknownX: forcing an unknown L: weak 00: forcing 0 H: weak 11: forcing 1 - : don‘t care

Z: high impedance (weakest)

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Module Outline

Introduction

VHDL Design Example


Basic VHDL Constructs

Examples

Summary

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Examples

Build a library of logic gatesAND, OR, NAND, NOR, INV, etc.

Include sequential elementsDFF, Register, etc.

Include tri-state devicesUse 4-valued logic

‘X’, ‘0’, ‘1’, ‘Z’Encapsulate global declarations in a package

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Global Package

PACKAGE resources IS

TYPE level IS ('X', '0', '1', 'Z'); -- enumerated type

TYPE level_vector IS ARRAY (NATURAL RANGE <>) OF level;-- type for vectors (buses)

SUBTYPE delay IS TIME; -- subtype for gate delays

-- Function and procedure declarations go here

END resources;

Package declaration for the user defined four valued type package.

It includes the four valued enumerated type itself, a vector or array of that type, and a subtype of type time to be used for delay values. Functions and/or procedures could be declared in the package (with their actual implementation descriptions included in the package body),

11/17/2005 176

Two Input AND Gate Example

USE work.resources.all;

ENTITY and2 IS

GENERIC(trise : delay := 10 ns;tfall : delay := 8 ns);

PORT(a, b : IN level;c : OUT level);

END and2;

ARCHITECTURE behav OF and2 IS

BEGIN

one : PROCESS (a,b)

BEGINIF (a = '1' AND b = '1') THENc <= '1' AFTER trise;

ELSIF (a = '0' OR b = '0') THENc <= '0' AFTER tfall;

ELSEc<= 'X' AFTER (trise+tfall)/2;

END IF;

END PROCESS one;

END behav;

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And Gate Simulation Results

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Tri-State Buffer Example


ENTITY tri_state IS

GENERIC(trise : delay := 6 ns;tfall : delay := 5 ns;thiz : delay := 8 ns);

PORT(a : IN level;e : IN level;b : OUT level);

END tri_state;

ARCHITECTURE behav OF tri_state IS

BEGIN

one : PROCESS (a,e)

BEGINIF (e = '1' AND a = '1') THEN

-- enabled and valid datab <= '1' AFTER trise;

ELSIF (e = '1' AND a = '0') THENb <= '0' AFTER tfall;

ELSIF (e = '0') THEN -- disabledb <= 'Z' AFTER thiz;

ELSE -- invalid data or enableb <= 'X' AFTER (trise+tfall)/2;

END IF;

END PROCESS one;

END behav;

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Tri-State Buffer Simulation Results

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D Flip Flop Example


ENTITY dff IS

GENERIC(tprop : delay := 8 ns;tsu : delay := 2 ns);

PORT(d : IN level;clk : IN level;enable : IN level;q : OUT level;qn : OUT level);

END dff;

ARCHITECTURE behav OF dff ISBEGINone : PROCESS (clk)

BEGIN-- check for rising clock edgeIF ((clk = '1' AND clk'LAST_VALUE = '0')

AND enable = '1') THEN -- ff enabled-- first, check setup time requirementIF (d'STABLE(tsu)) THEN

-- check valid input dataIF (d = '0') THEN

q <= '0' AFTER tprop;qn <= '1' AFTER tprop;

ELSIF (d = '1') THENq <= '1' AFTER tprop;qn <= '0' AFTER tprop;

ELSE -- else invalid dataq <= 'X';qn <= 'X';

END IF;ELSE -- else violated setup time requirement

q <= 'X';qn <= 'X';

END IF;END IF;

END PROCESS one;END behav;

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D Flip Flop Simulation Results

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Finite State Machine: Specification

CS IN NS OUT ST1 11 ST1 00ST1 01 ST2 00ST1 -0 ST2 00ST2 11 ST1 11ST2 01 ST3 11ST2 -0 ST3 11ST3 00 ST3 01ST3 10 ST4 01ST3 -1 ST4 01ST4 0- ST3 10ST4 1- ST2 10

ST211

ST100

ST410

ST301

01, -0

00

01, -0 10, -1

1-

11 0-

ST211

ST100

ST410

ST301

01, -0

00

01, -0 10, -1

1-

11 0-

ST211

ST100

ST410

ST301

01, -0

00

01, -0 10, -1

1-

11 0-

11

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Finite State Machine: Source CodeEntity FSM2 is

Port ( RST, CLK : In bit;CMD_IN : In bit_vector (0 to 1);Y_OUT : Out bit_vector (0 to 1));

end FSM”;architecture MOORE of FSM2 is –- FSM Mealy ??

type T_STATE is ( ST1, ST2, ST3, ST4);signal current_state, next_state : T_STATE;

BEGIN-----------------------Reset : Sequential Process---------------------

reg: process (CLK, RST)begin

if RST = ‘1’ thencurrent_state <= ST1;elseif (CLK’event and CLK = ‘1’) then

current_state <= next_state;end if;

end process;

11/17/2005 184

Finite State Machine: Source Code (Cont.)

-----------------------Next State Logic: Combinatorial Process---------------------

comb: process (current_state, CMD_IN)begin

case current_state iswhen ST1 =>

if (CMD_IN=“00” or CMD_IN=“01” or CMD_IN=“10”) thenNEXT_STATE <= ST2;

elseNEXT_STATE <= ST1;

end if;when ST2 =>



end if;when ST3 =>



end if;

11/17/2005 185

Finite State Machine: Source Code (Cont.)

when ST4 =>if (CMD_IN=“00” or CMD_IN=“01”) then

NEXT_STATE <= ST3;else

NEXT_STATE <= ST2; end if;

end case;end process;

-----------------------Output Logic: Combinatorial Process---------------------

out_logic: process (current_state)begin

case current_state iswhen ST1 =>

Y_OUT <= “00”;when ST2 =>



Y_OUT <= “10”;end case;

end process;end MOORE;

11/17/2005 188

References[Bhasker95] Bhasker, J. A VHDL Primer, Prentice Hall, 1995.

[Calhoun95] Calhoun, J.S., Reese, B.,. “Class Notes for EE-4993/6993: Special Topics in Electrical Engineering (VHDL)”, Mississippi State University, http://www.erc.msstate.edu/mpl/vhdl-class/html, 1995.

[Coelho89] Coelho, D. R., The VHDL Handbook, Kluwer Academic Publishers, 1989.

[Gajski83] Gajski, Daniel D. and Kuhn, Robert H., "Guest Editors Introduction - New VLSI Tools", IEEE Computer, pp 11-14, IEEE, 1983

[Lipsett89] Lipsett, R., C. Schaefer, C. Ussery, VHDL: Hardware Description and Design, Kluwer Academic Publishers, , 1989.

[LRM94] IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1993, 1994.

[Navabi93] Navabi, Z., VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, 1993.

[Menchini94] Menchini, P., “Class Notes for Top Down Design with VHDL”, 1994.

[MG90] An Introduction to Modeling in VHDL, Mentor Graphics Corporation, 1990.

[MG93] Introduction to VHDL, Mentor Graphics Corporation, 1993.

[Perry94] Perry, D. L., VHDL, McGraw-Hill, 1994.

[Smith88] Smith, David, “What is Logic Synthesis”, VLSI Design and Test, October, 1988.

[USE/DA94] USE/DA Standards Survey, 1994.

[VI93] VHDL International Survey, 1993.

[Walker85] Walker, Robert A. and Thomas, Donald E., "A Model of Design Representation and Syntheses", 22nd Design Automation Conference, pp. 453-459, IEEE, 1985

[Williams94] Williams, R. D., "Class Notes for EE 435: Computer Organization and Design", University of Virginia, 1994.

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