A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 1, JANUARY 2011 165

allows higher level of reconfiguration compared to blurred images forsame quality [Fig. 6(d)].

V. CONCLUSION

We have presented a reconfigurable SRAM architecture forlow-power mobile multimedia applications. The proposed architectureuses spatial voltage scaling where cells storing lower-order bits ofan image pixel are operated at a lower voltage, and the higher-ordercells are operated at nominal voltage. The results demonstrate that45% power savings can be obtained with marginal image qualitydegradation.

REFERENCES

[1] S. Yang et al., Power and performance analysis of motion estimationbased on hardware and software realizations, IEEE Trans. Computers,vol. 54, no. 6, pp. 714716, Jun. 2005.

[2] G. Chen and M. Kandemir, Optimizing address code generation forarray-intensive DSP applications, in Proc. Int. Symp. Code GenerationOptimization, 2005, pp. 141152.

[3] S. Mukhopadhyay et al., Modeling of failure probability and statisticaldesign of SRAM array for yield enhancement in nano-scaled CMOS,IEEE Trans. Comput.-Aided Design, vol. 24, no. 5, pp. 18591880,Dec. 2005.

[4] F. Kurdahi et al., Error aware design, in Proc. 10th Eur. Conf. DigitalSystem Design Architectures, Aug. 2007, pp. 815.

[5] A. K. Djahromi et al., Cross layer error exploitation for aggressivevoltage scaling, in Proc. IEEE Int. Symp. Quality Electronic Design,Mar. 2007, pp. 192197.

[6] J. George, B. Marr, B. E. S. Akgul, and K. V. Palem, Probabilisticarithmetic and energy efficient embedded signal processing, in Proc.CASES, Oct. 2006, pp. 168198.

[7] K. Yi, S. Y. Cheng, F. Kurdahi, and A. Ettawil, A partial memoryprotection scheme for higher effective yield of embedded memory forvideo data, in Proc. ACSAC, 2008, pp. 273278.

[8] M. Cho, J. Schlessman, W. Wolf, and S. Mukhopadhyay, Accuracy-aware SRAM: A reconfigurable low power SRAM architecture for mo-bile multimedia applications, in Proc. ASPDAC, 2009, pp. 823828.

[9] K. Zhang, V. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N.Vallepalli, Y. Wang, B. Zheng, and M. Bohr, A 3-GHz 70 MB SRAMin 65 nm CMOS technology with integrated column-based dynamicpower supply, in Proc. ISSCC 2005, pp. 474611.

[10] [Online]. Available: http://www.imageprocessingplace.com/[11] Z. Wang, A. C. Bovik, H. R. Sheikh, and E. P. Simoncelli, Image

quality assessment: From error visibility to structural similarity, IEEETrans. Image Process., vol. 13, no. 4, pp. 600612, Apr. 2004.

[12] T. Liu, T. Lin, S. Wang, W. Lee, J. Yang, K. Hou, and C. Lee, A 125uW, fully scalable MPEG-2 and H.264/AVC video decoder for mobileapplications, IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 161169,Jan. 2007.

A Low-Jitter ADPLL via a Suppressive Digital Filter andan Interpolation-Based Locking Scheme

Hsuan-Jung Hsu and Shi-Yu Huang

AbstractIn this brief, we present a low-jitter and wide-range all-digitalphase-locked loop (ADPLL). This ADPLL achieves low output clock jitterby a number of schemes. First, the phase is locked quickly through a predic-tive phase-locking scheme. Then, the jitter is further reduced by a suppres-sive digital loop filter. Finally, an interpolation-based locking scheme is uti-lized to enhance the resolution of the digitally controlled oscillator (DCO)so as to further reduce the phase error and jitter. Simulation results showthat the jitter performance is very close to that of the free-running DCO.Measurement results show that the and are 56and 7.28 ps, respectively, when the output clock of the ADPLL is runningat 600 MHz.

Index TermsAll-digital phase-locked loop (ADPLL), digital filter, dig-itally controlled oscillator (DCO), frequency interpolation, locking algo-rithm.

I. INTRODUCTION

In a system-on-chip (SOC) era, it is common that a chip is embeddedwith its own clock generator. Phase-locked loop (PLL) is an importantclocking device for these digital systems. Traditionally, a PLL is partlymade of some analog components. However, an analog control signalis often subject to digital switching noise so that more design efforts areneeded when operating in a noisy digital environment. Moreover, theloop filter in traditional analog PLLs is usually composed of passivedevices, such as resistors and capacitances, leading to not only largearea but also low portability to different processes. On the contrary, anall-digital phase-locked loop (ADPLL) has not only higher noise im-munity but also a number of other attractive features, including bettertestability, programmability, and ease of integration into digital sys-tems. With the aid of digital filtering techniques, the passive devicescould be avoided to save the cost and increase the portability of theADPLLs.

Numerous works on ADPLL have been presented in the past [1][4],[6], [9][12], in which the digitally controlled oscillator (DCO) is atthe heart. Unlike the traditional analog voltage controlled oscillator(VCO), the oscillator in ADPLL is digitally controlled so that somequantization error exists. High-resolution design of DCO is thus pur-sued to catch up with the performance of analog VCO where the res-olution can be defined as the minimum delay difference between theclock periods of two adjacent frequencies a DCO can generate. How todesign the fine-resolution delay cell becomes the early challenge of theDCO design. Several types of DCOs have been analyzed and summa-rized in [12]. In [8], the average resolution of DCO could be enhancedto as fine as 1 ps with the insertion of more delay cells and control lines,implying that the performance bottleneck of ADPLL is now shifting tothe other components such as the phase detectors (PDs) and/or the loopfilters.

In addition to the DCO, the resolution of an ADPLL is also dictatedby the phase-frequency detector (PFD), or simply PD in some AD-PLLs. Recently, the design of a high-resolution PD that is able to dis-tinguish a minute phase difference is becoming more desirable. Sheng

Manuscript received January 15, 2009; revised May 18, 2009. First publishedOctober 13, 2009; current version published December 27, 2010.

The authors are with the Department of Electrical Engineering, NationalTsing-Hua University, Hsin-Chu 30013, Taiwan (e-mail: [email protected]; [email protected]).

Digital Object Identifier 10.1109/TVLSI.2009.2030410

1063-8210/$26.00 2009 IEEE

166 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 1, JANUARY 2011

Fig. 1. Architecture of the ADPLL.

et al. [6] used pulse amplifier and signal extender to amplify the smallphase difference, i.e., 5 ps, to be detected. Tierno et al. [11] inserted ameta-stability filter to enhance the resolution of proposed PFD. In [12],we discovered that a latch-based sense amplifier could be modified toserve as a good PD in which the minimum resolvable phase differenceis as small as 1 ps.

Since the two critical components, i.e., the PD and the DCO, haveperformed almost as well as their analog counterparts, the digital loopfilter or called controller in the ADPLL turns into a new focal point. Thedigital loop filter, in some sense, seems like the bridge between the PDand the DCO. It converts the phase information received from the PDinto a digital code sequence that directs the increase or the decreaseof the frequency of the DCO. This is especially difficult for ADPLLssince most PDs only provide the phase polarity, not the exact phasemagnitude. Whether the frequency of DCO can adequately react to thephase polarity has a large influence on performance parameters such asjitter and phase noise.

In this brief, we present an ADPLL that reuses the high-resolutionDCO and the PD proposed in [12]. We further improve its jitter perfor-mance by a four-step frequency/phase locking procedure: 1) frequencylocking, 2) preliminary phase locking, 3) jitter reduction by a suppres-sive filter, and finally 4) phase error reduction by frequency interpola-tion. Experimental results show that the proposed scheme can reducethe jitter to a level as small as 7.28 ps, which is only 3% away from theideal jitter amount (7.06 ps) of a free-running DCO, when the outputclock is operating at 600 MHz.

The rest of this paper is organized as follows. Section II provides theoverview of our ADPLL architecture and the designs of the DCO andthe PD. Section III discusses the details of the four-step locking proce-dure. Section IV presents our experimental results. Finally, Section Vconcludes.

II. THE ADPLL ARCHITECTURE

A. Overall Architecture

Fig. 1 shows the architecture of the proposed ADPLL. In integer-ADPLL, the frequency of the output clock signal generated by the DCOis divided by times to produce a divided clock signal. The parameter will be referred to as the frequency multiplicative factor in the se-quel. When the frequency of an ADPLL is locked (i.e., the frequencyof divided clock has the same frequency as the reference clock), theoutput clock frequency is times the reference clock frequency.

The DCO is often regarded as the most critical part among thesecomponents because it dictates the frequency range and the resolutionthat an ADPLL can synthesize. It is controlled by 12 b in our design,dividing into two parts: a 6-b coarse control code and a 6-b fine con-trol code. The PD is to compare the phase polarity between the divided

Fig. 2. Locking procedure of the ADPLL.

Fig. 3. Relationship between phase error and control code.

Fig. 4. Quick phase-locking approach.

clock signal and the reference clock signal. It generates two mutuallyexclusive signals: lead and lag to show whose edge is leading. Sincethe bandwidth of the DCO is quite large, the frequency detector is tocompare the divided clock with the reference clock so as to make thefrequency of DCO gradually approach the target frequency. Once thefrequency of DCO has been tuned as close as possible to the target fre-quency, signal frequency_lock is asserted and the phase-locking processbegins. The controller performs a phase-locking algorithm, mimickingthe function of loop filter in an analog PLL. In a number of referenceclock cycles, the control code will gradually converge to a small range,indicating that the phase has also been locked to the reference clockand the target frequency has been synthesized.

B. Digitally Controlled Oscillator

The DCO architecture we use in this design follows the one dis-cussed in [12]. The fine-tuning delay cell comprises an array of tunablemetaloxidesemiconductor (MOS) capacitance, resulting in a high-resolution, uniform, and monotonic delay profile of DCO. Such prop-erties are contributive to the frequency detection and phase locking andsimplify the design of the digital loop filter. The average resolution ofone coarse step and one fine step is summarized in Table I. It is notablethat the delay range of the fine-tuning delay cell can always cover a


Fig. 5. Operation flow of the suppressive filter.

TABLE IMEASURED CHARACTERISTICS OF THE DCO

coarse-tuning step even after manufacturing so that the DCO does nothave any uncovered region within the supported frequency range.

C. Phase DetectorWe adopt the sense-amplifier-based PD proposed in [12] since it can

almost eliminate the dead zone, (which is the minute range of phasedifference a PD cannot properly react). The phase polarity of two inputclocks is sent to both frequency detector and phase-locking controller.Experimental results show that the performance will not be affectedeven when there is severe process variation.

III. LOCKING PROCEDURE OF THE ADPLLThe locking procedure is the most contributive part in this work as

compared to previous ADPLL designs. It is composed of four stepsshown as Fig. 2. In step 1, the frequency tuning range of DCO should benarrowed down to the proximity of the target frequency so as to facili-tate the subsequent phase locking. This is achieved by tuning the coarsecontrol code of DCO under the guidance of the frequency detector. Instep 2, we start the preliminary phase locking with the reference clock.The phase will be locked quickly but roughly, implying that the jittercould still be large. Next, a suppressive digital filter is adopted in step3 to further reduce the jitter. Finally, an interpolation-based locking al-gorithm is used to make the phase error as small as possible. In thefollowing sections, we will introduce the detail of each step. In the se-quel, the reference clock signal in our ADPLL is denoted as ref_clk,and the divided clock signal is denoted as div_clk. We will mentionthese two signals frequently in the rest of our discussion.

A. Frequency DetectorSince the initial frequency of the DCO could be far from the target

frequency, we should draw it to closer to the target one first. This isdone by a binary search process to select an adequate coarse controlcode so that the phase locking in the following steps can be achieved by

tuning fine control code only. In the frequency detector, the most crit-ical operation is the frequency comparisonan operation that checks ifref_clk or div_clk has a higher frequency. The one with a larger numberof edges within a preset period is assumed to have a higher frequency.Since the accuracy of the edge counting is limited to the setup/holdtime constraint of a flip-flop, we further use the information derivedby our 1-ps-resolution PD to achieve a higher accuracy [12]. The fre-quency_lock signal will be triggered once the binary search process iscompleted. In other words, we have found the two neighboring coarsecontrol codes surrounding the target frequency. Therefore, the delaydifference between the current clock period and the target one is withinthe delay of one coarse step, said about 230 ps by the measurement re-sults in TSMC18 process.

B. Preliminary Phase-Locking SchemeBefore starting phase locking, the DCO is reset first to align the phase

of div_clk with the ref_clk. Fig. 3 shows an example relationship be-tween the phase error (which relates to the amount of time differencebetween the two rising edges of signals div_clk and ref_clk) and thecontrol code. It is notable that if div_clk leads ref_clk, then the phaseerror polarity is defined as positive. Under such a condition, the DCOsfrequency will be decreased until the phase error eventually becomesnegative. Very often, the frequency of the DCO is now underestimatedand another cycle of catching up is started. In that cycle, the DCOsfrequency is increased gradually until the phase error turns positiveagain. If such an oscillation pattern appears, we can say that the phaseof div_clk is locked to that of ref_clk at least roughly. It can be seenfrom the illustration that the target frequency is approximately locatedat the middle value of the maximal and minimal control codes.

In light of the previous observation, we can quicken thephase-locking process by a forward prediction on the control code.The idea is that the maximal and minimal control codes always occurwhen the polarity changes. To take advantage of this phenomenon,we record one previous control code at all times. Whenever there is apolarity change, the next control code will be set to be the average ofthe current control code and the previous recorded one. Fig. 4 showsan example, the phase polarity changes at point B so that the nextcontrol code, which is #3, will be set to the average of current controlcode, which is #2, and the previous recorded control code, which is#1. The recorded control code is then updated as the control code #3.As we can see, the phase is quickly locked and the fluctuations ofthe phase error and the control code are limited to a narrower range,implying that the resulting ADPLL would have a lower jitter. Then we


Fig. 6. Concept of frequency interpolation.

stop preliminary phase locking to avoid adding extra cycle-to-cyclejitter.

C. Jitter Reduction By a Suppressive FilterAfter the preliminary phase-locking step, the sensitivity of the loop

filter can be lowered to reduce the jitter of the output clock. In otherwords, we do not need to tune the control code every ref_clk cycle butonly tune it in some situations instead. This is done by a so-called sup-pressive digital loop filter. As the name suggests, the aim of the digitalfilter is to further suppress the magnitude of the control code rangeafter the preliminary phase locking. The operation flow is depicted asFig. 5. We use a counting signal, named peat in the figure, to record thenumber of successive lead signal or the number of successive lag signalproduced by the PD when the phase polarity is unchanged. The con-trol code will be changed only in two situations. One is when polaritychanges in two successive phase comparisons, i.e., either from lead tolag, or vice versa, then the control code changes and the threshold re-sets to a preset value. The other is when the counter value is larger thanthe threshold. Then we take two actions whenever the counter valueexceeds the threshold value: 1) we reset the counter value, and 2) wedouble the threshold value. In the other situations, we do nothing to ourcontrol code. In this way, the ADPLL is more stable and will not over-react to spontaneous noise. After the control code has been limited towithin a certain range, we will stop the suppressive filtering process andstart the phase error reduction by the frequency interpolation scheme.

D. Phase Error Reduction By Frequency InterpolationIn general, the ADPLL performs one phase comparison at each rising

edge of ref_clk and the control code is adjusted accordingly. When thedivided number is larger, too many cycles of dco_clk (i.e., the clocksignal at the DCOs output) may have elapsed between two phase com-parisons, thus leading to a large tracking jitter due to phase error ac-cumulation. To alleviate this problem, we need a DCO with an evenhigher resolution. We discovered that this can be achieved by a fre-quency-interpolation scheme, by which the DCO could produce almostany frequency within its output range, or, in some sense, it can possessan almost continuous frequency profile like an analog DCO.

The concept is depicted in Fig. 6, assuming that and are twosuccessive fine control codes and the delay difference between them isregarded as the original minimum resolution of the DCO. Our schemecreates some virtual frequencies between the two frequencies definedby the two successive fine control codes and . In this ex-ample, we aim to create 15 virtual frequency points. Effectively, theresolution of the DCO will be improved by 16 times. These virtual fre-quency points are realized by allowing the DCO to operate alternativelybetween the frequency points defined by and . For example,assume that the frequency of dco_clk is denoted as

when the con-trol code to the DCO is , and

when the control code is .If we wish to generate a clock with frequency of

,

then we can simply alternate the control codes between and .The above discussion can be further generalized to derive the formulaof the frequencies of the 15 virtual frequency points. Let us denote theindex of these virtual frequency points as , ranging from 1 to 15 (from

Fig. 7. Block diagram of frequency interpolation scheme.

Fig. 8. Simulation results of the phase error after locked.

Fig. 9. Die photo of the test chip.

the frequency point towards the frequency point ) as shownin Fig. 6. Then, we can infer the following formula for a virtual fre-quency:

For example, if equals 3, then it becomes

It means that in 3 out of 16 occurrences, the control code of the DCOshould be set to , while it should be set to for the rest 13occurrences. In other words, by changing the probability of the controlcode, we can realize each desired virtual frequency.

The hardware used to implement the above formula is not expensive.Fig. 7 shows the block diagram. To generate a virtual frequency, wesimply take its corresponding alpha value as a threshold. For each clockcycle of dco_clk, we toss a random number in by a modifiedsimple linear feedback shift register (LFSR). If the random number islarger or equal to the target alpha value, then we set the fine controlcode to . Otherwise, we set the fine control code to .

By frequency interpolation, we are now able to produce a dco_clkwith the frequency even closer to a desired frequency so that the phaseerror can be reduced. Still, this technique needs to be applied inside thephase-locking scheme. The suppressive filtering technique used in step3 can be applied again. Instead of adjusting the fine control code as wedid in step 3, we now adjust the alpha value after each phase compar-ison. Since alpha value is an even finer adjustment than the fine controlcode, the phase error as well as the jitter can be reduced furthermore.


TABLE IIPERFORMANCE COMPARISON

IV. EXPERIMENTAL RESULTS

In order to setup the experimental environment of the proposedADPLL, the PD and DCO are precharacterized by postlayout tran-sistor-level simulation to their abstract models. Then, we simulate ourADPLL using postlayout gate-level simulation to save the simulationtime in the design phase. After the design phase is completed, weverify the whole circuit and derive the characteristics from quickSPICE simulation using NanoSim.

Fig. 8 shows the simulated phase error after phase locking of threedifferent configurations. In this simulation, the reference clock is anideal clock source without jitter. The one without frequency interpola-tion, i.e., the one skipping step 4 in our locking procedure, is selectedas the baseline approach for comparison. As we have mentioned, thenumber of virtual frequency points created influences the effective res-olution. In the other two configurations, we create 3 and 15 frequencypoints, respectively, so that the DCOs resolution is thereby improvedto 1/4 and 1/16 of original one equivalently. It can be seen that the phaseerror can be reduced further. Generally speaking, the more the virtualfrequency points are created, the smaller the phase error becomes. Inthis case, where reference clock is 1 MHz and the multiplicative factor is 128, the magnitude of the phase error can be substantially reducedfrom 558 ps to only 21 ps in the 1/16 resolution configuration.

The test chip has been fabricated by Taiwan Semiconductor Manu-facturing Company (TSMC) 0.18-m CMOS technology. Fig. 9 showsthe die photo.

Fig. 10(a) shows the waveform of ref_clk and div_clk after the phaseis locked where the reference clock frequency is 1 MHz and the multi-plicative factor is 600. The div_clk is perfectly locked to the ref_clkin phase where the 180 phase difference is because div_clk is invertedwhen passing through the output pad. Fig. 10(b) shows the jitter per-formance of the ADPLL. In this case, the interpolation-based lockingscheme is adopted to enhance the DCOs resolution by 16 times. The

and the

of the ADPLL are 56 and 7.28 ps, whichare only 3.36% and 0.43%, respectively, of the output clock period.We compare the jitter performance with that of the free-running DCOoperated at 600 MHz. Measurement results show that

and

of the free-running DCO are 56 and 7.06 ps, respectively.This indicates that our jitter performance is very close to that of afree-running DCO, which can be regarded as the lowest jitter one couldpossibly achieve.

Fig. 10. (a) Phase alignment after phase locked. (b) Jitter measurement of theADPLL (@600 MHz).

Fig. 11. Jitter performance under different output frequencies (reference clockfrequency fixed at 1 MHz).

Measurement results of jitter performance under different output fre-quencies are presented in Fig. 11. The reference clock frequency isfixed and the output frequency is changed by tuning the multiplica-tive number . It is found that the interpolation-based locking schemecan not only reduce the phase error but also further reduce the jitter.The

and the

of ADPLL are 72 and 10.1 ps at100 MHz and 68 and 8.81 ps, respectively, in our free-running DCO.The

is small than 0.44%UI even when the output frequencyvaries from 100 to 600 MHz, indicating that the ADPLL can achievelow-jitter performance all over its operation range. Experimental re-sults reveal that the jitter of our ADPLL is very close to that of freerunning DCO no matter what output frequency is synthesized.

Table II shows the characteristics of our ADPLL and its compar-ison with some previous works. All of them can provide a wide range


of multiplicative numbers for frequency multiplication or clock gener-ation. Measurement results show that our ADPLL can correctly func-tion under varying input reference clock frequencies and multiplicativenumbers. In general, our measured jitter is comparable to the analogPLL and clearly outperforms the previous ADPLLs.

V. CONCLUSION

ADPLL has been regarded inferior to its analog counterpart fromthe performance point of view. More recently, ADPLL design has pro-gressed significantly. However, problems such as inadequate DCOsresolution and large jitter remain to be solved. In this brief, we pre-sented an ADPLL with an ultralow-jitter characteristic. There are threemajor contributions we made in this paper. 1) We use a predictivescheme to expedite the preliminary phase-locking procedure. 2) Wefurther successfully reduce the jitter amount by a simple and inexpen-sive suppressive digital loop filter, which incorporates only countingand thresholding to reduce the sensitivity of a PLL during the secondphase-locking stage. 3) We propose to use frequency interpolation tovirtually improve the resolution of a DCO beyond its physical limita-tion. Better jitter performance and phase error can thus be achieved.Measurement results of a test chip show that the root mean square(RMS) jitter is less then 0.44%UI when the output clock frequencyvaries from 100 to 600 MHz. Operated at 600 MHz, the jitter is only7.28 ps, which is only 3% away from that of the free-running DCO(7.06 ps).

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A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

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