A generalized multilevel inverter topology with self...

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 37, NO. 2, MARCH/APRIL 2001 611

A Generalized Multilevel Inverter Topologywith Self Voltage Balancing

Fang Zheng Peng, Senior Member, IEEE

Abstract—Multilevel power converters that provide morethan two levels of voltage to achieve smoother and less distortedac-to-dc, dc-to-ac, and dc-to-dc power conversion, have attractedmany contributors. This paper presents a generalized multi-level inverter (converter) topology with self voltage balancing.The existing multilevel inverters such as diode-clamped andcapacitor-clamped multilevel inverters can be derived from thegeneralized inverter topology. Moreover, the generalized multilevelinverter topology provides a true multilevel structure that canbalance each dc voltage level automatically without any assistancefrom other circuits, thus, in principle, providing a complete andtrue multilevel topology that embraces the existing multilevelinverters. From this generalized multilevel inverter topology,several new multilevel inverter structures can be derived. Someapplication examples of the generalized multilevel converter willbe given.

Index Terms—Diode-clamped multilevel inverter, flying-capac-itor multilevel inverter, multilevel converter, multilevel inverter,power conversion.

I. INTRODUCTION

M ULTILEVEL converters (or inverters) have been usedfor ac-to-dc, ac-to-dc-to-ac, dc-to-ac, and dc-to-dc

power conversion in high-power applications such as utilityand large motor drive applications. Multilevel inverters pro-vide more than two voltage levels. A desired output voltagewaveform can be synthesized from the multiple voltage levelswith less distortion, less switching frequency, higher efficiency,and lower voltage devices. There are three major multileveltopologies: cascaded, diode clamped, and capacitor clamped[1]–[11]. For the number of levels ( ) no greater than three(i.e., ), or some applications such as reactive andharmonic compensation in power systems, these multilevelconverters do not require a separate dc power source to maintaineach voltage level. Instead, each voltage level can be supportedby a capacitor and proper control [6], [7], [11]. However, for

and applications involved in active power transfer, suchas motor drives, these multilevel converters all require eitherisolated dc power sources or a complicated voltage balancingcircuit and control to support and maintain each voltage level[7], [10]. In this aspect, the three existing multilevel converters

Paper IPCSD 00–067, presented at the 2000 Industry Applications SocietyAnnual Meeting, Rome, Italy, October 8–12, and approved for publication inthe IEEE TRANSACTIONS ONINDUSTRY APPLICATIONSby the Industrial PowerConverter Committee of the IEEE Industry Applications Society. Manuscriptsubmitted for review April 1, 2000 and released for publication December 1,2000.

The author is with the Department of Electrical and Computer Engineering,Michigan State University, East Lansing, MI 48826-1226 USA (e-mail:[email protected]).

Publisher Item Identifier S 0093-9994(01)02100-4.

are neither operable nor complete for real (active) powerconversion because they all depend on outside circuits forvoltage balancing.

This paper presents a generalized multilevel invertertopology. The generalized multilevel inverter topology can bal-ance each voltage level by itself regardless of inverter controland load characteristics. The existing multilevel inverters suchas diode-clamped and capacitor-clamped multilevel inverterscan be derived from this generalized inverter topology. More-over, the generalized multilevel inverter topology provides atrue multilevel structure that can balance each dc voltage levelautomatically at any number of levels regardless of active orreactive power conversion without any assistance from othercircuits, thus in principle providing a complete multileveltopology that embraces the existing multilevel inverters. Fromthis generalized multilevel inverter topology, several newmultilevel inverter structures can be derived. In this paper, thedetailed structures and operating principle of the generalizedmultilevel converter topology are presented. Analysis, discus-sion, and some application examples are briefed.

II. GENERALIZED MULTILEVEL INVERTER AND

OPERATING PRINCIPLE

Fig. 1 shows the generalized multilevel inverter topology perphase leg, where each switching device, diode, or capacitor’svoltage is 1 V , i.e., ( ) of the dc-link voltage. Any in-verter with any number of levels including the conventional two-level inverter, can be obtained from this generalized topology asshown in the figure. For example, the two-level inverter phaseleg can be obtained by cutting off at the “2-level line,” three-level inverter leg by cutting off at the “3-level line,” and so on,as shown in Fig. 1. It is evident that an-level inverter can beconstructed by the basic cell as shown in the inset of Fig. 1. Thegeneralized -level phase leg (Fig. 1) is a horizontal pyramidof the basic cells. Since the basic cell is a two-level phase leg,this generalized multilevel inverter (Fig. 1) is called the P2 mul-tilevel inverter. To explain the operating principle and analyzethe circuit, the five-level circuit is used hereafter. Fig. 2 showsthe generalized five-level inverter phase leg (or five-level P2 in-verter phase leg).

In Fig. 2, switches Sp1–Sp4 and Sn1–Sn4 and diodesDp1–Dp4 and Dn1–Dn4 shown in bold lines are the maindevices to produce desired voltage waveforms. The rest ofthe switches and diodes are for clamping and balancing thecapacitors’ voltages, i.e., voltage levels. Each component’svoltage stress is 1 V. All voltage levels are self-balancedthrough clamping switches and clamping diodes. The operationcan be explained as in Figs. 3–5. The circled (both solid and

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612 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 37, NO. 2, MARCH/APRIL 2001

Fig. 1. Generalized multilevel inverter topology (M -level, one phase leg). Inset: basic P2 cell.

Fig. 2. Five-level P2 inverter phase leg.

dashed lines) devices indicate on-state devices and currentpath. The uncircled devices are off-state devices. In addition,the solid-line circled devices are the on-state devices necessaryto produce the desired voltage level, whereas the dashed-line

circled ones are the on-state devices to keep their capacitors’voltages balanced, i.e., for balancing and clamping purpose. Forexample, in Fig. 3, switches Sn1–Sn4 are gated on to producezero (0) voltage (i.e., , the zero potential is referenced tothe negative rail of the dc bus). The dashed-line circled devicesare gated on to clamp and balance voltages. The switches Sc1,Sc5, and Sc11 are gated on so that the capacitors C1, C3, C6,and C10 are connected in parallel to balance their charges (i.e.,

). Similarly, the switches Sc3 andSc9 are gated on so that the capacitors C2, C5, and C9 arecharge-balanced (i.e., ). And Sc7 is gatedon letting C4 and C8 be charge-balanced (i.e., ).Fig. 4 shows one set of switching states for producingV . There are three other alternative switching states as shownin Table I to produce V and balance capacitors’charges. Fig. 5 shows one example of the alternatives. InFig. 4, , ,and . In Fig. 5, ,

, and . In thisway, all capacitors’ voltage can be balanced.

From the above explanation and with reference to Fig. 5, onecan infer the following switching rules: 1) each switch pole isan independent switching unit; 2) any adjacent two switches of


PENG: MULTILEVEL INVERTER TOPOLOGY WITH SELF VOLTAGE BALANCING 613

Fig. 3. Switching states to producev = 0 and to clamp and balancecapacitors’ voltages.

Fig. 4. Switching states to producev = 1 V and to clamp and balancecapacitors’ voltages.

each switch pole are complementary, (i.e., if one is on the otheris off and vice versa); 3) if any switch’s state is determined orknown then the rest switches of the pole are automatically deter-mined because of the complementary rule. Table I summarizesthe switching states to generate 0-, 1-, 2-, 3-, and 4-Vvoltagelevels. Only Sp1-Sp4’s states are shown because the comple-mentary rule uniquely determines all remaining switches’ states.

Fig. 6 shows simulation results of a three phase five-levelP2 inverter (three Fig. 2 phase legs connected together witha shared dc bus) driving an induction motor. I(Load_a),I(Load_b), and I(Load_c) are the motor currents, Vab is theinverter output phase “a” to phase “b” voltage, V1–V5 are thefive voltage levels, I(PhaseA.IGBT_Sp1) is the current of phase“a” main device Sp1, and I(PhaseA.IGBT_Sc1) is the current ofphase “a“ clamping device Sc1. The waveforms clearly showedturn-on transient pulse current in Sc1 and demonstrated thatall the voltage levels are well balanced. As a well-known fact,the existing diode-clamped and capacitor-clamped multilevelinverters with more than three levels have no ability to balanceeach voltage level themselves for active power conversion.

Fig. 5. Alternative switching states to producev = 1 V and toclamp/balance capacitors’ voltages.

Figs. 7–10 show some examples of existing multilevelinverters that can be deduced from the generalized multilevelinverter. Fig. 7 shows the diode- and capacitor-clampedmultilevel inverter that is derived from Fig. 2 by eliminatingall clamping switches. Further eliminating the clampingswitches and diodes of Fig. 2 yields the capacitor-clamped(or flying capacitor) multilevel inverter of Fig. 8. Similarly, adiode-clamped multilevel inverter, Fig. 9, can be derived fromFig. 2 by eliminating the clamping switches and capacitors.Further, another diode-clamped multilevel inverter as shown inFig. 10 can be obtained by swapping diode clamping paths.

Using the same pyramid structure of the P2 inverter, severalother new configurations can be derived from the generalizedmultilevel inverter topology. For example, a P3 inverter can beconfigured using the three-level basic cells. More specifically,Fig. 11 shows a generalized multilevel inverter that is based ona three-level diode-clamped phase leg, thus being called P3Dmultilevel inverter (or converter). Similarly, Fig. 12 shows thegeneralized P3C multilevel converter, which is based on a three-level capacitor-clamped phase leg. Again in Figs. 11 and 12,each device’s voltage stress is one voltage level. Compared withthe P2 multilevel inverter, however, the P3D and P3C multilevelinverters require fewer clamping switches, diodes, and capaci-tors for the same number of levels. Some analysis and compar-ison are given in the following section. Other examples includethe P2 H-bridge inverter that is configured with two P2 cells andthe P3 H-bridge inverter with two P3 cells. A cascade multilevelinverter can be further configured using the P2 H-bridge or P3H-bridge or a combination of P2 H-bridge and P3 H-bridge in-verter cells [6].

III. A NALYSIS, DISCUSSION, AND APPLICATION EXAMPLES

As described in the previous section, all capacitors’ voltageis clamped (equalized) as the multilevel converter switchesfrom one state to another. At each state change, the multi-level converter connects two different groups of capacitors



TABLE ISWITCHING STATES TO PRODUCEv = 0, 1-, 2-, 3–,AND 4-V VOLTAGE LEVELS

Fig. 6. Simulation results showing balanced voltage levels.

together through switches and/or diodes. Fig. 13(a) shows acircuit illustrating this transition. If the two capacitors have avoltage difference , power loss will occur at each transition

when the switch closes. To investigate such power loss, aMOSFET based multilevel converter is used as an example.For a MOSFET switch, it can be equivalently expressed as a



Fig.7. Diode- and capacitor-clamped multilevel inverter deduced from theFig. 2 generalized topology without clamping switches.

Fig. 8. Capacitor-clamped (or flying capacitor) multilevel inverter furtherdeduced from the Fig. 2 generalized topology without clamping switches anddiodes.

resistance when turned on [Fig. 13(b)]. The energy loss can beexpressed as the following at each transition:

(1)

which is proportional to the voltage difference and capacitancebut independent of the resistance. The resistance only affects theinitial charging/discharging current and duration [Fig. 13(c)],but has no effect on the loss. The voltage difference is causedby charging or discharging current during each switching state,which can be expressed as

(2)

Fig. 9. Diode-clamped multilevel inverter I further deduced from the Fig. 2generalized topology without clamping switches and capacitors.

Fig. 10. Diode-clamped multilevel inverter II further deduced from the Fig. 2generalized topology without clamping switches and capacitors and withswapped diode clamping paths.

where is the average charging or discharging current duringone switching cycle and is the switching frequency. From(1) and (2), the energy loss at each switching-over instant canbe rewritten as (3) and the power loss is thus expressed as (4)

(3)

(4)

Therefore, the power loss is inversely proportional to the ca-pacitance and switching frequency. In the simulation of Fig. 6,it was confirmed that the power loss generated is less than 1%of the load power at fundamental frequency switching. Using



Fig. 11. Generalized P3D multilevel inverter.

Fig. 12. Generalized P3C multilevel inverter.

higher switching frequency and redundant switching states canreduce this power loss dramatically.

Fig. 13. Equivalent circuits and charging/discharging current waveformsduring voltage equalization.

In the P2 -level converter, the number of the requiredswitching devices/diodes is and the number ofthe required capacitors is . These numbers canbe easily obtained from the pyramid structure. Similarly, in theP3D -level converter the required switching devices/diodesis and the number of the required capacitors orclamping diodes is . In the P3C M-level converterthe required switching devices/diodes is againand the number of the required capacitors is .Compared with the P2 multi-level converter, the P3D andP3C multilevel converters advantageously use less switchingdevices, diodes, and capacitors. For example, the P2 five-levelinverter needs 20 switching devices/diodes and ten capacitorsper phase leg, whereas the P3D five-level inverter only uses12 switching devices/diodes and six capacitors. It is possibleto construct a multilevel inverter using basic cells with morethan three levels. However, voltage balancing becomes an issueagain.

The immediate use of the generalized multilevel convertertopology may include switched-capacitor dc-to-dc convertersand voltage multipliers [12]–[16]. For these applications, thecomponent count is actually minimal and less than traditionalones. In addition, device stresses are minimized because ofthe auto-voltage balancing ability. Fig. 14 shows one examplefor such applications with bidirectional power flow. WhenFig. 14 is used for bidirectional dc/dc conversion, the inputinductor can be minimized or even eliminated for voltagemultipliers. Another interesting and promising application isshown in Fig. 15 for bidirectional dc-to-dc conversion for thedual battery system of automobiles [17], [18]. In this applica-tion, low-voltage (30 V) low-cost MOSFETs can be used toachieve high-efficiency (99%), compact, and magneticlesspower conversion. Therefore, in these niched applications,the generalized multilevel converter can: 1) use low-voltageMOSFETs; 2) minimize or eliminate bulky magnetics; and3) produce less distortion and virtually zero electromagnetic



Fig. 14. Generalized P2 five-level converter for switched-capacitor dc–dc converter and voltage multiplier applications with bidirectional power flow.

(a)

(b)

Fig. 15. (a) Four-level P2 converter for dual battery system of automobiles and(b) its prototype photograph.

interference (EMI) at output. A 2-kW prototype has been builtand tested. Due to page limitations, detailed experimental setupinformation and results cannot be included in this paper. Ina follow-up paper, some more application examples will beinvestigated and experimental results will be reported.

IV. CONCLUSIONS

This paper has presented a generalized multilevel invertertopology. The existing multilevel inverters can be derivedfrom this generalized structure. It has been demonstrated thatthe generalized multilevel inverter has self-voltage-balancingability that the existing multilevel inverters do not have for thenumber of levels greater than three (i.e., ) and for realpower conversion. Although the generalized multilevel inverterneeds a lot of clamping switches, diodes, and capacitors, inprinciple, it is a true and complete multilevel inverter (orconverter). In addition, the generalized topology has led tosome new multilevel structures such as P3D and P3C. In someapplications such as capacitor-switched power conversion,voltage multiplier, and bidirectional dc/dc conversion, thegeneralized multilevel converter topology has a niche for im-plementing magneticsless, compact, high-efficiency, zero-EMI,and low-cost power conversion. In a follow-up paper, someapplication examples will be investigated and experimentalresults of a P2 four-level dc-to-dc converter for the dual batterysystem of automobiles will be reported.

REFERENCES

[1] N. S. Choi, G. C. Cho, and G. H. Cho, “Modeling and analysis of a staticvar compensator using multilevel voltage source inverter,” inConf. Rec.IEEE-IAS Annu. Meeting, 1993, pp. 901–908.

[2] Y. S. Kim, B. S. Seo, and D. S. Hyun, “A new N-level high voltageinversion system,” inProc. IEEE IECON’93, 1993, pp. 1252–1257.

[3] T. A. Meynard and H. Forch, “Multilevel conversion: High voltagechopper and voltage-source inverters,” inProc. IEEE PESC’92, 1992,pp. 397–403.

[4] X. Yuan, I. Barbi, and H. Stemmler, “A New diode clamping multilevelinverter,” inProc. IEEE APEC’99, 1999, pp. 494–501.

[5] J. S. Lai and F. Z. Peng, “Multilevel converters – A new breed of powerconverters,”IEEE Trans. Ind. Applicat., vol. 32, pp. 509–517, May/June1996.

[6] F. Z. Peng, J. S. Lai, J. W. McKeever, and J. VanCoevering, “A multi-level voltage-source inverter with separate DC sources for static var gen-eration,”IEEE Trans. Ind. Applicat., vol. 32, pp. 1130–1138, Sept./Oct.1996.



[7] F. Z. Peng and J. S. Lai, “A static var generator using a staircase wave-form multilevel voltage-source converter,” inUSA Official Proc. 7th Int.Power Quality Conference, Dallas/Ft. Worth, TX, Sept. 17–22, 1994, pp.58–66.

[8] C. Hochgraf, R. Lasseter, D. Divan, and T. A. Lipo, “Comparison ofmultilevel inverters for static var compensation,” inConf. Rec. IEEE-IASAnnu. Meeting, 1994, pp. 921–928.

[9] F. Z. Peng, J. S. Lai, J. McKeever, and J. Vancoevering, “A multilevelvoltage-source converter system with balanced DC voltages,” inProc.IEEE PESC’95, Atlanta, GA, 1995, pp. 1144–1150.

[10] Menzies, P. Steimer, and J. K. Steike, “Five level GTO inverters forlarge induction motor drives,” inConf. Rec. IEEE-IAS Annu. Meeting,1993, pp. 595–601.

[11] X. Yuan, H. Stemmler, and I. Barbi, “Investigation of the clampingvoltage self-balancing of the three-level capacitor clamping inverter,”in Proc. IEEE PESC’99, 1999, pp. 1059–1064.

[12] J. S. Brugler, “Theoretical performance of voltage multiplier circuits,”IEEE J. Solid-State Circuits, vol. 6, pp. 132–135, June 1971.

[13] P. M. Lin and L. O. Chua, “Topological generation and analysis ofvoltage multiplier circuits,”IEEE Trans. Circuits Syst., vol. CAS-24,pp. 517–530, Oct. 1977.

[14] L. Malesani and R. Piovan, “Theoretical performance of capacitor-diodevoltage multiplier fed by a current source,”IEEE Trans. Power Elec-tron., vol. 8, pp. 147–155, Apr. 1993.

[15] A. Lamantia, P. G. Maranesi, and L. Radrizzani, “Smaill-signal model ofthe Cockcroft-Walton voltage multiplier,”IEEE Trans. Power Electron.,vol. 9, pp. 18–25, Jan. 1994.

[16] K. D. T. Ngo and R. Webster, “Steady-state analysis and design of aswitched-capacitor DC-DC converter,” inProc. IEEE PESC’92, 1992,pp. 378–385.

[17] J. G. Kassakian, “Automotive electrical systems—The power elec-tronics market of the future,” inProc. IEEE APEC, 2000, pp. 1–7.

[18] J. M. Miller and A. R. Gale, “Hybrid electric vehicle success will dependon low cost, efficient power electronics systems,”PCIM, vol. 23, no. 11,pp. 23–38, Nov. 1997.

Fang Zheng Peng(M’93–SM’96) received the B.S.degree from Wuhan University, Wuhan, China, andthe M.S. and Ph.D. degrees from Nagaoka Univer-sity of Technology, Japan, in 1983, 1987, and 1990,respectively, all in electrical engineering.

From 1990 to 1992, he was a Research Scientistwith Toyo Electric Manufacturing Company, Ltd.,where he was engaged in research and developmentof active power filters, flexible ac transmission sys-tems (FACTS) applications, and motor drives. From1992 to 1994, he was a Research Assistant Professor

at Tokyo Institute of Technology, where he initiated a multilevel inverterprogram for FACTS applications and a speed-sensorless vector control project.From 1994 to 1997, he was a Research Assistant Professor at the University ofTennessee, working for Oak Ridge National Laboratory (ORNL). From 1997to 2000, he was a Senior Staff Member at ORNL and Lead (principal) Scientistof the Power Electronics and Electric Machinery Research Center. In 2000, hejoined Michigan State University, East Lansing, as an Associate Professor.

Dr. Peng has received numerous awards, including the 1996 First Prize PaperAward and the 1995 Second Prize Paper Award from the Industrial Power Con-verter Committee at the IEEE Industry Applications Society Annual Meeting;the 1996 Advanced Technology Award of the Inventors Clubs of America, Inc.,the International Hall of Fame; the 1991 First Prize Paper Award from the IEEETRANSACTIONS ONINDUSTRY APPLICATIONs; the 1990 Best Paper Award fromtheTransactions of the Institute of Electrical Engineers of Japan; and the Pro-motion Award of the Electrical Academy. He has been an Associate Editor ofthe IEEE TRANSACTIONS ONPOWER ELECTRONICSsince 1997.


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