A Class-D CMOS DCO with an on-chip LDOLuca Fanori1,2, Thomas Mattsson3, and Pietro Andreani1,3

1Lund University, Sweden, 2now in Marvell Italy, Pavia, Italy 3Ericsson Modem, Lund, Swedenlucaf@marvell.com, thomas.mattsson@ericsson.com, pietro.andreani@eit.lth.se

Abstract—This paper presents the co-design of a class-Ddigitally-controlled oscillator (DCO) and a low-dropout voltageregulator (LDO) generating the supply voltage for the DCO.Despite the high intrinsic supply pushing of the class-D oscillatortopology, the LDO noise has only a very marginal impact on theDCO phase noise.

The class-D DCO and LDO have been integrated in a 65 nmCMOS process without any thick top metal layer. The oscillationfrequency is tunable between 3.0 GHz and 4.3 GHz, for a tuningrange of 36%, with a fine frequency step below 3 kHz and a finefrequency range of 10 MHz (both measured at 3 GHz).

Drawing 9.0 mA from 0.4 V (corresponding to an unregulatedsupply voltage of 0.6 V), the phase noise is -145.5 dBc/Hz at a10 MHz offset from a 3.0 GHz carrier. The resulting FoM is189.5 dBc/Hz, and varies less than 1 dB across the tuning range.The FoM increases to above 190 dBc/Hz when the regulatedsupply voltage is 0.5 V.

Index Terms—VCO, DCO, class-D, low phase noise, highefficiency, CMOS, low-voltage, LDO, voltage regulator.

I. INTRODUCTION

Despite the apparent simplicity, designing integratedvoltage-controlled-oscillators (VCOs) with a wide tuningrange and a low phase noise remains very challenging, es-pecially if a high power efficiency is required. The steadyreduction of the supply voltage Vdd in nanometer CMOSprocesses certainly benefits power saving in digital circuits,but makes it the more difficult for a VCO to achieve the phasenoise performance required by cellular applications, since thisis naturally limited by Vdd.

Recently, we have proposed a class-D oscillator topology[1] that is capable of combining low phase noise, low Vdd,and high power efficiency, close to 90%. This is made possibleby the voltage-mode operation of the class-D oscillator, wherethe bias-current limitation typical of class-B/C oscillators is re-moved, and the cross-coupled transistor pair size is as wide asallowed by the technology and by the required oscillation fre-quency and tuning range. In the limit of ideal MOS switches,the peak-to-peak single-ended class-D oscillation amplitude isas high as 3Vdd, as opposed to a maximum of 2Vdd in class-B/C oscillators. The class-D current consumption, on the otherhand, is proportional to Vdd and, in a less straightforward waythan in the case of class-B/C oscillators, to tank losses [1].

The main drawback of the class-D architecture is the highsupply pushing [1], which has two consequences: first, thelow-frequency noise from the LDO (necessary in real-lifeapplications to isolate the VCO from the external powersupply) is up-converted into phase noise in an amount directlyproportional to pushing; and secondly, the ripple on the powersupply, unavoidable when the latter is generated by a DC-DC converter, gives rise to spectral spurs through the samemechanism.

+ Vout -

M2M1

Vdd,ext

Coarse & MediumTuning

b0

b12

Vref RLP

CLP

FineTuning

b0

b10

Vdd

CCT

Ltail

Ptop-

+

Vdd,1.2V

Fig. 1. Schematic view of the class-D DCO with on-chip LDO.

An additional issue in class-D oscillators is the relativelyhigh 1/f3 phase noise corner [1], whose origin, too, can betraced back to the high supply pushing [1].

This work shows that it is indeed possible to design a class-D VCO-LDO combo (or, as in the case at hand, its digitalequivalent, using a DCO) that delivers a very low phase noisefrom a very low Vdd, notwithstanding the high native pushingof the class-D topology. This is achieved primarily througha dedicated LDO design, with the further aid of an inductivedegeneration of the core MOS devices in the oscillator [2] [1].The latter technique is also instrumental to reduce the 1/f3

phase noise to levels typical of class-B/C oscillators.

II. LDO DESIGN

The schematic view of the class-D DCO with LDO isshown in Fig. 1, where we have indicated with Vdd the LDO-generated voltage at the center-tap of the LC-tank inductor,and with Vdd,ext the external supply voltage. The value of Vddtracks that of a reference voltage Vref , typically generatedby a bandgap reference circuit. The LDO is based on itsmost common design, where a large PMOS transistor Ptop

delivering the current needed by the oscillator constitutesthe output stage of a low-frequency loop closed around anoperational amplifier (opamp, implemented here as a single-stage differential pair, with a gain of 25 dB and a current

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PN with wide-band LDOPN with narrow-band LDOPN with noise-less LDO

Vdd = 0.4V, fosc = 4.3GHz

-80

Fig. 2. Phase noise simulations for the DCO-LDO combo.

consumption of 0.5 mA from 1.2 V), such that Vdd ≈ Vreffollows.

To neutralize the phase noise contribution of the opamp (andpossibly of the bandgap circuit generating Vref ) due to thepushing, a low-pass filter is interposed at the opamp output,made of capacitance CLP and resistance RLP . Outside thefilter bandwidth fLP , the LDO noise reduces to that from Ptop,whose low-frequency noise must be low enough to avoid anysubstantial phase noise degradation, while its high-frequencynoise is filtered by capacitance CCT . Within fLP , the low-frequency LDO noise is increased by the presence of a largeRLP , which imposes to choose fLP lower than the bandwidthof the phase-locked loop (PLL) where the DCO is going towork − in this way, the PLL loop gain effectively attenuatesall LDO noise up to (and beyond) fLP . A low fLP , however,conflicts with the desire of a fast settling PLL. For this reason,a switch in parallel to RLP enables a much higher fLP fora fast start-up, during which a high phase noise is of noconsequence. Fig. 2 shows phase noise simulations for thecircuit in Fig. 1, for an oscillation frequency of 4.3 GHz anda Vdd of 0.4 V, while Vdd,ext is 0.6 V. Three situations areconsidered: a low fLP ≈ 2 kHz, a high fLP ≈ 2 MHz,and a noise-less LDO acting as a reference. The phase noisedeterioration when fLP = 2 kHz is contained to less than1 dB in the 1/f2 region, and to less than 3 dB in the 1/f3

region, while the improvement with respect to fLP = 2 MHzis very large. It should also be remarked that these simulationsaddress the worst-case scenario, when the DCO is working atits highest frequency and supply pushing is highest [1]; at thelowest frequency of 3.0 GHz, on the other hand, the phasenoise for fLP = 2 kHz overlaps the reference curve.

A second crucial task of CLP and RLP is to enable a pathfrom Ptop source to gate, improving the out-band LDO PSRR,whose simulated results are shown in Fig. 3 for both narrowand wide loop bandwidth. Here, the CLP -RLP filter acts as ahigh-pass, removing supply noise (and spurs) above fLP . Theeffectiveness of this solution depends on how closely the Ptop

gate follows the source [3], which means that the parasiticcapacitance to ground at the Ptop gate must be kept muchsmaller than CLP .

Finally, another key detail for noise cancellation to workproperly is that Ptop source and bulk be connected together;

Frequency (Hz)

40

35

30

25

20

15

45

1k 10k

50

PSRR with wide-band LDOPSRR with narrow-band LDO

VCT = 0.4V, fosc = 4.3GHz

100k 1M 10M 100M 1G

PS

RR

(dB

)

Fig. 3. Simulate PSRR for both narrow and wide LDO bandwidth.

in fact, if the bulk does not follow the source, noise may evenbe boosted (rather than strongly attenuated) by the back-gatetransconductance of Ptop.

III. DCO DESIGN

The DCO tank employs a 0.9 nH 8-shape inductor [4][5], which both rejects any common-mode magnetic fieldimpinging on it, and generates a magnetic field that vanishesfar from the coil itself, minimizing the so-called magneticpulling on and from the DCO. Due to the absence of thickmetal layers, the inductor quality factor Q at 4 GHz is limitedto approximately 14, estimated from post-layout simulationsfitting the measured power consumption.

The oscillation frequency is digitally tunable between3.0 GHz and 4.3 GHz via a 7-bit coarse-tuning metal-oxide-metal (MOM) capacitor array, further refined by a 6-bitmedium-tuning MOM capacitors array, having a frequencystep lower than 500 KHz and a full range spanning threecoarse tuning steps. Finally, fine tuning is performed byexploiting the capacitive divider principle [6] shown in Fig. 4:a variation of the tunable capacitance ∆Ctune is seen as amuch smaller equivalent variation ∆Ceq by the LC tank, with∆Ceq ≈ (C2/(C1 + C2))

2∆Ctune where C1 and C2 are

is Fig. 4(a). As an example, if C2 ≈ 1/13C1 (as in thepresent design, where C1 = 1 pF and C2 = 80 fF), ∆Ceq isapproximately 170 times smaller than ∆Ctune, and a readilyfeasible ∆Ctune of 10 fF corresponds to a ∆Ceq of 60 aF,which would be problematic to achieve in a direct way.

row

dec

oder

b4b6 b5

column decoder

b10

b9

b7

b8

P M

Gnd Vdd, var

Connected to Vdd, var

Connected to Gnd

Connected to VDAC

DA

C

b0

b3

C1

2C22C2

Fine tuning capacitor array

Ctank

Ltank

RbRb

Vvar

CtuneP M

(a) (b)

Fig. 4. (a) Capacitive divider scheme; (b) Fine-tuning varactor array.

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Fig. 5. Chip photograph.

The fine-tuning capacitor bank, shown in Fig. 4(b), isborrowed from [7]: the 7 MSBs of the 11 fine-tuning bitsimplement a thermometric control of an 8×16 varactor array,where each varactor is biased to either Vdd,var or ground;the 4 LSBs, on the other hand, feed a resistive-ladder DAC,which provides 16 voltage levels between Vdd,var and groundto bias an additional ultra-fine-tuning varactor. Finally, the gateterminal of all varactors is biased at a voltage Vvar through alarge resistor Rb (Fig. 4(a)), where Vvar is half way betweenVdd,var and ground in order to maximize the varactor tuningrange. In this work, Vdd,var was set to 1.2 V.

The two DCO core transistors M1 and M2 are implementedusing low-threshold-voltage NMOS devices to maximize theirperformance as switches, with minimum length of 60 nm andwidth of 500µm, large enough to sustain a proper class-Doperation without excessively affecting the DCO tuning range.

The common source of M1 and M2 is degenerated by atail inductance of 250 pH with Q around 6, which resonateswith the parasitic capacitance in parallel to it at approximatelytwice the oscillation frequency [2], creating an LC tail filter.This is advantageous in terms of a reduced supply pushingand a reduced upconversion of 1/f noise from M1 and M2[1, 2]. While this technique had a limited success in theprototypes presented in [1], better results are obtained in thiswork, most likely due to the availability of more accurateprocess models to characterize the tail inductor. Although theoscillation frequency varies by a relatively large amount, itwas also found that resonance tuning of the tail filter was notnecessary.

IV. MEASUREMENT RESULTS

The class-D DCO with fully integrated LDO was fabricatedin a standard 65 nm CMOS process and tested. Fig. 5 dis-plays the photograph of the chip, which occupies an area of0.35 mm2. This includes a CCT of 250 pF (needed to absorbthe large second-order current harmonic of class-D oscillators),a CLP of 140 pF, both using a parallel combination of MOMand MOS capacitors, resulting in capacity density around 15-20 fF/µm2, and transistor Ptop, which is 10 mm wide and 1µmlong. Both MOS capacitors and Ptop are implemented witha high-voltage double-gate device to avoid the gate leakagecurrent, while RLP = 600 kΩ is implemented with a high-resistivity polysilicon layer.

The DCO is tunable between 3.0 GHz and 4.3 GHz, for atuning range of approximately 36%. The fine tuning covers a

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PN @ 3.0GHz, IDC = 9.0mAPN @ 3.6GHz, IDC = 7.5mAPN @ 4.3GHz, IDC = 7.0mA

Vdd = 0.4V, FoM 189/189.5dBc/Hz

-140.5dBc/Hz

-145.5dBc/Hz

1/f3 corner frequency

-143.5dBc/Hz

Fig. 6. Phase noise measurements at minimum, middle and maximumoscillation frequencies with Vdd = 0.4V .

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Vdd = 0.4V, fosc = 4.3GHz

-80

10dB

6dB

Fig. 7. Phase noise measurements with wide-band and narrow-band LDO atmaximum oscillation frequency.

range of 5.8 MHz at 3 GHz, which increases to 16.0 MHz at4.3 GHz, resulting in a average frequency resolution of 2.4 kHzand 8.6 kHz, respectively.

Since the maximum voltage excursion between gate andsource/drain of M1/M2 is 1.2 V and the maximum oscillationamplitude of the class-D DCO is approximately 3Vdd, thenominal value of Vdd is 0.4 V. This limitation is not relaxedby the presence of the tail inductor, since the maximumvoltage excursion between gate and source/drain of M1/M2is only very slightly diminished by it. Nevertheless, the DCOperformance is assessed also for Vdd = 0.5 V, as this wouldprobably still be acceptable in terms of circuit lifetime. In bothcases, Vdd,ext is kept 200 mV above Vdd, which ensures thatPtop is working in the active region.

The class-D DCO-LDO combo yields a very good phasenoise performance already for Vdd = 0.4 V, as shown in Fig. 6for minimum, middle, and maximum oscillation frequencies,especially considering that the Q of the overall LC had anestimated value of 11 at 4 GHz. The 1/f2 phase noise, mea-sured at 10 MHz from the carrier, is -145.5 dBc/Hz at 3.0 GHzand -140.5 dBc/Hz at 4.3 GHz, while the current consumptiondecreases from 9 mA at 3.0 GHz to 7 mA at 4.3 GHz. Theresulting phase-noise figure-of-merit (FoM, calculated fromVdd rather than Vdd,ext, to enable a fair comparison with mostVCO/DCO designs reported in the literature) varies between189.0 dBc/Hz and 189.5 dBc/Hz across the tuning range. Fur-thermore, the 1/f3 phase noise corner is at approximately

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TABLE ICOMPARISON WITH STATE-OF-THE-ART CELLULAR TRANSMITTER VCOS/DCOS HAVING A TUNING RANGE OF AT LEAST 15%.

Vdd (V) Tech(nm)

Frequency(GHz)

PN(dBc/Hz)

DCO fine-tuningrange (MHz)

PDC

(mW)FoM

(dBc/Hz)

Nakamura, ESSCIRC ’12 [8] 2.8 65 3.1-4.1 (28%) -151@10MHz from 3.6GHz 0.1, LSB = 0.6 kHz 56.7 185

Liscidini, ISSCC ’12 [9] 1.5 55 6.5-9.0 (33%) -135@2MHz from 3.9GHz(a) 8-20, LSB = 2-5 kHz 36 185

Staszewski, JSSC ’05 [10] 1.4 90 3.2-4.1 (25%) -165@20MHz from 915MHz(b) 0.8, LSB = 12 kHz(c) 25.2 183

Chen, A-SSCC ’07 [6] 1.4 90 6.4-9.2 (36%) -126@1MHz from 7.8GHz 0.6, LSB = 0.8 kHz 19.2 183

Babaie, ISSCC ’13 [11] 1.25 65 2.9-3.8 (25%) -142@3MHz from 3.7GHz analog tuning 15 192

Zhuang, A-SSCC’07 [12] 1.2 90 3.0-3.6(18%) -118@1MHz from 3.3GHz 10, LSB = 5 kHz 2.4 185

Li, JSSC ’12 [13] 0.6 65 2.5-5.6 (76%) -157@20MHz from 3.6GHz analog tuning 13.5 188/192

Fanori, ISSCC ’14 [14] 0.4 65 2.4-5.3 (75%) -149@10MHz from 2.4GHz analog tuning 6 187/189

This work0.4

65 3.0-4.3 (36%)

-140.5/-145.5@10MHz from3.0/4.3GHz 5.8-16, LSB = 2.4-8.6 kHz

3.6-2.8 189

0.5 -146.5/-149.5@10MHz from3.0/4.3GHz

6.5-4.0 190/191

(a): After division by 2; (b): After division by 4; (c): Without dithering

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PN @ 3.0GHz, IDC = 13mAPN @ 3.6GHz, IDC = 11mAPN @ 4.3GHz, IDC = 8mA

Vdd = 0.5V, FoM 190/191dBc/Hz

-144dBc/Hz

-149.5dBc/Hz

1/f3 corner frequency

-146.5dBc/Hz

Fig. 8. Phase noise measurements at minimum, middle and maximumoscillation frequencies with Vdd = 0.5V .

400-500 kHz and is comparable to what may be expectedfrom class-B/C VCOs (see e.g. [15]). The effectiveness ofthe low-pass filter in the LDO is shown by the phase noisemeasurements of Fig. 7, where it is clear that a narrow-bandLDO greatly improves the phase noise spectrum.

The phase noise measurements for Vdd = 0.5 V are shownin Fig. 8, where an improvement of 3 to 4 dB is noticed,compared to the corresponding curves in Fig. 6. Of course,current consumption increases as well, but the higher oscilla-tion amplitude allowed by the higher supply voltage results inNMOS switches with a lower channel resistance, improvingthe net class-D DCO performance. As a consequence, theFoM increases by approximately 1 dB, for a value of 190-191 dBc/Hz across the tuning range.

Table I summarizes the class-D DCO performance, com-paring it with several published VCOs/DCOs (most of whichdo not use an an-chip LDO) having a tuning range of at least15% and meeting GSM transmitter specifications.

V. CONCLUSIONS

This paper has presented a class-D DCO with a fully inte-grated LDO, where the noise generated by the LDO does notdeteriorate the phase noise of the DCO. The low phase noisemeasured on a 65 nm CMOS prototype shows that the highly

efficient class-D oscillator topology can be adopted in cellularcommunications, while an unregulated power supply of 600-700 mV is already sufficient for an optimal performance.

VI. ACKNOWLEDGMENTSThe authors thank STMicroelectronics for the generous silicon donation.This work was supported by the European Project Marie Curie FP7-

PEOPLE-2009-IAPP project number n 251399, and by the Swedish Foun-dation for Strategic Research (SSF) under the DARE project.

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