A 4×32-Channel Neural Recording System for Deep...

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.1, FEBRUARY, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2017.17.1.129 ISSN(Online) 2233-4866

Manuscript received Mar. 27, 2016; accepted Nov. 1, 2016 1 Department of Electrical and Computer Engineering, Seoul National University, Seoul, 08826, Korea 2 System LSI, Semiconductor Business Group, Samsung Electronics Co. Ltd., Hwaseong, 18448, Korea 3 Department of Neurosurgery, Yonsei University College of Medicine, Seoul, 03722, Korea E-mail : [email protected]

A 4×32-Channel Neural Recording System for Deep Brain Stimulation Systems

Susie Kim1, Seung-In Na2, Youngtae Yang1, Hyunjong Kim1, Taehoon Kim1, Jun Soo Cho1,

Jinhyung Kim, Jin Woo Chang3, and Suhwan Kim1,*

Abstract—In this paper, a 4×32-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in 0.18 mm CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is 10.2 mVrms. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat. Index Terms—Analog front-end (AFE), analog-to-digital converter (ADC), action potential (AP), 4×32-channel, neural recording system

I. INTRODUCTION

It is now common for neuroscientists and clinicians to observe the behavior of diverse signals as part of their research, and this has motivated the development of low-noise, low-power neural recording systems [1-4]. Since most neurological and behavioral disorders can be observed by brain activity, brain computer interfaces (BCIs) have been developed for the acquisition of neural signals by electroencephalography (EEG) signals [5]. Along with BCIs, various measurement methods to predict EEG signals have been researched [6-10]. BCIs can allow patients who have movement disorders to control external devices directly through neural signals from a brain. Deep brain stimulation (DBS) is a related technology that can be used to treat neurological disorders such as Parkinson's disease [11-13], depression [14], and epilepsy [15, 16]. An open-loop DBS system is relatively easy to configure, and is a preferred approach when patients have to undergo repeated surgery. However, an open-loop system cannot respond to changes in a patient’s condition. A closed-loop DBS system [16-18] monitors brain activities and delivers a modified stimulation. There are three main advantages of a closed-loop DBS: 1) it provides stimulation tailored to each patient; 2) extends the period between surgeries; 3) produces the minimum current necessary to reduce symptoms and therefore reduces the side effects that can result from an overstimulation.

A closed-loop DBS system needs feedback to control stimulation, and this is provided by a neural recording system. The action potential (AP), local field potential (LFP), and fast ripple (FR) signals produced by the brain

130 SUSIE KIM et al : A 4×32-CHANNEL NEURAL RECORDING SYSTEM FOR DEEP BRAIN STIMULATION SYSTEMS

are possible candidates for the feedback indicators [17, 19]. AP signals are typically in a frequency range of 100 Hz to 10 kHz, with amplitudes in the range 50 mV to 1 mV [20]. LFP signals have a very low frequency range of 1 Hz to 100 Hz, with similar amplitudes to AP signals [20]. FR signals, which are observed in the hippocampal area of epileptic patients, mainly exhibit frequencies of 250 Hz to 500 Hz, with an amplitude range of 30 mV to 1.5 mV [21]. AP signals have the advantage of providing information, which assists in positioning the stimulation electrodes at the correct site [19].

Neural signals generally have extremely small

amplitudes, from a few mV to a few mV. Moreover, background noise at the recording site is typically in the range of 5 mVrms to 10 mVrms [22]. Therefore, an analog front-end (AFE) of a neural recording system needs to have an input-referred noise (IRN) of no more than a few mVrms [17, 19, 23]. In addition, a neural recording system cannot use much power, because heat dissipation must be restricted to avoid necrosis in cellular tissue. Thus, an implantable system can only draw a few hundred mW [24, 25]. An electrode is another important requisite for recording a neural signal. A flexible flat-plate LCP probe, which is reliable and biocompatible, was implemented

Fig. 1. Overall architecture of the 4×32-channel neural recording system.

Fig. 2. Simplified block diagram of the 32-channel neural recording IC.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.1, FEBRUARY, 2017 131

and demonstrated with a neural recording system [26]. In this paper, we present an integrated 4×32-channel

neural recording system for DBS systems. The whole system is verified by recording a neural spike in in-vivo test on the primary somatosensory cortex of a rat. The neural recording system and electrodes are connected with a 128-channel coaxial cable, which is shielded with ground. The cable provides the test environment to be improved at the aspect of noise issue. The neural recording system includes four 32-channel neural recording ICs, Xilinx XC95144XL-10TQG100C complex programmable logic devices (CPLDs), a Microchip PIC32MX795F128L micro controller unit (MCU) with USB interface, and a PC. The 32-channel neural recording IC is implemented in 0.18 mm CMOS technology and includes AFEs and an analog-to-digital converter (ADC). The AFE has an IRN of 10.2 mVrms over a 10-kHz bandwidth and the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB at a sampling-rate of 2.5 MS/s. A high sampling-rate is appropriate for multi-channel system. The USB interface, which provides the high-speed serial link, is used to transmit the digitized neural signals of the neural recording ICs to the PC. The rest of the paper is organized as follows: Section II describes the overall architecture of the system and the details of the 32-channel neural recording IC. Section III discusses experimental results obtained from an implementation, and Section IV concludes the paper.

II. SYSTEM ARCHITECTURE

The overall architecture of our system is shown in Fig. 1. It consists of four 32-channel neural recording ICs, CPLDs, the MCU with USB interface, and the PC. When the system starts up, a start command, with 2-bit chip selection (CS[1:0]) signals and 5-bit channel selection (CHS[4:0]) signals, are sent by the PC to the MCU. The selection signals are demultiplexed by the CPLDs and transferred to the neural recording ICs. The outputs of the neural recording ICs are multiplexed by the CPLD and forwarded through the MCU. Finally, the output data are sent to the PC via the USB connection.

Fig. 2 shows a simplified block diagram of the 32-channel neural recording IC, which consists of 32 channels of AFEs, a 32-to-1 analog multiplexer, and the ADC. Each AFE is composed of a low-noise amplifier (LNA) and a programmable-gain amplifier (PGA). The PGA sets the input range of the ADC, to 500 mVpp. The ADC digitizes the amplified signal to 10-bit.

The AFE is designed with target pass-band gain and bandwidth over 40 dB, and 45 Hz to 10 kHz. The bandwidth of the AFE is tunable, allowing them to acquire LFP signals with frequencies below 100 Hz.

To achieve the dynamic range up to 60 dB, the ADC requires at least 10-bit resolution [27]. In our case, a single 10-bit, 2.5-MS/s cyclic ADC converts 32 neural signals from the AFEs to digitized ones. A required minimum sampling-rate of the ADC is 640 kS/s to handle 32 neural signals with 10-kHz bandwidth. Nevertheless, we used a sampling-rate of 2.5 MS/s considering a further system, which is capable of

Fig. 3. Block diagram of the (a) LNA, (b) OTA of the LNA, (c) PGA.


covering 128 neural signals with all frequencies of interest.

1. Analog Front-End

Since neural signals have extremely small amplitudes,

design of an AFE is the most challenging task in constructing a neural recording system. Recent designs of AFE have achieved very low IRN value of 1 mVrms to 3 mVrms [25, 28], but this requires an undesirable amount of power and area. Furthermore, such a low IRN is unnecessary in the context of the thermal noise and biological noise experienced at typical recording bandwidths of 450 Hz to 5 kHz: the average thermal noise from an electrode and the biological noise resulting from the activity of surrounding neurons are around 6.2 mVrms and 10.2 mVrms respectively [29]. Thus, a reasonable estimate of total average noise is 11.9 mVrms, and so 10 mVrms is a reasonable specification for the IRN of an AFE in a neural recording system.

A block diagram of the LNA is shown in Fig. 3(a). The LNA has a conventional capacitor feedback topology [25], which has an effective way to obtain a low IRN. The mid-band gain of the LNA is determined by the ratio of the input capacitance to the feedback capacitance CI/CF: we set CI = 10 pF and CF = 25 fF. The LNA requires a low high-pass cutoff frequency to eliminate the DC offset introduced by the electrode tissue interface. A suitable high-pass cutoff frequency can be obtained by the introduction of the PMOS pseudo-resistors, M1, M2, M3, and M4, which achieve a high resistance RX of 1012 Ω to 1014 Ω with a small area. The high-pass cutoff frequency fH and the low-pass cutoff frequency fL of the LNA can be expressed as follows:

1

2 ( )HX F X

fR C Cp

=+

(1)

,2

mL

L tot

Gf

Cap

= (2)

where F X

I P F X

C CC C C C

a+

=+ + +

a

and ,

( )( )F X I PL tot L

I P F X

C C C CC CC C C C

+ += +

+ + +. a

Gm is the transconductance of the operational

transconductance amplifier (OTA) within the LNA, CL is

the capacitance of the output load of the LNA, CP is the parasitic capacitance at the input to the LNA, and CX is the parasitic capacitance of the PMOS pseudo-resistors. The high-pass cutoff frequency of the LNA is tunable by adjusting RX. As the common-gate voltage VCON of the PMOS pseudo-resistors increases, the high-pass cutoff frequency of the LNA decreases. The loop gain of the LNA, T(s) is derived by solving the KCL nodal equation, which can be expressed as:

,

( )1

m out

out L tot

G RT s

sR Ca

=+

. (3)

Assuming that a DC loop gain is sufficiently large, the

transfer function of the LNA, H(s) can be approximated as follows:

,

1( )1 ( / )

( )1 ( )

I

F X L tot m

X F X

X F X

CH sC C s C G

sR C CsR C C

aæ öæ ö

= ç ÷ç ÷ç ÷+ +è øè øæ ö+ç ÷+ +è ø

. (4)

The noise that comes from the PGA is divided by the

gain of the LNA, and thus we can assume that noise from the LNA itself dominates the IRN of the AFE. Considering thermal noise alone, the IRN power-spectral density (PSD) of the LNA can be expressed as follows:

2 3 7

1 1 1

4 28 23

M Min

M M M

g gkTV fg g g

æ ö= + + Dç ÷

è ø (5)

where k is Boltzmann's constant and T is the absolute temperature. This tells that the IRN of the LNA is inversely proportional to the transconductance gM1 of its input transistor, as shown in Fig. 3(b). Considering the results, increasing the width of this transistor reduces the IRN, at the expense of additional power and area. Therefore, we size M1 to achieve an appropriate compromises between noise and power, W/L = 200, and set a bias current to 2 mA. The noise efficiency factor (NEF) [30] expresses a tradeoff between noise and power:

,

24

totni rms

T

INEF V

kTU BWp= (6)


where Vni,rms is the input-referred RMS noise voltage, Itot is the total supply current, UT is the thermal voltage, and BW is the bandwidth, which is -3 dB.

Fig. 3(c) shows a block diagram of the PGA, which is designed with a flip-over-capacitor [31]. The mid-band gain of the PGA can be adjusted to 7, 10, 15, or 20 dB. The switch pairs S1 and S1B, S2 and S2B are complementary. The bandwidth of the PGA is designed to cover the full range of the LNA, from 10 Hz to 30 kHz.

2. Analog-to-digital Converter

As CMOS technology scales down, designing the

analog circuits in ADCs has become more difficult, especially with high-gain operational amplifiers (opamps) [32]. Several techniques have been developed to address this problem, such as correlated level shifting [33], open-loop residue amplifiers [34], gain calibration [35], and comparator-based switched-capacitor (CBSC) technique [36]. The particular advantage of the CBSC technique is that it replaces an opamp with a comparator, which reduces the design complexity and power consumption of an ADC. It is especially well suited to a cyclic ADC, which only uses a single gain stage and performs conversions cyclically. A cyclic ADC offers a combination of high-resolution, low power consumption, and small chip area that is suitable for a neural recording IC. Its main disadvantage is the length of conversion cycles. However, by boosting the preset voltage, we can improve the conversion rate without increasing the power consumption.

During the sampling phase (Φ1), as shown in Fig. 4, the input voltage is sampled to the capacitors C1 and C2, which acquire a total charge and can be expressed as follows:

1 2( )( )in comQ C C V V= + - . (7)

Fig. 5 shows the conventional CBSC gain stage and its

transient response. The gain stage operates with a preset phase (P) followed by a charge transfer phase (E). During the preset phase, the sampling switch is closed to reset the load capacitance.

The initial value of the summing node voltage VX0 can be expressed as follows:

20

1 2

2X com in

CV V VC C

æ ö= - -ç ÷+è ø

. (8)

The time required to complete the charge transfer

depends on VX0. To ensure the correct operation, all the charge must be transferred during the charge transfer phase. In our case, this is achieved by the boosted preset voltage scheme shown in Fig. 6(a). When the preset voltage Vpreset is applied at the output node, initial value of the summing node voltage VX0 can be expressed as follows:

2 10

1 2 1 2

2X com in preset

C CV V V VC C C C

æ ö æ ö= - - +ç ÷ ç ÷+ +è ø è ø

. (9)

Fig. 6(b) shows the preset voltage reducing the time to

Fig. 4. Conventional CBSC sampling phase (Φ1) and transfer phase (Φ2).

Fig. 5. (a) Conventional CBSC gain stage, (b) its transient response.


complete the charge transfer. A block diagram of the cyclic ADC is shown in Fig. 7.

The implemented ADC consists of two multiplying DACs (MDACs), two 1.5-bit sub-ADCs (SADCs), a digital correction logic, and a clock signal generator. An extra set of MDAC and SADC stages is substituted for the sample-and-hold amplifier (SHA) used in a conventional cyclic ADC. This doubles conversion speed and eliminates the noise that would otherwise be contributed by the SHA. The CBSC technique is implemented using a single comparator and current sources to support two MDACs. The main issues in the CBSC stage are the voltage offset and nonlinearity; these effects are proportional to the charging current, which produces an overshoot voltage. This is reduced by the use of coarse and fine charge transfer phases shown in Fig. 8(a). During the coarse charge transfer phase (E1), the output voltage VO and virtual ground condition are quickly estimated. When the comparator makes its decision, the current source I1 turns off. However, the output voltage VO and the summing-node voltage VX0 overshoot their correct values, as shown in Fig. 8(b). The fine charge transfer phase (E2) then begins, and the values are corrected by a current flowing in the opposite direction, provided by a second current source I2.

III. MEASUREMENT RESULTS

We implemented a 4×32-channel neural recording system, which is integrated by stacking boards. This structure gives short wire lines to be connected and provides a compact volume. Fig. 9 shows a die photograph of the 32-channel neural recording IC, which is one of the key components of our system. The neural recording IC is fabricated in 0.18 mm CMOS process with one poly silicon and six metal layers. The area of the 32 channels of the AFEs and the ADC are 4.55 mm2 and 0.146 mm2 respectively.

Fig. 6. (a) CBSC with boosted preset voltage gain stage, (b) its transient response.

Fig. 7. Block diagram of the proposed comparator-based cyclic ADC.

Fig. 8. (a) Proposed CBSC with boosted preset voltage gain stage, (b) its transient response.


1. Neural Recording IC Characteristics The performance of our 32-channel neural recording

IC is verified with an Agilent 35670A dynamic signal analyzer and a Tektronix TLA6202 logic analyzer. Measuring a single channel is valid for verifying our 32-channel neural recording IC because all channels are designed to have same characteristics. An input sine wave with an amplitude of 1 mVpp and a frequency of 1 kHz is used for the AFE.

Fig. 10 shows how the transfer function of the AFE changes as the gain of the PGA varies. When the gain of the PGA is set to 7 dB, the mid-band gain of the AFE achieves 54.5 dB, and the high-pass and low-pass cutoff frequencies are 35.3 Hz and 5.8 kHz respectively. Fig. 11 shows how the transfer function of the AFE changes as the high-pass cutoff frequency varies. The high-pass cutoff frequency varies from 18.6 Hz to 154.7 Hz as

VCON of the LNA decreases from 925 mV to 850 mV. Fig. 12 shows the IRN spectrum of the AFE, which is

measured by dividing the output-referred noise (ORN) spectrum of the AFE by its gain. It is recommended to measure the ORN with dividing the frequency ranges in order to obtain accurate data values. Since the resolutions between the gain of the AFE and the ORN are different, we interpolated the lacking data of the AFE by using a curve fitting tool in MATLAB. The IRN and NEF of the AFE are found to be 10.2 mVrms and 10.3 respectively.

Fig. 13 shows the measured output spectrum of the ADC with a 10-kHz sine wave and sampling-rate of 2.5 MS/s. The SNDR and the spurious-free dynamic range (SFDR) are found to be 50.63 dB and 63.88 dB respectively. The output data of a single channel that consists of the AFE and the ADC are successively transferred to the PC through the high-speed serial link.

Fig. 9. Die photograph of the 32-channel neural recording IC.

Fig. 10. Measured transfer function of the AFE on the gain of the PGA.

Fig. 11. Measured transfer function of the AFE on the high-pass cutoff frequency.

Fig. 12. IRN spectrum of the AFE.


The power consumption per channel is 62.5 mW. 2. In-vivo Test

Our implemented 4×32-channel neural recording

system is also validated in in-vivo recording of the primary somatosensory cortex of a rat. Commercial electrodes are coupled to our system. Since in-vivo test is vulnerable to external electrical noise, the experiment is proceeded inside a Faraday cage, as shown in Fig. 14. A 128-channel coaxial cable is employed to connect and share the ground between the electrode and our system. The specification of the cable covers multi micro-coaxial cable for medical equipment. Each channel of the cable is shielded with ground to suppress an external noise and a coupling effect.

A stimulus is applied to the rat's whisker area. The recorded neural spike, which is obtained by our implemented system is shown in Fig. 15. The occurrence of a neural spike between 20.41 sec and 20.42 sec is clearly recorded.

Table 1 compares the characteristics of our system

Fig. 13. Measured output spectrum of the ADC with a 10-kHz sinusoidal input signal sampled at 2.5 MS/s.

Fig. 14. Experimental environment of the in-vivo test.

Fig. 15. Recorded neural spike from the in-vivo test with ourimplemented system.

Table 1. Comparison to Other Neural Recording Systems Characteristics

Reference This work [17] [31] [38] [39] Number of channels 128 (= 4×32) 4 16 128 8

AC Gain [dB] 54.5 - 65.7 54 70 73 65.6 High-pass cutoff freq. [Hz] 18.6 - 154.7 0.64 100 10 1.1 Low-pass cutoff freq. [kHz] 5.8 6 9.2 5 12

Total IRN [mVrms] 10.2 6.3 5.4 6.08 3.12 NEF 10.3 3.76 4.9 5.6 2.68

ADC type Cyclic Pipeline (log) SAR SAR SAR ADC resolution [bits] 10 8 8 8 10

SNDR [dB] 50.63 35.5 N/A N/A < 50 Sampling-rate [S/s] 2.5 M 100 k 30 k 111 k 35.7 k

Power [mW/channel] 62.5 61.25 42.5 15.52 32.8

Technology [mm] 0.18 0.18 0.18 0.35 0.35


with several other neural recording systems that have a similar recording bandwidth. Our system achieves superior resolution, SNDR, and sampling-rate. In addition, our system contains 4×32-channel and therefore has advantage over the others in terms of acquiring meaningful data.

IV. CONCLUSIONS

We have presented a 4×32-channel neural recording system that acquires neural signals, and validated in in-vivo test on the primary somatosensory cortex of a rat. The 128-channel ground-shielded coaxial cable is used in in-vivo test to eliminate the external noise sources. The 32-channel neural recording ICs, which are implemented in 0.18 mm CMOS technology, are used. The AFE of our system has an IRN of 10.2 mVrms. The comparator-based cyclic ADC with boosted preset voltage has achieved high-resolution, low power consumption, and high conversion speed. Our neural recording system is designed for use in multi-channel DBS systems.

ACKNOWLEDGMENTS

This work was supported in part by Inter-university Semiconductor Research Center (ISRC) of Seoul National University.

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Susie Kim received the B.S. degree in the Department of Electrical and Computer Engineering from Seoul national University, Seoul, Korea, in 2007. She is currently working toward the Ph.D. degree at Seoul National University, Seoul, Korea.

Her research interests are in analog and mixed-signal integrated circuits and systems.

Seung-In Na received the B.S. degree in the Department of Electrical Engineering from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2009 and received the M.S. and Ph.D. degrees in the Department of

Electrical and Computer Engineering from Seoul National University, Seoul, Korea, in 2011 and 2016, respectively. In 2016, he joined at Samsung Electronics, where he has been working in the area of oversampling ADC design for audio application. His current research interest includes analog circuit designs for audio application.

Youngtae Yang received the B.S. degree in the Department of Elec- trical and Computer Engineering from Seoul National University, Seoul, Korea, in 2013. He is currently working toward the Ph.D. degree at Seoul National University,

Seoul, Korea. His research interests include oversampling ADC for audio and motion sensor application.

Hyunjong Kim received the B.S. degree in the Department of Electrical and Computer Engineering from Seoul National University, Seoul, Korea, in 2014. He is currently working toward the Ph.D. degree at Seoul National University,

Seoul, Korea. His research interests are in analog and mixed-signal integrated circuits and systems.

Taehoon Kim received the B.S. and M.S. degrees in the Department of Electrical and Computer Engineering from Seoul National University, Seoul, Korea, in 2009 and 2012, respectively. He is currently working toward the Ph.D. degree at Seoul

National University, Seoul, Korea. His research interests include sensor interface circuits, analog front-end circuits and analog-to-digital converters for ultrasound medical imaging application.


Jun Soo Cho received the B.S. and M.S. degrees in the Department of Industrial Engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. In 2014, he received the Ph.D. in the Department of Electrical and Computer

Engineering from Seoul National University, Seoul, Korea, focusing on audio mixed signal circuits including high-fidelity sigma-delta ADC. He worked at Neofidelity Inc., Korea, designing full digital audio amplifier circuits from 2001 to 2014. He is currently with Inter-university Semiconductor Research Center in Seoul National University, Seoul, Korea. His research interests include analog/digital/mixed circuit design and audio signal processing.

Jinhyung Kim received the B.S. degree in the Department of Information Technology Engineering, College of Engineering, Hanyang University, Seoul, Korea, in 2007. In 2014, he received the Ph.D. degree in the Department of Neurosurgery,

College of Medicine, Yonsei University, Seoul, Korea. His thesis of the Ph.D. was on finding the alleviation effect by deep brain stimulation (DBS) for cold allodynia. To elucidate this, he developed a new behavioral test method for cold allodynia with DBS in animal model, and analyzed brain activities using electrophysiology. He is currently working on neuropathic pain including cold allodynia using electrophysiology, imaging methods such as mPET, fMRI and optogenesis.

Jin Woo Chang received the B.S., M.S., and Ph.D degrees in the Department of Neurosurgery, College of Medicine, Yonsei University, Seoul, Korea, in 1983, 1985, and 1993, respectively. The thesis of his Ph.D. degree was focused on the

effects of neural transplantation in the rat parkinsonian model. He started his profession in stereotaxic functional neurosurgery, in 1991, and he is currently the professor

in Department of Neurosurgery at Yonsei University College of Medicine, Seoul, Korea. Currently, Dr. Chang is a President of Korean Neurosurgical Society and he is a secretary of the World Society for Stereotaxic and Functional Neurosurgery.

Suhwan Kim received the B.S. and M.S. degrees in electrical engineering and computer science from Korea University, Seoul, Korea, in 1990 and 1992, respectively, and the Ph.D degree in electrical engineering and computer science from the

University of Michigan, Ann Arbor, in 2001. From 1993 to 1999, he was with LG Electronics, Seoul, Korea. From 2001 to 2004, he was a research staff member at the IBM T.J. Watson Research Center, Yorktown Heights, New York. In 2004, he joined Seoul National University, Seoul, Korea, where he is currently professor of electrical engineering. His research interests encompass Analog and Mixed Signal circuits and Device/Circuit Co-Design opportunities. He received the 1991 Best Student Paper Award of the IEEE Korea Section, the First Prize (Operational Category) in the VLSI Design Contest of the 38th ACM/IEEE Design Automation Conference, and the 2011 Best Paper Award of the International Symposium on Low-Power Electronics and Design. He served as a guest editor for IEEE Journal of Solid-State Circuits special issue on IEEE Asian Solid-State Circuits Conference. He has also served as the general co-chair and technical program chair for the IEEE International SOC Conference. He has participated on the technical program committee of the IEEE International SOC Conference, the International Symposium on Low-Power Electronics and Design, the IEEE Asian Solid-State Circuits Conference, and the IEEE International Solid-State Circuits Conference.

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