Cost-Efficient and Automatic Large Volume Data Acquisition Method for On-Chip...

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2015.15.2.184 ISSN(Online) 2233-4866

Manuscript received Aug. 20, 2014; accepted Jan. 1, 2015 Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH) 77 Cheongam-Ro, Nam-Gu, Pohang, Gyeongsangbuk-do, 790-784, Korea E-mail : [email protected], [email protected]

Cost-Efficient and Automatic Large Volume Data Acquisition Method for On-Chip Random Process

Variation Measurement

Sooeun Lee, Seungho Han, Ikho Lee, Jae-Yoon Sim, Hong-June Park, and Byungsub Kim

Abstract—This paper proposes a cost-efficient and automatic method for large data acquisition from a test chip without expensive equipment to characterize random process variation in an integrated circuit. Our method requires only a test chip, a personal computer, a cheap digital-to-analog converter, a controller and multimeters, and thus large volume measurement can be performed on an office desk at low cost. To demonstrate the proposed method, we designed a test chip with a current model logic driver and an array of 128 current mirrors that mimic the random process variation of the driver's tail current mirror. Using our method, we characterized the random process variation of the driver's voltage due to the random process variation on the driver's tail current mirror from large volume measurement data. The statistical characteristics of the driver's output voltage calculated from the measured data are compared with Monte Carlo simulation. The difference between the measured and the simulated averages and standard deviations are less than 20% showing that we can easily characterize the random process variation at low cost by using our cost-efficient automatic large data acquisition method. Index Terms—Random process variation, cost-efficient measurement, automatic large volume data acquisition, statistical characterization, current mode

logic driver, current mirror array

I. INTRODUCTION

Random process variation is becoming problematic degrading circuit performance in analog circuits as CMOS technology advances into nano scale. For instance, sensitivity of a sense amplifier is reduced by large threshold voltage variation [1, 2]. In feed forward equalization (FFE) transmitters that use a current mode logic (CML) type driver, process variation at current biasing in a driver causes tap coefficient errors which lead to overall FFE performance degradation [2-5].

To estimate the performance degradation due to random process variation, large volume measurement is necessary to statistically characterize random process variation. Statistical characteristics such as average and standard deviation allow designers to compute performance variation of circuits for a given target yield. However, to fully characterize random process variation, massive measurement data for all interesting dc conditions are required since random process variation depends on dc conditions such as bias voltage and bias current. Because at least hundreds of samples are required by each statistical characterization for a given dc condition and designers can be interested in more than hundreds of dc conditions, the overall data volume can easily exceed million points.

Measuring large volume data requires too expensive testing equipment or costs too much human labors increasing time-to-market. To statistically characterize random process variation, large volume of identical cells

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015 185

should be implemented on wafers and measured. For this purpose, expensive automatic on-wafer testing equipment is widely used but it is very costly. Without expensive equipment, often tedious manual repetitive experiment is required for massive measurements.

To reduce the cost of random process variation measurement, we propose an automatic method to measure on-chip random process variation at low cost. The proposed method enables large volume measurement on an office desk utilizing a personal computer (PC), a controller, a cheap digital-to-analog converter (DAC). In our method, with a simple script on the PC, engineers can program the test sequence and test conditions such as selection of 128 current mirrors via the controller and the bias voltage by the DAC. When incorporated with cheap multimeters which are controlled by general purpose interface bus (GPIB), our method allows engineers to measure random process variation easily, cost-efficiently, and automatically.

The rest of this paper is organized as follows. Section II explains our measurement object, and Section III describes the overall structure of the proposed measurement setup. Section IV explains the design of the test circuits, and Section V discusses details of the controller. In Section VI, we analyze the variation measurement result and compare it with the simulation result. Section VII summarizes and concludes this paper.

II. MEASUREMENT TARGET

We demonstrate the proposed method by measuring how the random process variation of a current mirror affects a CML driver. Fig. 1 describes the test object, a CML type driver, and its current biasing circuit. A CML driver is widely used in many high-speed interconnect applications including peripheral component interconnect-express (PCI-e) [6] and universal serial bus (USB) [7] in which the voltage swing of the output driver is typically specified tightly. The voltage swing is usually controlled by the bias current through a driver's tail current mirror. Therefore, random process variation on the current mirror varies the bias current and thus the output voltage swings. On the contrary, the output voltage variation due to random process variation on the CML driver is insignificant because the transistors in CML drivers are relatively large and fully turn on during

operation. In mass production, this output voltage variation may reduce design margin and thus yield. Therefore, statistical analysis on the effect of the random process variation of the current mirror on the output voltage is the key information in design for manufacturing.

Our measurement method enables engineers to easily measure the effect of the random process variation of the current mirror on the CML driver. The measurement method is not limited only to the CML driver explained in the following sections, but is also applicable to other similar variation measurement by replacing the test circuit structure with new measurement target.

III. MEASUREMENT SET-UP

We describe the overview of the proposed measurement method in this section, and then illustrate the details in the next sections. Fig. 2 illustrates the overview of the test set-up for the proposed method. This set-up consists of five major blocks: a test chip, a DAC, a controller, multimeters that are compatible with a GPIB, and a PC.

• Test chip: To measure random process variation of the output voltage due to the variation on the current mirror, we designed a selectable 128-current mirror array that biases a CML driver. From the central limit theorem, if the variation is attributed to the random variation and number of sample is larger than 30 (128 samples in this work), we expect to get quite accurate statistical characteristic. We can increase the number of samples, but we need to

Fig. 1. A CML driver affected by random process variation in current mirror.

186 SOOEUN LEE et al : COST-EFFICIENT AND AUTOMATIC LARGE VOLUME DATA ACQUISITION METHOD FOR ON-CHIP …

spend more area to implement more samples. Because our random process variation measurement method focuses on cost-efficiency, we choose to design a selectable 128-current mirror array. A 7-to-128 decoder was used to select one of the 128 current mirrors in the array. Because of random process variation among the 128 current mirrors, the output current of the current mirror array varies as the decoder’s selection changes. The output current of the array feeds the bias current of the CML driver. By measuring variation in the differential voltage of the CML driver we can measure how the random process variation on the current mirror circuit affects the CML driver.

• DAC: To characterize random process variation at various dc conditions we control the reference current of the current mirror array by programming DAC voltage because the DAC output is connected to the reference current mirror input of our test chip through a series resistor. In our method, engineers can control the DAC voltage with a simple function on a PC through a controller. In our system, an 8-channel, 12-bit DAC with 0~0.25 V output voltage range is used.

• controller: A controller implemented in a field programmable gate array (FPGA) enables automatic measurement by controlling inputs of the test chip according to the instruction from the PC. The controller controls the DAC output voltage and gives

8-bit static decoder input (a<0:6> and Reset) which is used to select the current mirror sample out of the current mirror array according to the message passed from a PC through a USB interface. By sweeping DAC output voltage for each current mirror sample, we can acquire enough data to statistically characterize the effect of random process variation on the test object at various bias conditions.

• GPIB-compatible multimeters: The input reference current of the current mirror and the differential output voltage of the CML driver are measured using GPIB-compatible multimeters. The GPIB-compatible multimeters provide a cheap solution for automatic data acquisition by a PC.

• PC: In our method, a PC controls overall measurement through the controller according to the user input script. The PC sends messages to the controller through a USB interface. In addition, the PC controls and acquires measurement data from GPIB-compatible multimeters, and also performs statistical analysis.

In this method, only with those five inexpensive blocks,

engineers can automatically acquire large volume data to characterize random process variation across various bias conditions using a simple script running on a PC.

IV. CIRCUIT DESCRIPTION

In this section, we describe details of the implemented test chip including the current mirror array, the 7-to-128 decoder, and the CML driver.

1. Current Mirror Array

Fig. 3 depicts the structure of the current mirror

feeding the bias current of the CML driver. The current mirror consists of two parts: a reference input stage and a current mirror array. The external reference current input is precisely controlled by the DAC and a series resistor connected to the reference input stage through the pad. At reference input stage, the external reference current input is duplicated and fed to one of the 128 current mirrors in the mirror array according to Sel<0:127> input of the 7-to-128 decoder. To prevent the gate voltages of the 127 unselected current mirrors from

Fig. 2. The test set-up of the proposed cost-efficient and automatic on-chip testing method to measure random process variation.


floating, the gates of NMOS and PMOS of the unselected current mirrors are connected to ground and supply, respectively, through switches. The output current of the current mirror array is multiplied and fed to the CML driver’s bias current input. The bias current input and thus the output voltage of the CML vary due to the random process variation among 128 current mirrors when different current mirror is selected from the array. Therefore, by measuring variation of the output voltage of the CML driver for each current mirror, we can measure the effect of random process variation of a current mirror on a CML driver.

2. 7-to-128 Decoder Fig. 4 shows a schematic diagram of our 7-to-128

decoder composed of 128 'nor' type structured decoder cells. From the 7-bit selection input a<0:6>, a 7-bit inverter array generates the complement 7-bit signal

0:6a < > . The a<0:6> and 0:6a < > signals in the

decoder cells are connected differently from each other; this difference ensures that only one cell does not have a pull-down connection for all a<0:6> input codes. This pull-down path is designed to be stronger than the other

two pull-up PMOSs: one for Reset and one for charge keeping. Therefore, for a given input code a<0:6>, when the reset pulse is applied, only one decoder cell, which does not have the pull-down path for the given code, charges up the bit-line node of the cell. Once this node is charged up, the charge keeping pull-up PMOS turns on and compensates for the leakage current of the disconnected pull-down NMOSs to prevent voltage drop by the leakage. As a result, only one Sel<k> signal out of Sel<0:127> becomes 1; the others remain 0.

3. CML Driver

A typical CML I/O driver with 50-Ω termination is implemented as a test object. The differential output voltage of the CML is measured to characterize the effect of random process variation among the current mirrors in the current mirror array. Because of random process variation in the bias current of the CML driver, the output voltage of the CML driver has random process variation.

V. CONTROLLER

A controller for the DAC and the decoder of the test chip is implemented in an FPGA. Fig. 5 shows the block diagram of the controller consisting of a USB 2.0 interface circuit, first input first output (FIFO) blocks,

Fig. 3. A circuit diagram of the current mirror array and the CML driver.

Fig. 4. A simplified schematic diagram of the decoder. 7-bit inverters which generate 0 : 6a< > are omitted.


and a serial peripheral interface (SPI) module. A PC delivers 32-bit messages for the DAC and 8-bit static decoder input (a<0:7> and Reset) to the controller through USB. Inside the controller, a USB 2.0 interface circuit receives 32-bit messages and 8-bit static decoder input, and sends the messages to a 16-bit FIFO module and feeds the 8-bit static decoder input to the decoder. The USB 2.0 interface circuit is designed for general purpose 16-bit packet communication whereas the message for DAC control is 32-bit wide. Therefore, the PC delivers two 16-bit packets through the USB and the FIFO-merge module combines them into one 32-bit message. The SPI module receives the 32-bit message from a FIFO-32 module and serializes the message into SPI signal DIN and generates the SPI control signals SCLK and NSYNC. When the NSYNC signal is kept low for 32 falling edges of SCLK, the 32-bit parallel massage is serially transferred to the DAC on the falling edge of SCLK by the SPI module.

Fig. 6 shows the timing diagram of data transfer in our system and Table 1 explains the related control signals. To prevent message overwrite between modules systematically, the interface is designed based on two control signals: FULL and READY. The FULL signal becomes high whenever a receiving module cannot receive data because the buffer is full. The READY signal is high when the transmitting module is ready to transfer data. When the FULL signal is low and the READY signal is high between two modules, data transfer is performed in a guarded atomic action [8].

For easy usage, a DAC control function dacctr(obj.ptr,

Chx, Vx) is provided as a script function. Chx is the channel selection input between 1 and 8, and Vx is voltage input between 0 and 2.5. For example, in Fig. 5 user input “dacctr(obj.ptr, 1, 2)” sets the output voltage of DAC channel 1 to 2 V. This input is mapped to a 32-bit message as Fig. 7. The 32-bit message consists of command bits [27:24], address bits [23:20], data bits [19:8], and other reserved bits as shown in Fig. 7. The command bits [27:24] are used for updating the DAC voltage and changing the DAC mode. The address bits

Fig. 6. Timing diagram of the USB interface circuit.

Table 1. Control signals for guarded atomic data transfer

READY When this signal is high, the transmitting module is ready to transfer a data

FULL This signal is high, when the receiving module is full, i.e., not ready to receive a data.

Fig. 7. Composition of a 32-bit message for a DAC.

Fig. 5. A block diagram of the controller implemented in an FPGA.


[23:20] determine the DAC output channel. Finally, the data bits [19:8] determine the magnitude of the 12-bit DAC voltage.

VI. MEASUREMENT RESULT

The proposed test chip was fabricated in 65-nm CMOS technology and the die photo is shown in Fig. 8. The current mirror array occupies 40 μm × 100 μm and the decoder occupies 60 μm × 80 μm. The area of the CML driver is negligible compared with other blocks.

The fabricated chip was tested using our method on an office desk without expensive on-wafer testing equipment. Fig. 9(a) shows our experimental set-up consisting of a test chip, a PC, a controller, a DAC, and multimeters. The test was fully automated by a simple script on PC, and therefore, human labors for testing could be greatly saved. Compared to our method, a typical method using commercial on-wafer testing equipment shown in Fig. 9(b) is too expensive and occupies too much space for a small budget research group. Therefore, small research groups in academia and small research institutes can be equipped with automatic large volume measurement by using our method.

To statistically characterize random process variation we automatically measured differential output voltage of the CML driver for all 128 current mirrors. Selecting the current mirror cell, setting the reference current, and measuring the CML output voltage were performed completely automatically using our user script. We swept the reference current for 16 different values, and measured the 128 output voltages of the CML driver per each reference current point. Table 2 shows the

measurement time to measure the result in Fig. 10. As seen in Table 2, the proposed measurement method spends 2999 seconds to measure 2048 voltage samples (1.464 seconds per a sample), supporting large volume of measurement is possible without costly equipment. From the measured 128 CML voltages, the average and the

Fig. 8. A die photo of the test-chip.

Fig. 9. Measurement set-ups for large volume data acquisition to characterize random process variation (a) the proposed measurement method, (b) costly on-wafer testing equipment.

Fig. 10. Measured CML output voltages for 16 different dc reference currents.

Table 2. Measurement time to measure 2048 voltage samples

Measurement time (s) 2999 Measurement time for a point (s) 1.464


standard deviation of the CML output voltages were calculated and they are converted to the average and the standard deviation of the tail currents of the CML driver in Table 3. Also, to show the distributions of the CML output voltage directly, we plotted the histograms of the measured 128 CML output voltages when the reference currents are 107 μA and 197 μA in Fig. 11.

To verify the accuracy of our measurement, we performed Monte Carlo simulations for the same reference

currents, and compared the simulated results to the measured data. Table 3 shows the average and the standard deviation values of the simulated CML output voltages too. We also converted them to the average and standard deviation values of the tail currents of the CML driver in the same table. To show the distributions of the simulated CML output voltages directly as we presented the measured data, we plotted the histograms of the simulated 128 CML output voltages when the reference currents are 107 μA and 197 μA in Fig. 12. Because the test chip was implemented using mature CMOS technology whose random process variation has been modeled well, the results from the measurement and the simulation must be similar. When the reference current is small, the difference between the measured and the simulated average voltages is relatively large: the difference is up to 11.1 mV (20 %). However, the difference decreases as the reference current increases, and becomes only 1.1 mV when the reference current is 197 μA as Table 3 and Fig. 13(a) show. The reason for the relatively large difference at low reference current condition is due to the offset voltage which was resulted from systematic error: the average of the CML output voltage is 12.8 mV although the reference current is closed to zero (1.2 μA) in Fig. 10. In Fig. 13(b), the measured standard deviation is always higher than the simulated standard deviation, because Monte Carlo simulation takes only the random process variation into account while the systematic variation is included in our measurement. Also, although the difference between the simulated and the measured standard deviations is up to 20 % when the reference current is 197 μA, the magnitude of the difference is small (only 1 mV), which

mean : 174.8 mVs.d : 7.1 mV

(a)

(b)

mean : 252.7 mVs.d: 5.9 mV

Fig. 11. Histograms of the measured CML output voltages(n=128) when (a) reference current is 107 mA, (b) reference current is 197 mA.

Table 3. The measured and simulated CML output voltages and the tail currents of the CML driver listed by the reference current point

Measured Simulated CML output voltage Converted to tail current CML output voltage Converted to tail current

reference current (mA) mean(mV) s.d.(mV) mean(mA) s.d.(mA) mean(mV) s.d.(mV) mean(mA) s.d.(mA) 19.3 71.8 5.4 1.44 108 60.7 4.9 1.21 98 47.5 111.3 6.3 2.23 126 102.5 6.0 2.05 120 77.0 144.3 6.8 2.89 136 138.0 6.2 2.76 124 106.8 174.8 7.1 3.50 142 170.5 6.2 3.41 124 136.9 203.5 7.0 4.07 140 200.3 5.9 4.01 118 167.2 230.0 6.6 4.60 132 227.8 5.5 4.56 110 197.4 252.7 5.9 5.05 118 251.6 4.9 5.03 98


can be considered as measurement error. Because Monte Carlo simulation is based on statistical characteristics of random process variation measured by expensive measurement equipment, the similarity of our results to those of Monte Carlo simulation implies that we can rapidly characterize random variation at interesting dc points with our costless measurement method.

VII. CONCLUSIONS

We presented a cost-efficient and automatic testing method to measure random process variation only using a test chip, a cheap controller implemented in an FPGA, a cheap DAC, a PC, and GPIB-compatible multimeters instead of expensive measurement equipment. In our method, with a simple script, engineers can program the bias condition or the digital configuration of the test chip with the DAC via a controller, and can measure voltage or current by the GPIB-compatible multimeters. Therefore, large volume data at various bias condition can be automatically acquired with our method. For demonstration, a test chip was implemented to measure random process variation of the CML driver's output voltage due to the random process variation on its tail current mirror. To mimic these variation, a CML driver and a 128 current mirror array is included in the test chip. By using the proposed method we measured random process variation of our test chip. The differences between the averages and the standard deviations from our measurement and Monte Carlo simulation are 1.1 mV and 1 mV, respectively, when the systematic error becomes insignificant. Since this small difference can be considered as measurement error, this result implies that we could statistically characterize the random process variation within reasonable measurement error. With our proposed method, cost-efficient and automatic measurement of the effect of the random process variation of a current mirror on the CML driver is possible. The measurement method is not limited only to a CML driver but is applicable to other similar variation measurement by replacing the test circuit structure with new measurement target.

Fig. 12. Histograms of the simulated CML output voltages(n=1000) when (a) reference current is 107 mA, (b) reference current is 197 mA.

(a)

(b)

Fig. 13. (a) Averages of the measured and the simulated CML output voltages, (b) the standard deviations of the measured and the simulated CML output voltages for various reference currents.


ACKNOWLEDGMENT

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (No. 2013R1A1A2007094).

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Sooeun Lee was born in Su-Won, Korea, on 1990. She received B.S. degree in the Department of Elec- trical Engineering from Pohang University of Science and Techno- logy (POSTECH), Pohang, Korea, in 2013. She is currently pursuing the

M.S. degree in the Department of Electronic and Electrical Engineering from POSTECH, Korea. Her interests include high-speed serial/parallel links, Resistive RAM.

Seungho Han received the B.S. degree in the department of Electrical Engineering at Pohang University of Science and Technology (POSTECH), Pohang, Korea in 2013. He is currently pursuing Ph.D. degree at the same school. His research interest

includes high-speed interface disgn and computer-aided-design for mixed-signal circuits.

Ikho Lee received B.S. degree in the Department of Electrical Engineering from Kyungpook National University, Daegu, Korea, in 2013. He is currently pursuing the M.S. degree in the Department of Electronic and Electrical Engineering from Pohang

University of Science and Technology, Korea. His interests include biosensor testing system, digital system design.


Jae-Yoon Sim received the B.S., M.S., and Ph.D. degrees in Elec- tronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea, in 1993, 1995, and 1999, respectively. From 1999 to 2005, he worked as a

senior engineer at Samsung Electronics, Korea. From 2003 to 2005, he was a post-doctoral researcher with the University of Southern California, Los Angeles. From 2011 to 2012, he was a visiting scholar with the University of Michigan, Ann Arbor. In 2005, he joined POSTECH, where he is currently an Associate Professor. He has served in the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC), Symposium on VLSI Circuits, and Asian Solid-State Circuits Conference. He is a co-recipient of the Takuo Sugano Award at ISSCC 2001. His research interests include high-speed serial/parallel links, PLLs, data converters and power module for plasma generation.

Hong-June Park received the B.S. degree from the Department of Electronic Engineering, Seoul National University, Seoul, Korea, in 1979, the M.S. degree from the Korea Advanced Institute of Science and Technology, Taejon, in 1981, and the Ph.D. degree

from the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, in 1989. He was a CAD engineer with ETRI, Korea, from 1981 to 1984 and a Senior Engineer in the TCAD Department of INTEL from 1989 to 1991. In 1991, he joined the Faculty of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Gyeongbuk, Korea, where he is currently Professor. His research interests include CMOS analog circuit design such as high-speed interface circuits, ROIC of touch sensors and analog/digital beamformer circuits for ultrasound medical imaging. Prof. Park is a senior member of IEEE and a member of IEEK. He served as the Editor-in-Chief of Journal of Semiconductor Technology and Science, an SCIE journal (http://www.jsts. org) from 2009 to 2012, also as the Vice President of IEEK in 2012 and as the technical program committee member of ISSCC, SOVC and A-SSCC for several years.

Byungsub Kim received the B.S. degree in Electronic and Electrical Engineering (EEE) from Pohang University of Science and Tech- nology (POSTECH), Pohang, Korea, in 2000, and the M.S. (2004) and Ph.D. (2010) degrees in Electrical

Engineering and Computer Science (EECS) from Massachusetts Institute of Technology (MIT), Cambridge, USA. From 2010 to 2011, he worked as an analog design engineer at Intel Corporation, Hillsboro, OR, USA. In 2012, he joined the faculty of the department of Electronic and Electrical Engineering at POSTECH, where he is currently working as an assistant professor. He received several honorable awards. In 2011, Dr. Kim received MIT EECS Jin-Au Kong Outstanding Doctoral Thesis Honorable Mentions, and IEEE 2009 Journal of Solid-State Circuits Best Paper Award. In 2009, he received Analog Device Inc. Outstanding Student Designer Award from MIT, and was also a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 IEEE Internal Solid-State Circuits Conference.

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