A 20 MHz 200-500 mA Monolithic Buck Converterfor RF Applications

Jason Hannon, Raymond Foley, James Griffiths, Dara O’Sullivan, Kevin G. McCarthy and Michael G. EganDepartment of Electrical and

Electronic EngineeringUniversity College Cork

Cork, IrelandEmail: jhannon@pei.ucc.ie

Abstract— In an RF system power amplifiers (PAs) typi-cally consume the most power. This paper presents a buckconverter design optimised for a wideband code divisionmultiple access (WCDMA) PA. The design approach takenfocuses on the optimization of switch sizing based on theoverall power losses of the system including the outputinductor losses. The converter is optimised for 20 MHzswitching and output currents in the range of 200-500mA. Experimented results are presented on the fabricatedconverter, with a maximum measured efficiency of 82%.

I. INTRODUCTION

In a dc/dc buck converter, increasing the switchingfrequency results in reduced output voltage ripple andfaster dynamic response; however, a trade-off must bemade between efficiency and switching frequency. Cur-rently the trend for portable electronics devices such asmobile/cell phones is to increase the number of newfeatures in an ever decreasing size; however, this has theeffect of reducing the volume available for the powersupply and battery. Consequently, a reduction in powersupply output voltage ripple is desirable due to theresulting volume reduction that can be achieved usingsmaller passive devices. This is particularly true forthe inductor and capacitor in the low-pass filter. Thedesign described here is a monolithic dc-dc converter fora radio frequency power amplifier (RFPA) application.With WCDMA, the modulation scheme requires a linearPA that is an ‘always-on’ type of architecture. Fig. 1shows the transmission power probability for a WCDMAusage profile [1] [2] [3]; from this figure it can beseen that most of the demand is for power levels below20 dBm. Therefore, optimising the converter designefficiency for lower loads can result in longer batterylife than optimising the efficiency at the highest load.

Fig. 1. TX Power Probability for WCDMA.

The optimisation model described in this paper is anevolution of an earlier model [4], the main differencebeing that the losses in the inductor are included allowingthe full system to be optimised rather then just the powertrain. The main sections of this paper are: Section IIdescribes the steps taken to optimise the converters effi-ciency; Section III details the overall circuit architecture;Section IV presents the simulation results for the powertrain while Section V shows the measured results for thefabricated IC.

II. OPTIMISATION

There are a number of non-idealities that ac-count for power losses in switched mode converters[4] [5] [6] [7] [8]. The two main loss mechanismsare static and dynamic power losses. Static losses are

978-1-422-2812-0/09/$25.00 ©2009 IEEE 503

TimeDead

Cin

Low SidePower Device

Switch Node

PWMIout

Iin

Load

LS Driver

HS Driver

Power Device

Filter

Power Device

LC

High SideAuxiliaryHigh Side Vin

Vout

Control Interface

10+ MHz

Fig. 2. Block Diagram of Chip.

accounted for by on-state conduction losses. Dynamiclosses consist of gate driver losses, crossover switchinglosses, dead time losses, drain-source capacitive switch-ing losses and body diode reverse recovery losses. Tooptimise the switch sizing, the length of the switch wasset to its minimum value for the chosen process andlosses were calculated for a range of switch widths. Inthis design, instead of just optimising the power train thefull system was optimised. The power loss calculationswere further enhanced to include the losses from a set ofcommercially available inductors. To calculate the DClosses in the inductor the RMS voltage and current isfirst calculated for a given frequency. From this the DCpower losses can be caculated using P = V × I . For theAC losses the first 20 harmonics was considered and thetotal losses summed.

III. CIRCUIT ARCHITECTURE

A block diagram of the implemented converter isshown in Fig. 2. The main blocks for this converter are:a digital pulse-width modulator and control interface;delay circuitry; driver circuits; power devices and an in-put capacitor. Closed-loop control has been implementedoff-chip to allow maximum design flexibility. To controlthe converter, a 32-bit value is loaded into a digitalregister which sets the frequency, duty cycle and deadtime. The digital pulse width modulator allows for bothfrequency and duty cycle adjustment, with a maximumfrequency of above 30 MHz and a duty-cycle range ofbetween 5% and 100%. The dead time circuit sets deadtimes from approximately 0 to 5 ns in increments of150 ps. The gate drives comprise of a tapered bufferarrangement that uses a minimum number of stages inorder to reduce the power dissipation [9]. An on-chip

decoupling capacitor Cin yields a number of benefits,one of which is to provide a local reservoir of chargeto the power switches. Also the decoupling capacitorcan reduce radiated emission over a wide frequencyrange [10]. Additionally, the decoupling capacitor helpsto control the resonance frequency associated with thebond wires connecting the IC to its package. A bondwire with a diameter of 25 µm has approximately 2 nHof inductance per mm [11] with an associated resonancefrequency given by:

f =1

2π√LC

. (1)

Careful attention must be paid to the interaction ofswitching frequency, bond wire length and the packageparasitic which may excite a resonance in the powerpath [12] [13]. A method to avoid this is to choose adecoupling capacitor with a value such that the resonantfrequency is pushed far above or far below the switchingfrequency.

To increase efficiency for light and medium loads itis beneficial to use more than one top-switch device[14] [15] [16]. At light loads the high power consumptionof high frequency gate drivers reduces overall efficiency.The trade-off between a desire for low on-resistance andpower dissapation from the gate drivers can be overcomeby adding an extra top switch and implementing abanking strategy. The banking strategy is based on theuse of an extra top switch at higher load to increaseefficiency. In Fig. 2 the banking switch is shown as theauxiliary switch. One top switch is permanently enabledwith the auxiliary switch enabled when the load requiresa higher current.

978-1-422-2812-0/09/$25.00 ©2009 IEEE 504

Fig. 3. Efficiency Simulations for 20 MHz.

IV. SIMULATION RESULTS

This section shows the results for the power trainand inductor. The efficiency for the system has beensimulated using a 10 Ω load to mimic a typical WCDMAPA requirment. Fig. 3 shows the results for 20 MHzswitching with and without the banking switch enabled.From the simulations it can be seen that for light loadsa single top switch in the converter is more efficient,whereas for medium to higher loads adding the extratop switch increases efficiency. Fig. 4 shows simulatedresults with switching frequencies of 10, 20 and 30MHz. It is seen from the simulations that a 10 MHzswitching frequency is the most efficient which is to beexpected with the lower switching losses. Fig. 5 showssimulated results with different output inductors used.The inductor with a value of 421 nH has the best overallperformance, with the 101 nH inductor having betterhigh load efficiencies due to its lower DC resistance,but its low load efficiences are lower due to a higherripple and hence higher AC losses.

V. MEASURED RESULTS

The IC was designed and fabricated based on a 0.35µm process and the layout of the chip is shown in Fig. 6.It has been packaged in a QFN package shown in Fig. 7along with the test PCB.

Waveforms taken from the packaged die are displayedin Fig. 8, which shows the switch-node signal and alsothe input voltage Vin. Fig. 9 shows the high-side andlow-side gate drive signals.

Fig. 4. Efficiency Predictions with Banking for Varied Frequency.

Fig. 5. Efficiency Simulations for Different Inductors.

Fig. 6. Die Layout.

978-1-422-2812-0/09/$25.00 ©2009 IEEE 505

Fig. 7. Test Board with QFN packaged die.

10 ns

Switch Node

Vin

Fig. 8. Switch Node and Vin Measurements.

Measured efficiencies are shown in Fig. 10 throughFig. 14. Fig. 10 shows the measured efficiencies withoutbanking for 10 MHz, 20 MHz and 30 MHz with Vin at3 V and Vout at 1.5 V. Fig. 11 shows varied frequencywith the banking enabled. From these results it can beseen that the most efficient operation is at 10 MHz asexpected from theory. Fig. 12 shows the efficiency for theload set to 10 Ω. Fig. 13 shows the effect of dead-timeadjustment on efficiency. It is clear that smaller deadtimes are more efficient at light loads whereas largerdead times improve the efficiency at higher loads. Fig. 14shows measured efficiencies for three different inductorvalues; this shows that the 421 nH inductor is the mostefficient overall and as predicted the 101 nH inductorwith its lower DC resistance has higher efficiency at

10 ns

HS Drive

LS Drive

Fig. 9. Gate-drive Signals.

Fig. 10. Efficiency Plot without Banking for Varied Frequency.

higher loads. Fig. 15 shows efficiencies for varied outputvoltages. The measured efficiencies for the 10 Ω loadshow the optimum crossover load current for the bankingswitch to be at approximately 100 mA and this compareswell with simulated results.

VI. CONCLUSION

This paper has presented a 20 MHz, 200-500 mA,monolithic buck dc/dc converter. The converter has beenotpimised for a WCDMA PA with particular attentionpaid to regions of most likely operation to extend bat-tery life time. The buck converter was designed andfabricated based on a 0.35 µm CMOS process. Effi-

978-1-422-2812-0/09/$25.00 ©2009 IEEE 506

Fig. 11. Efficiency Plot with banking for Various frequencies.

Fig. 12. Efficiency for 10Ω load at 20 MHz.

ciency measurements have been carried out at differentfrequencies and also with a 10 Ω constant resistive loadto emulate the PA power demand. A maximum measuredefficiency of 82% was achieved at a switching frequencyof 20 MHz.

ACKNOWLEDGMENT

This work was sponsored by Enterprise Irelandthought the Power Electronics Industry Group initiative,contract # ILRP/05/PEIG/4.

Fig. 13. Efficiency for Various dead-times at 20 MHz.

Fig. 14. Efficiency for Varied Inductors.

REFERENCES

[1] N. Karim and A. P. Agrawal, “Powering RF PowerAmplifiers with Magnetic Buck Converters.” WorldWide Web electronic publication. [Online]. Available:http://www.national.com/onlineseminar/

[2] T. Fowler, K. Burger, N.-S. Cheng, A. Samelis, E. Enobakhare,and S. Rohlfing, “Efficiency improvement techniques at lowpower levels for linear CDMA and WCDMA power amplifiers,”in Radio Frequency Integrated Circuits (RFIC) Symposium,2002 IEEE, Seattle, WA, June 2–4, 2002, pp. 41–44.

[3] A. B. Raju, “Characterization of uplink transmit power and talktime in wcdma networks,” Master of Science, Dept. of ElectricalEngineering, Virginia Polytechnic Institute and State University,2008.

978-1-422-2812-0/09/$25.00 ©2009 IEEE 507

Fig. 15. Efficiency for Varied Output Voltages.

[4] J. Hannon, D. O’Sullivan, R. Foley, J. Griffiths, K. G. McCarthy,and M. G. Egan, “Design and optimisation of a high current,high frequency monolithic buck converter,” in Applied PowerElectronics Conference and Exposition, 2008. APEC 2008.Twenty-Third Annual IEEE, Austin, TX, Feb. 24–28, 2008, pp.1472–1476.

[5] S. Mappus, “Predictive gate drive boosts synchronusDC/DC power converter efficiency.” World WideWeb electronic publication, 2003. [Online]. Available:http://focus.ti.com/lit/an/slua281/slua281.pdf

[6] C. S. Mitter, “Device considerations for high current, lowvoltage synchronous buck regulators (SBR),” in WESCON/97.Conference Proceedings, Santa Clara, CA, Nov. 4–6, 1997, pp.281–288.

[7] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model ofpower MOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2,pp. 310–319, Mar. 2006.

[8] S. Chen, O. Trescases, and W. T. Ng, “Fast Dead-time LockedLoops for a high-efficiency microprocessor-load ZVS-QSWDC/DC converter,” in Electron Devices and Solid-State Circuits,2003 IEEE Conference on, Dec. 16–18, 2003, pp. 391–394.

[9] G. Villar, E. Alarcon, J. Madrenas, F. Guinjoan, and A. Poveda,“Energy optimization of tapered buffers for CMOS on-chipswitching power converters,” in Circuits and Systems, 2005.ISCAS 2005. IEEE International Symposium on, May 23–26,2005, pp. 4453–4456.

[10] T. Sudo and M. Bonkohara, “Simulation of Reduction Proper-ties of Radiated Emission by On-chip Decoupling Capacitor,”in Signal Propagation on Interconnects, 6th IEEE Workshop on.Proceedings, Pisa, May 12–15, 2002, pp. 15–18.

[11] N. Karim and A. P. Agrawal, “Plastic PackagesElectrical Performance: Reduced Bond Wire Diameter.”World Wide Web electronic publication. [Online]. Available:http://www.amkor.com/services/electrical/bondwire.cfm

[12] P. Larsson, “Resonance and damping in CMOS circuits with on-chip decoupling capacitance,” IEEE Transactions on Circuitsand Systems I: Fundamental Theory and Applications, vol. 45,no. 8, pp. 849–858, Aug. 1998.

[13] N. Na, T. Budell, C. Chiu, E. Tremble, and I. Wemple, “The

effects of on-chip and package decoupling capacitors and anefficient ASIC decoupling methodology,” in Electronic Com-ponents and Technology Conference, 2004. Proceedings. 54th,vol. 1, June 1–4, 2004, pp. 556–567.

[14] R. K. Williams, W. Grabowski, A. Cowell, M. Darwish, andJ. Berwick, “The dual-gate W-switched power MOSFET: anew concept for improving light load efficiency in DC/DCconverters,” in Power Semiconductor Devices and IC’s, 1997.ISPSD ’97., 1997 IEEE International Symposium on, Weimar,May 26–29, 1997, pp. 193–196.

[15] O. Trescases, W. T. Ng, and G. Wei, “Integrated SwitchedMode Power Supplies Using Digital Controllers,” in Solid-State and Integrated Circuit Technology, 2006. ICSICT ’06. 8thInternational Conference on, 2006, pp. 1614–1617.

[16] S. Musunuri and P. L. Chapman, “Improvement of light-loadefficiency using width-switching scheme for CMOS transistors,”IEEE Power Electronics Letters, vol. 3, no. 3, pp. 105–110,Sept. 2005.

978-1-422-2812-0/09/$25.00 ©2009 IEEE 508