The World Leader in High Performance Signal Processing Solutions

Simplifying Radio Design Using a Wideband

IF Receiver Subsystem IC

Presented by: Paul Hendriks

Applications Engineer February 2015

AGENDA

Overview of Wideband Heterodyne Radio Using IF Sampling

Design Challenges for Next Generation “Reconfigurable” Receivers

Example of “Industry Leading” High Dynamic Range Radio

Overview of Enabling IF Rx Subystem IC

Support Tools facilitating quick evaluation and prototyping

Q & A Session

2

Heterodyne Wideband Digital Receiver

Heterodyne Receiver

Most widely deployed receiver for high performance receivers

Architecture (and limitations) are well understood.

IF Sampling ADC’s (introduced in late 1990’s) eliminated need for second down conversion stage

While advances in Direct Conversion Receivers are being made………challenges still remain to achieve SFDR<<-80 dBc

The Challenge Moving Forward

RF Bandwidth’s continue to increase (from 20 MHz to 160+MHz)

One SDR Platform covering wide range of RF bands (0.7-3.8 GHz)

ATT

RF

SAW

DGA

IF

SAW

Image-Reject

Filter High Order

LC LPF Duplexer

3

The Wireless Environment is a Harsh Place!

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New wideband standards (LTE) co-existing with old ones (GSM)

Co-location, self-blockers from transmitter in FDD (i.e. Tx Leakage)

High User Demand with High Quality of Service Demands

Consider Superbowl 2015 and usage right after game ended!

It all has to work……and receiver dynamic range is key!!

http://www.analog.com/AD6676

“IF-Sampling” Digital Receiver Challenges

IF Signal Path Complexity

IF Filtering due to ADC Nyquist Constraints (i.e. FS/2)

“Lossy” 15+ dB IF SAW Filter and Higher Order LC LPF

AGC Control….especially if RF/IF AGC used in tandem

Goal: Maximize Receivers “Instantaneous Dynamic Range” to increase AGC threshold level (i.e. reduce probability of its use)

IF Strip’s PCB Area and Power Consumption

More components>>>More space and power!!

IF Frequency Planning

ATT

RF

SAW

DGA

IF

SAW

IR

Filter

High Order

LC LPF

5

IF Frequency Planning Constraints

IF selection for Multi-band/mode radio has its challenges!!!!

Mixer Spurious and “Image Bands”

High vs Low Side Injection (IF/2, IF/3)

ADC Nyquist Zone and Aliasing of Spurs

PLL Spurious (Reference spurs)

The IF constraint “Cube” shrinks with increasing RF BW!!!

A High OSR ADC expands IF choices!!!

Oversampling (OSR) = FS/2*BW

High OSR (w/ digital filtering) reduces IF filtering!!

IF can be optimized for mixer and PLL

Aliasing and close in Mixer spurs (2x2) are not an issue

6

Mixer

Spurious

PL

L S

pu

rio

us

ADC Nyquist Zone/

Aliasing Spurious

Suitable

IF’s

(>BW)

Mixer MxN Spurious

Mixer Spur Charts or CAD tools help identify potential suitable IF’s

Mixer Spur Tables

Often provided on datasheet for popular RF and IF combinations as well as other characterization provide insight on a mixer’s behavior.

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N/M

(N-M

)/M

M

N

ADC Nyquist and Alias Spurious

8 8

Mixer Spur Charts or CAD tools help identify potential suitable IF’s

Mixer Spur Tables

Often provided on datasheet for popular RF and IF combinations as well as other characterization provide insight on a mixer’s behavior.

Mixer MxN Spurious and ADC Nyquist

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200 MSPS ADC Nyquist Zone

1st 2nd 4th 3rd 5th 6th 7th 8th 9th 10th

Mixer

2x2 Mixer

3x3

Swept CW @ -1 dBm Output

SA Set to “Peak Hold”

ADL5355 Mixer Output w/ LO=1550 MHz and IF=250 MHz

RF tone swept from 1774 to 1826 MHz (Peak Hold for Spec. Ana.)

Nyquist Zones=100 MHz for 200 MSPS ADC, IF centered in 3rd

For RF BW’s >50 MHz, Mixer’s 2X2 sets LPF transition band

95 dB SFDR requires extra 27 dB rejection under an octave!!

LPF

27dB

Mixer MxN Spurious and ADC Nyquist (cont.)

IF Sampling ADC’s have Input BW’s of 800+ MHz

Mixer “M x LO” harmonics are visible by ADC

LO Leakage (0,1)…. lots of suppression if aliasing back into ADC IF

Other spurious can also be problematic for <-95 dB SFDR

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0,1

“LO” 0,2

“2xLO” 0,3

1,-1

“IF”

Benefit of High Oversampling ADC

Larger Mixer MxN products fall “out-of-band”….no aliasing!!

IF frequency planning still applies for MxN terms that fall “in-band

Mixer IMD still an issue

Digital filtering removes out-of-band noise spurs

BPSDADC Output Before Filtering BPSDADC Output After Filtering

FADC=3200 MSPS

FIQ=100 MSPS

Dec-by-32

11

PCB Area……If Size Really Matters!

Industry Trend

Higher integration, Lower Size/Power, Higher Performance

What if a Rx IF Subsystem could result in

70% PCB savings with lower BOM

30+% in Power Savings

And…………….More Dynamic Range!!!!

>70% smaller

PCB Area

AAF IF SAW

5x7mm ADC

7x7mm

Mixer

5x5mm DGA

5x5mm IF Sub-

system Mixer

5x5mm

10 mm x 15 mm 12 mm x 45 mm

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Seeing is Believing!

High Performance Receiver Example

(RF=1800, LO=1550, IF=250, BW=40, CLK=3200, FDATA_IQ

=100 MSPS)

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Mixer LPF

IF Rx

Sub-

sytem IC

15 mm

10

mm

High AGC-free Dynamic Range

w/ NF<16 dB and PIN_0dBFS=0 dBm

NF=16 dB

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High Linearity Performance with 2-Tone

IMD=-84 dBc ( IIP3=34 dBm)

(

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http://www.analog.com/AD6676

Excellent Swept Spurious Performance

(Frequency Planning Required)

CW swept from

1750 to 1850 MHz

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http://www.analog.com/AD6676

Passband Flatness of +/-0.2 dB

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AD6676 Wideband IF Receiver Subsystem

Enables Breakthrough Direct VHF or heterodyne UHF Rx Architectures

Industry leading Dynamic Range

NSD of -160 dBFS/Hz, IMD3 of -96dBc

IIP3 up to 36dBm, NF of 13dBm

Swept Spurious < -99 dBFS

Nominal PIN_0dBFS = -2 dBm

Adjustable over +13 to -14 dBm range

Easy to drive ZIN of 60 ohms

Based on “Reconfigurable” oversampled BP ΣΔ ADC technology

Eliminates SAW filter, DGA and IF Gain

PCB area savings up to 70%

“Simple” RF-to-IF mixer interface with LPF

Very wide tunable IF/BW Rx platform

Same mixer-to-bits line-up can support 0.7-3.8 GHz

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4.3mm

5.0mm

AD6676 Wideband IF Receiver Subsystem

Enables “Reconfigurable” Wideband IF Rx Subsystem

Support Direct Sampling VHF or Heterodyne UHF Receivers

IF Frequency tunable from 70-450 MHz

Usable Passband BW tunable from 20-160 MHz

“Profile Feature” allows up to 4 different IF/BW combinations that can be switched within 1 µsecond

High Level of Integration/Functionality

IF Digital Attenuator with AGC Support (Detection/Gain Control)

High Dynamic Range SDADC

On-chip DSP includes QDDC and Decimation filters

I/Q 16-bit data via 1 or 2 lane JESD204B interface

Optional Clock Synthesizer (2.94-3.2 GHz operation)

Power Consumption of 1.2 W (w/ 1.1 V and 2.5 V supplies

Mixer-to-bits Rx chain of < 2 W (w/ mixer+PLL/VCO)

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ΔΣ

ADC CORE

What is the AD6676? (cont.)

ATT Decimation

filter

JESD204B

Serializer

I

Q

I

Q QDDC

Analog Digital Only conceptual, inherent

in the SD ADC design

Inherent Anti-alias Filter

Quantization Noise Shaping

Quadrature Downconversion

and Digital Filtering

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Reconfigurable BP SD ADC

“Application Parameters”

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NSD vs Oversampling Ratio Trade-off

Higher OSR results in lower NSD performance

Lower/Upper “Zeros” of NTF become further a part

Less forward gain in feedback loop to suppress ADC quantization noise (recall only 17-level ADC).

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“Profile Feature” allows up to 4 different

IF/BW combinations

User quickly switch between different pre-saved ADC configurations (i.e. Wideband vs Narrowband Modes)

Calibration of each profile configuration done at power-up

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Digital Processing Blocks

QDDC (Coarse/Fine) followed by selectable Decimation Filters

Dec Factors of 12, 16, 24, and 32

AGC/Overload Detection and Control.

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Want to Learn More? Visit the AD6676 Website

http://www.analog.com/ad6676

25

“LIVE”

WEB DEMO

TOOL!!

Try Before You Buy!!!

AD6676 Remote Test Tool

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AD6676 Remote Test Tool Capability

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Single-Tone Dual-Tone

Frequency Sweep Spurious vs Frequency Sweep

Not Shown: In-band Noise vs Amp Sweep

AD6676 Evaluation Platform

“Plug and Play and User-friendly” FMC-Compatible EVB

Requires no external generators/supplies to get operational!

Sophisticated Evaluation SW based on MATLAB Executable

Provides various analysis tools: enables detailed customer evaluation

Saves SPI initialization files for rapid software development

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AD6676 Evaluation Platform (cont.)

Sophisticated Evaluation SW based on MATLAB Executable Provides various analysis tools: enables detailed customer evaluation

Saves SPI initialization files for rapid software development

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Support Rapid FPGA Proto-typing with

AD6676 FMC EVB

Facilitate transition from AD6676 evaluation to software/firmware development using same EVB

Dedicated Wiki page includes HDL firmware, software, documentation.

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FPGA HDL Code and Linux Drivers

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http://wiki.analog.com/resources/tools-software/linux-

drivers/iio-adc/ad6676

https://github.com/analogdevicesinc/hdl/tree/dev/projects/ad6676evb

Product Availability

32

AD6676

Samples: Now

Production Quantities:

AD6676BCBZRL Now

1K pricing

AD6676BCBZRL $145

Evaluation and Prototyping Boards:

AD6676EBZ $395

HSC-ADC-EVALEZ data capture kit $750

http://www.analog.com/AD6676

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