9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and...
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Transcript of 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and...
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 1
Decoders and Multiplexer Circuits
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 2
Class 17 – Arithmetic Functions Iterative Combinational Circuits Binary Adders
Material from section 4-1 and 4-2 of text
Iterative Circuits The concept – Create a functional block and
create the circuit for doing the multiple bit operation by simply repeating it.
Another concept to be introduced – circuit contraction where you fix the value of some inputs and then can simplify the resulting circuit. Examples are incrementing, decrementing or multiplying by a constant.
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 3
Iterative Circuit Consider an iterative circuit that operates on
two binary vectors. Base unit
Iterative connection.
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 4
Iterative circuit area A lot in arithmetic area of application.
Adders Subtractors Incrementors Decrementors Multiplication circuits
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 5
Binary Adders Consider adding 2 binary digits. Can specify the requirement in a truth table.
A combinational circuit that adds two input bits is called a half adder.
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 6
Half adder equations The Sum and Carry equations
Implementation
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 7
S = X’Y + XY’ = X Y
C = XY
The full adder Can evolve half adder into a full adder. Full adder truth table and minimization.
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 8
S=X’Y’Z+X’YZ’+XY’Z’+XYZ = X Y Z = (X Y) Z
The full adder continued The carry minimization
Implementation
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 9
C = XY +XY’Z +X’YZ = XY +Z(XY’+X’Y) = XY + Z(X Y)
The full adder Have just seen a full adder implemented from the
structural connection of two half adders and an OR gate.
Can do a direct implementation. It will end up with the same number and type of gates.
For a multibit implementation need a symbol for the unit.
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 10
Multibit use And then can use that symbol in multibit or
hierarchical representations. A 2 bit example
In this adder the final output carry is generated in the final stage after the carry inputs to all the previous stages has settled.
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 11
Carry ripple So the carry ripples from the lsb to msb A
ripple carry adder.
All inputs, As,Bs, and C0 arrive – C1 becomes valid – C2 becomes valid – C3 becomes valid – C4 becomes valid -
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 12
Class 17 assignment Covered sections 4-1 through 4-2 Problems for hand in
none Problems for practice
4-2
Reading for next class: sections 4-3, 4-4
9/15/09 - L15 Decoders, Multiplexers
Copyright 2009 - Joanne DeGroat, ECE, OSU 13