9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU1 Flip Flops Not a gymnastic...

9/15/09 - L20 Flip Flops Copyright 2009 - Joanne DeGroat, ECE, OSU 1

Flip FlopsNot a gymnastic movement.


Class 20 – Flip Flops Definitions Latches

Set-Reset – SR The D Latch

Material from section 5-3 of text

Triggers When the control input to a flip-flop changes

value the state of the latch in the flip-flop will change state.

In a D-latch when the control input is a ‘1’, any changes on the input D will propagate to the output with the value of D at the time the control transitions from ‘1’ the final stored value.

In a D flip-flop, the value on D on the rising edge (falling edge) of the control input will be the captured value.


Flip-flops Constructed in such a way that they are edge-

triggered. This is in contrast to latches which are level

sensitive and said to be transparent.

There are two general methodologies for making flip-flops Edge-triggered Master-Slave


Master Slave Flip-flops The Master-Slave SR Flip-flop

And its operation


Master Slave D Flip-flop Can be constructed from the MS SR FF by

replacing the master SR latch by a D latch. This arrangement is also negative edge

triggered.


A HDL model of the same The SR latch

model with control input C


ENTITY SR_latch IS PORT (S,R,C : IN BIT; Q, Q_bar : OUT BIT);END SR_latch;ARCHITECTURE one OF SR_latch IS SIGNAL CS,CR : BIT; SIGNAL Q_int, Q_bar_int : BIT;BEGIN CS <= S nand C after 1 ns; CR <= R nand C after 1 ns; Q_int <= CS nand Q_bar_int after 1 ns; Q_bar_int <= CR nand Q_int after 1 ns; Q <= Q_int; Q_bar <= Q_bar_int;END one;

A testbench to provide stimulus tb model Links in the latch

in a master slave manner


ENTITY tb IS END tb; ARCHITECTURE one OF tb IS SIGNAL Clk,nClk,S,R,D : BIT; SIGNAL i1,i2 : BIT; SIGNAL SRq,SRqbar : BIT; COMPONENT SR_latch PORT (S,R,C : IN BIT; Q,Q_bar : OUT BIT); END COMPONENT; FOR ALL : SR_latch USE ENTITY work.sr_latch(one); BEGIN -- gen clock signals Clk <= not Clk after 10 ns; nClk <= not Clk after 1 ns; -- wire in master slave FF SRm : SR_latch PORT MAP(S,R,Clk,i1,i2); SRs : SR_latch PORT MAP(i1,i2,nClk,SRq,SRqbar); PROCESS BEGIN S<='0'; R<='0'; WAIT FOR 10 ns; S<='1'; R<='0'; WAIT FOR 20 ns; S<='0'; R<='0'; WAIT FOR 10 ns; S<='0'; R<='1'; WAIT FOR 20 ns; S<='0'; R<='0'; WAIT FOR 50 ns; S<='1'; R<='0'; WAIT FOR 20 ns; S<='0'; R<='0'; WAIT FOR 10 ns; WAIT; END PROCESS; END one;

VHDL simulation results Waveform display


The D Flip-flop The D can be constructed from the use of a D

latch and an SR latch.


For a positive edge FF Add an inverter to the clock input


HDL model and simulation A HDL model of the D latch was written.


ENTITY dlatch IS PORT (D,C : IN BIT; Q,Q_BAR : OUT BIT); END dlatch; ARCHITECTURE one OF dlatch IS SIGNAL S_bar, R_bar, D_bar : BIT; SIGNAL Q_int, Q_bar_int : BIT; BEGIN S_bar <= D nand C after 1 ns; R_bar <= D_bar nand C after 1 ns; D_bar <= not D after 1 ns; Q_int <= S_bar nand Q_bar_int after 1 ns; Q_bar_int <= R_bar nand Q_int after 1 ns; Q <= Q_int; Q_BAR <= Q_bar_int; END one;

HDL simulation Results now for the D F/F Remember the delays


Flip flop with preset and clear

9/15/09 - L20 Flip Flops

Allows direct setting of state of flip-flop. When initially powered state of flip-flop is

unknown. The sets the FF to a known state.

Copyright 2009 - Joanne DeGroat, ECE, OSU 14

Class 20 assignment Covered sections 5-1 and 5-2 Problems for hand in

L20 HW (on webpage) Problems for practice

none

Reading for next class: sections 5-4


9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU1 Flip Flops Not a gymnastic...

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