9 Experiment of Vlsi

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Shri Venkteshwar Institute Of Technology, IndoreDEPARTMET O! E"E#TROI#S AD #OMM$I#ATIO

V"SI Design %E# & '()*

E+PERIMET O - (.

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T/EOR01 -

A full adder is a logical circuit that performs an addition operation on three binary digits. The

full adders produce a sum and carry value, which are both binary digits.

V/D" code1

library IEEE;use IEEE.T!"#$%I&"11'(.A##;

use IEEE.T!"#$%I&"A)IT*.A##;

use IEEE.T!"#$%I&"+I%E!.A##;entity fadder is

port a,b,cin in bit; s,cout out bit/;

end fadder;architecture 0ehavioral of fadder is

begins 2 a 3or b 3or cin;

cout 2 a and b/ or a and cin/ or b and cin/;end 0ehavioral;

TR$T/ TA2"E 1 -

In3ut Out3ut

#in 2 A S #out

4 4 4 4 44 4 1 1 4

4 1 4 1 4

4 1 1 4 11 4 4 1 41 4 1 4 1

1 1 4 4 1

1 1 1 1 1

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PRO:RAM1 -

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DEM$"TIP"E+ER1 -

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T/EOR01 -

A multiple3er or mu3 is a device that performs multiple3ing; it selects one of many analog or

digital input signals and outputs that into a single line. In digital circuit design, the selector wiresare of digital value. The number of selector pins is eual to #og5n/


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T/EOR01 -

A demultiple3er !>+?/ is a device which essentially performs the opposite operation to the

>+?. That is, it functions as an electronic switch to route an incoming data signal to one ofseveral outputs.

V/D" #odeentity demultiple3er is

@ort input in std"logic"vector4 downto 4/;s4 in std"logic"vector4 downto 4/;

s1 in std"logic"vector4 downto 4/;

s5 in std"logic"vector4 downto 4/;

o4 out std"logic"vector4 downto 4/;o1 out std"logic"vector4 downto 4/;

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o5 out std"logic"vector4 downto 4/;

o6 out std"logic"vector4 downto 4/;

o( out std"logic"vector4 downto 4/;o7 out std"logic"vector4 downto 4/;

o' out std"logic"vector4 downto 4/;

o8 out std"logic"vector4 downto 4//;end demultiple3er;

architecture 0ehavioral of demultiple3er is

begino4 2 not s4 and not s1 and not s5 and input/;

o1 2 s4 and not s1 and not s5 and input/;

o5 2 not s4 and s1 and not s5 and input/;

o6 2 s4 and s1 and not s5 and input/;o( 2 not s4 and not s1 and s5 and input/;

o7 2 s4 and not s1 and s5 and input/;

o' 2 not s4 and

s1 and s5 and input/;o8 2 s4 and s1 and s5 and input/;

end 0ehavioral;

TR$T/ TA2"E 1 -

A5 A1 A4 $+T

4 4 4 !4

4 4 1 !1

4 1 4 !54 1 1 !6

1 4 4 !(

1 4 1 !71 1 4 !'

1 1 1 !8

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E+PERIMET O - .(

AIM1 - verification of B flip flop.

T/EOR01

The -B flip-flop is the most versatile of the basic flip-flops. It has the input-

following character of the clocCed ! flip-flop but has two inputs,traditionally labeled and B. If and B are different then the output D taCes

the value of at the ne3t clocC edge.

If and B are both low then no change occurs. If and B are both high at theclocC edge then the output will toggle from one state to the other. It can

perform the functions of the setreset flip-flop and has the advantage thatthere are no ambiguous states. It can also act as a T flip-flop to accomplish

toggling action if and B are tied together. This toggle application findse3tensive use in binary counters.

V/D" #ode


use IEEE.T!"#$%I&"A)IT*.A##;use IEEE.T!"#$%I&"+I%E!.A##;

entity FCflipflop is

port , ), ,B, Bin bit; D inout bit; D out bit2G1G/;end FCflipflop;

architecture 0ehavioral of FCflipflop is

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begin

process , ), B/

beginif )2G4G then D2G4G after 14 ns;

elsif 2G4G then D2G1G after 14 ns;

elsif B2G4G and BGevent thenD2 and not D/ or not B and D/ after 14 ns;

end if;

D2 not D;end process;

end 0ehavioral;

TR$T/ TA2"E 1

B D ne3t &omment

4 4 Dprev hold state4 1 4 reset

1 4 1 set1 1 DHprev toggle

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E+PERIMET O - ..

AIM1 - verification of T flip flop.

T/EOR01

The T or toggle flip-flop changes its output on each clocC edge, giving an

output which is half the freuency of the signal to the T input.It is useful for constructing binary counters, freuency dividers, and general

binary addition devices. It can be made from a -B flip-flop by tying both of

its inputs high.

V/D" code1 -

#ibrary IEEE;

use IEEE.T!"#$%I&"11'(.A##;

use IEEE.T!"#$%I&"A)IT*.A##;use IEEE.T!"#$%I&"+I%E!.A##;

entity tflip is

port T, Bin bit; D inout bit; D out bit/;end tflip;

architecture 0ehavioral of tflip is

beginprocess B/

begin

if B2G4G and BGevent then

D2 T and not D/ or not T and D/ after 14 ns;

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end if;

D2 not D;

end process;end 0ehavioral;

TR$T/ TA2"E1 -

T D Dne3t &omment

4 4 4 *old state4 1 1 *old state

1 4 1 Toggle

1 1 4 Toggle

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E+PERIMET O & .4

AIM1 - Jerification of Encoder.

T/EOR01 -

An encoder is a device used to change a signal such as a bit stream/ or data into a code.A single bit ( to 5-encoder taCes in ( bits and outputs 5 bits.

V/D" #ode 1

library IEEE;

use IEEE.T!"#$%I&"11'(.A##;


use IEEE.T!"#$%I&"+I%E!.A##;---- +ncomment the following library declaration if instantiating

---- any ?ilin3 primitives in this code.

--library +II>;--use +II>.J&omponents.all;

entity encoder isporta,b,c,d in bit; 3,y out bit/;

end encoder;

architecture 0ehavioral of encoder isbegin3 2 c or d;

y 2 d or b;

end 0ehavioral;

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TR$T/ TA2"E1

I@+T $+T@+T

I6 I5 I1 I4 $1 $4

4 4 4 1 4 44 4 1 4 4 1

4 1 4 4 1 4

1 4 4 4 1 1

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E+PERIMET O & .5

AIM1 - Jerification of !ecoders.

T/EOR01 -

Adecoder is a device which does the reverse of an encoder, undoing theencoding so that the original information can be retrieved. The same method

used to encode is usually Fust reversed in order to decode.

In digital electronics this would mean that a decoder is a multiple-input,

multiple-output logic circuit that converts coded inputs into coded outputs,

where the input and output codes are different.

It has n inputs and 5n outputs

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V/D" code1 -



use IEEE.T!"#$%I&"+I%E!.A##;entity decoder is

ports1,s5,s6in bit;d1,d5,d6,d(,d7,d',d8,d9out bit/;

end decoder;architecture 0ehavioral of decoder is

begin

d1 2 s1 and s5 and s6;

d5 2 s1 and s5 and not s6/;d6 2 s1 and not s5/ and s6;

d( 2 s1 and not s5/ and not s6/;

d7 2 not s1/ and s5 and s6;

d' 2 not s1/ and s5 and not s6/;d8 2 not s1/ and not s5/ and s6;

d9 2 not s1/ and not s5/ and not s6/;

TR$T/ TA2"E1

!ecimal

!igit 5 1 4 $utputs

!4 !1 !5 !6 !( !7 !' !84 4 4 4 1 4 4 4 4 4 4 4

1 4 4 1 4 1 4 4 4 4 4 4

5 4 1 4 4 4 1 4 4 4 4 46 4 1 1 4 4 4 1 4 4 4 4

( 1 4 4 4 4 4 4 1 4 4 4

7 1 4 1 4 4 4 4 4 1 4 4' 1 1 4 4 4 4 4 4 4 1 4

8 1 1 1 4 4 4 4 4 4 4 1

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9 Experiment of Vlsi

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