VLSI DESIGN LAB - Electronics Club0 ShriRam College of Engineering & Managment National Expressway...

0 ShriRam College of Engineering & Managment

National Expressway (A.B. Road), Banmore

VLSI DESIGN LAB

CONTENTS

S. No. List of Experiment Page

No

1.

Design of CMOS inverter using design architect for NMOS: L=1.5

micrometer, W=2.75 micrometer and for PMOS : L=1.5 micrometer and

W=3.5 micrometer.

01-03

2.

Design of CMOS NAND gate using design architect for NMOS: L=1.5


W=3.5 micrometer.

04-06

3.

Design of CMOS NOR gate using design architect for NMOS: L=1.5


W=3.5 micrometer.

07-09

4.

Design of AND gate using design architect for NMOS: L=1.5


W=3.5 micrometer.

10-12

5.

Design of OR gate using design architect for NMOS: L=1.5 micrometer,

W=2.75 micrometer and for PMOS : L=1.5 micrometer and W=3.5

micrometer.

13-15

6.

Design of XOR gate using design architect for NMOS: L=1.5


W=3.5 micrometer.

16-18

7.

Design of XNOR gate using design architect for NMOS: L=1.5


W=3.5 micrometer.

19-21

Lab In-charge



Experiment No.1

Objective: Design of CMOS inverter using design architect for NMOS: L=1.5 micrometer,

W=2.75 micrometer and for PMOS : L=1.5 micrometer and W=3.5 micrometer.

Steps to write VLSI Design program –

1. Invoke Design Architect IC by using the following command da_ic & Choose the MGC

>Session from the Menu if palette is not present in the open window Select the "Show

Palette" and choose OK.

2. Choose the "Schematic" option from the right side palette.

3. Select the "Library" from the right side palette. Choose the "Device Lib" and select "4-

pin MOS" displayed under the "NMOS" Category.

4. Place 4 terminal NMOS to construct the Inverter.

5. Similarly place 4 terminal PMOS to form the P tree for Inverter as shown in the figure

below. And an interconnection.

6. Choose Add >Wire from Menu and complete the Inverter wiring.

7. Select "Back" from the palette and choose the "Generic Lib".

8. Choose and place the VDD port and GND port.

9. Place the input and output ports by selecting the Portin and Portout from Ports category.

10. Select the input nets and the output nets and assign name by selecting the right click and

"Name nets". Enter the net names as “A, and B" respectively in the "New value" tab.

11. Select the NMOS right click on it. Choose the Properties>Modify Multiple. (OR Select

the NMOS and press "Q" from the keyboard).

12. In the "Edit Properties" window select the ASIM _MODEL and change the value to "N".

13. Scroll down select the "L" property and change it to 2u.

14. Scroll down select the "W" property and change it to 5u.

15. Select the PMOS, right click on it. Choose the Properties>Modify Multiple.

16. In the "Edit Properties" window select the ASIM_MODEL and change the value to "P".

17. Scroll down select the “L” property and change it to 2u.


19. In order to do the simulation, click on start simulation.

20. Eldonet as default Spice simulator and Click ok.

21. Click on library.



22. Assign the path for the model file in the include file path as follows

$ADK/technology/ic/models/ami05.mod

23. Click on Analysis in the right side Palette. Select Transient for analysis; Assign the

parameter in the Transient Analysis sub palette “Setup Transient Analysis”

24. Now Select the Input and output port A& B respectively by pressing the Ctrl tab of

keyboard it will be highlighted as white.

25. Click on Wave Output, Select TRAN in the Analysis option, Select + icon on the right

side to add the input and output ports.

26. After that click on View Waves in the Palette. Wait for a moment it will invoke

EZWAVE viewer, Select the TRAN in time left palette in the EZWAVE window, and

from the bottom palette select the Vin und Vout and drag in the wave region (OR double

click on the Vin And Vout).

27. Congratulation!!! Here you finished your lab design, which was Schematic design Entry

using Design Architect Tool (da_ic), and Simulation with ELDO tool.



Waveforms-

-------------------------------



Experiment No.2

Objective: Design of CMOS NAND gate using design architect for NMOS: L=1.5

micrometer, W=2.75 micrometer and for PMOS : L=1.5 micrometer and W=3.5

micrometer.


1. Invoke Design Architect IC by using the following command da_ic &

2. Choose the MGC >Session from the Menu if palette is not present in the open

window Select the "Show Palette" and choose OK.


4. Select the "Library" from the right side palette. Choose the "Device Lib" and select

"4- pin MOS" displayed under the "NMOS" Category.

5. Place 4 terminal NMOS to construct the NAND gate.

6. Similarly place 4 terminal PMOS to form the P tree for Inverter as shown in the

figure below. And an interconnection.




10. Place the input and output ports by selecting the Portin and Portout from Ports

category.

11. Select the input nets and the output nets and assign name by selecting the right click

and "Name nets". Enter the net names as “A, and B" respectively in the "New value"

tab.

12. Select the NMOS right click on it. Choose the Properties>Modify Multiple. (OR

Select the NMOS and press "Q" from the keyboard).

13. In the "Edit Properties" window select the ASIM _MODEL and change the value to

"N".




17. In the "Edit Properties" window select the ASIM_MODEL and change the value to

"P".














26. Click on Wave Output, Select TRAN in the Analysis option, Select + icon on the

right side to add the input and output ports.


EZWAVE viewer, Select the TRAN in time left palette in the EZWAVE window,

and from the bottom palette select the Vin und Vout and drag in the wave region

(OR double click on the Vin And Vout).

28. Congratulation!!! Here you finished your lab design, which was Schematic design

Entry using Design Architect Tool (da_ic), and Simulation with ELDO tool.



Waveforms-

------------------------------



Experiment No.3

Object: Design of CMOS NOR gate using design architect for NMOS: L=1.5

micrometer, W=2.75 micrometer and for PMOS : L=1.5 micrometer and W=3.5

micrometer.


1. Invoke Design Architect IC by using the following command da_ic & Choose the

MGC >Session from the Menu if palette is not present in the open window Select

the "Show Palette" and choose OK.


3. Select the "Library" from the right side palette. Choose the "Device Lib" and select

"4- pin MOS" displayed under the "NMOS" Category.

4. Place 4 terminal NMOS to construct the NOR gate.

5. Similarly place 4 terminal PMOS to form the P tree for Inverter as shown in the

figure below. And an interconnection.




9. Place the input and output ports by selecting the Portin and Portout from Ports

category.

10. Select the input nets and the output nets and assign name by selecting the right click

and "Name nets". Enter the net names as “A, and B" respectively in the "New value"

tab.

11. Select the NMOS right click on it. Choose the Properties>Modify Multiple. (OR

Select the NMOS and press "Q" from the keyboard).

12. In the "Edit Properties" window select the ASIM _MODEL and change the value to

"N".






16. In the "Edit Properties" window select the ASIM_MODEL and change the value to

"P".




20. Eldonet as default Spice simulator.

21. Click ok.






25. Click on Wave Output, Select TRAN in the Analysis option, Select + icon on the

right side to add the input and output ports.


EZWAVE viewer, Select the TRAN in time left palette in the EZWAVE window,

and from the bottom palette select the Vin und Vout and drag in the wave region

(OR double click on the Vin And Vout).

27. Congratulation!!! Here you finished your lab design, which was Schematic design

Entry using Design Architect Tool (da_ic), and Simulation with ELDO tool.



Waveforms-

-------------------------------



Experiment No.4

Object: - Design of AND gate using design architect for NMOS: L=1.5 micrometer, W=2.75

micrometer and for PMOS : L=1.5 micrometer and W=3.5 micrometer.






3. Select the "Library" from the right side palette. Choose the "Device Lib" and select "4- pin

MOS" displayed under the "NMOS" Category.

4. Place 4 terminal NMOS to construct the AND gate.









11. Select the NMOS right click on it. Choose the Properties>Modify Multiple. (OR Select the

NMOS and press "Q" from the keyboard).

















24. Now Select the Input and output port A& B respectively by pressing the Ctrl tab of keyboard

it will be highlighted as white.

25. Click on Wave Output, Select TRAN in the Analysis option, Select + icon on the right side

to add the input and output ports.

26. After that click on View Waves in the Palette. Wait for a moment it will invoke EZWAVE

viewer, Select the TRAN in time left palette in the EZWAVE window, and from the bottom

palette select the Vin und Vout and drag in the wave region (OR double click on the Vin

And Vout).





Waveforms-

-------------------------------



Experiment No.5

Object: - Design of OR gate using design architect for NMOS: L=1.5 micrometer, W=2.75









4. Place 4 terminal NMOS to construct the OR gate.


































And Vout).





WAVEFORMS-

-------------------------------



Experiment No.6

Objective: Design of XOR gate using design architect for NMOS: L=1.5 micrometer, W=2.75


1. Steps to write VLSI Design program –





3. Select the "Library" from the right side palette. Choose the "Device Lib" and select "4-

pin MOS" displayed under the "NMOS" Category.

4. Place 4 terminal NMOS to construct the XOR gate.









11. Select the NMOS right click on it. Choose the Properties>Modify Multiple. (OR Select

the NMOS and press "Q" from the keyboard).









20. Eldonet as default Spice simulator and click ok.










25. Click on Wave Output, Select TRAN in the Analysis option, Select + icon on the right

side to add the input and output ports.


EZWAVE viewer, Select the TRAN in time left palette in the EZWAVE window, and

from the bottom palette select the Vin und Vout and drag in the wave region (OR double

click on the Vin And Vout).





Waveforms-

-------------------------------



Experiment No.7

Objective: Design of XNOR gate using design architect for NMOS: L=1.5 micrometer,

W=2.75 micrometer and for PMOS : L=1.5 micrometer and W=3.5 micrometer.

1. Steps to write VLSI Design program –

1. Invoke Design Architect IC by using the following command da_ic & choose the MGC






4. Place 4 terminal NMOS to construct the XNOR gate.



















20. Eldonet as default Spice simulator.

21. Click ok and click on library.














And Vout).





waveforms-

-------------------------------

VLSI DESIGN LAB - Electronics Club0 ShriRam College of Engineering & Managment National Expressway...

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