8086 UNIT-1

8086 1

8086-Architecture• Functional and Internal block schematic of

8086

• Features of 8086

• Register organization of 8086

• Memory organization of 8086

8086 2

S

Y

S

T

E

M

B

U

S

Timing

Central processing

unit

BusControl

logic

Memorymodule

MemoryModule

InterfaceMass

Storagedevice

InterfaceI/O

device

Interface

Interface

I/O subsystem

Memory

Architecture of an typical microprocessor based system

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Typical Microprocessor based system

A typical microprocessor based system consists of CPU (central Processing Unit)

(ALU + Register organization + Control unit) Timing unit Bus control logic Memory I/O subsystem

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Features of 8086

• Introduced in 1978 .• Comes in Dual-In-Line Package(DIP) IC.• 8086 is a 16-bit N-channel HMOS microprocessor .• Works on 5 volts power supply and draws a current of 360

ma, with an internal circuitry made up of 29K transistors.• It consists of an electronic circuitry built using 29000

transistors.• It is built on single semiconductor chip and packaged in an

40-pin IC.• It has 20-bit address bus and 16-bit data bus.• It can directly address upto 220 I.e., 1M bytes of memory.• The 16-bit data word is divided into lower-order byte and

higher order byte.

8086 5

Features of 8086

• The 20-bit address bus is time multiplexed: The lower order 16-bit address bus is time multiplexed

with data bus. The higher order 4-bit address bus is time multiplexed

with status signals.

• The maximum internal clock for 8086 is 5MHz.

• 8086 chip does not have the facility of internal clock generation.

(the INTEL 8284 clock generator/driver is used to generate the clock signal for 8086 microprocessor

• The clock signal is divided by 3 in case of 8086 for internal clock requirements.

8086 6

Features of 8086

• 8086 uses I/O mapped I/O techniques hence I/O devices are accessed by using separate 16-bit address

• 8086 operates in two different modes Minimum mode

( It works as a simple single processor system when configured in minimum mode)

Maximum mode

( It works as a multiprocessor system i.e., along with math coprocessor and I/O coprocessor when configured in maximum mode)

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Control & Timing

Data pointer&

Index registers

ALU

FLAGS

Segment registers&

Instruction pointer

BusInterface

Unit

Instruction Queue

2

____BHE

A16/S3 to A19/S6

AD0 to AD15

_____INTA__RD__

WR

_

DT/R

___DEN

ALE

_____TESTINTR

NMI

__RQ/GT

LOCK

QS0

QS1

__

S1

__

S3

__

S2Vcc

___MN/MX

READY

RESET

CLKHLDAHOLD

GND

RelocationRegister fileExecution Unit

BUS interface unit

8086 8

AH ALBH BLCH CL

DLDHStack Pointer

Base Pointer

Destination Index

Source Index OperandsFLAGS

Instruction PointerDS RegisterSS RegisterCS RegisterES Register

654321

ControlSystem

Memory Interface

ALU

EU

BIU

DXCX

AX

BX

Instruction Queue

INTERNAL

BLOCK

DIAGRAM

8086 9

8086 Architecture• Architecture of 8086 is pipeline type of architecture.• The architecture of 8086 is divided into two functional

parts i.e.,i. Execution unit (EU)ii. Bus interface unit (BIU) These two units work asynchronously.• Functional division of architecture speeds up the

processing, since BIU and EU operate parallely and independently i.e., EU executes the instructions and BIU fetches another instruction from the memory simultaneously.

• As the whole architecture is divided into two independent functional parts and both the subsystem’s operations can be overlapped,hence the architecture is PIPELINING type of architecture.

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8086 ArchitectureEXECUTION UNIT

• The execution unit informs the BIU of the processor regarding from where to fetch the instructions from and then executes these instructions.

• The execution unit consists of the following: General purpose registers Stack pointer Base pointer Index registers ALU Flag register( FLAGS/ PSW) Instruction decoder Timing and control unit

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8086 ArchitectureFunctions of EU

• Tells BIU regarding from where to fetch instructions or to read data.

• Receives opcode of an instruction from the queue. • decodes the instructions.• Executes the instruction.

Functions of various parts of EU• Control circuitry: Directs internal operations.• Instruction Decoder: Translates instructions fetched from

memory into series of actions.• ALU: Performs arithmetic and logical operations.• FLAGS: Reflects the status of program.• General purpose registers: Used to store Temporary data.• Index and Pointer registers: Specifies/ informs about offset of

operand

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8086 ArchitectureBUS INTERFACE UNIT

• The BIU handles transfer of data and address between the processor and memory/ I/O devices by computing address (Physical/ Effective address) and send the computed address to memory / I/O and fetches instruction codes then stores them in FIFO register set called Queue register.

• The BIU also relocates the addresses of the un relocated operands and reads/writes data from/to memory/ I/O devices.

• The BIU consists of the following:

o Segment Registers

o Instruction pointer

o 6-Byte instruction Queue Register

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8086 ArchitectureFunctions of BIU

• Handles transfer of data and address between processor and memory / I/O devices.

• Compute physical address and send it to memory interfaces.

• Fetches instruction codes and stores it in Queue

• Reads/Writes data from/to memory/ I/O devices

• Relocates the unrelocated addresses of operands sent by EU

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8086 Architecture

Functions of various parts of BIU• Segment registers : Used to hold the starting address of the

segment registers.

• Queue register: Used to store prefetched instructions and inputs it to EU.

• Instruction Pointer: Used to point to the next instruction to be executed by EU.

• While the EU is decoding an instruction or executing an instruction which does not require use of the buses, the BIU fetches upto six instruction bytes that will be following the present instruction from memory and stores them in the queue register simultaneously.

8086 15

8086 Architecture• The prefetched instructions are stored in the queue register

which is an 6-byte FIFO register set.• When the EU is ready for its next instruction,it simply

reads the instruction byte(s) for the instruction from the queue which is present in BIU.

• At the starting, CS : IP pair are loaded with the required address from which the execution is to be started.

Initially, the queue register will be empty and microprocessor starts a fetch operation to bring one byte (the 1st byte ) of the instruction code depending on whether CS : IP is pointing to an even memory location or an odd memory location.

• The instruction of 8086 have 1 to 6 bytes i.e., we have instruction of size 1-byte long to 6-byte long, at a time two bytes of queue can be filled.

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Register organization of 8086• The various registers available internal to 8086

microprocessors are :1. Flag Register2. General purpose registers AX ( AH,AL) BX (BH,BL) CX (CH,CL) DX (DH,DL)3. Queue registers4. Instruction pointer (IP)5. Pointer and Index registers (SP,BP & SI,DI)6. Segment registers ES, CS, DS,SS

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Register organization of 8086

Flag Register• Flag register is part of EU.• 8086 microprocessor has a 16-bit flag register.• The register is also known as PSW ( Program Status Word).• The flag register/psw can be divided into 2-parts: Conditional /status flags Control flags• 8086 microprocessor has 9- active flags 6- conditional flags 3- control flags• Conditional flags: The lower byte of the flag register along

with overflow flag, they reflect the status of program.

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• Control Flags : Higher byte of the flag register , It has 3-flags i.e., direction flag, interrupt flag and trap flag.

They control the working of machine ( microprocessor)

O Overflow flag, D Direction flag, I Interrupt flag,

T Trap flag, S Sign flag, Z Zero flag,

AC Auxiliary Carry flag, P Parity flag

CY Carry flag, X Not used / Undefined

Bit SET 1 & Bit RESET 0.

X X X X O D I T S Z X AC X P CX

BIT 03 125 47 61113 1015 14 8912

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Flag Register

Condition flags

• Bit – 0 : CF (carry flag) — addition sets flag if carry out of MSB generate; subtraction sets flag if borrow needed.

• Bit –2 : PF (parity flag) — set to 1 if low-order 8 bits (low order byte) contain even number of 1’s (that is, gives odd parity)

• Bit – 4 : AF (auxiliary carry flag) — set if carry out of bit 3 during addition or borrow by bit 3 during subtraction. Used exclusively for BCD arithmetic.

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Flag Register

Condition flags• Bit – 6 : ZF (zero flag) — set to 1 if result is 0; to 0 if

result is nonzero

• Bit – 7 : SF (sign flag) — equal to MSB of result

• Bit – 11 : OF (overflow flag) — set if overflow occurs (that is, if carry in to MSB is not equal to carry out from MSB)

This generally occurs when the result of a signed operation is large enough to be accommodated in the destination register.

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Register organization of 8086Example – 1

• CF (carry flag) — carry out of MSB

• PF (parity flag) — set to 1 if low-order 8 bits (low order byte) contain even number of 1’s

• AF (auxiliary carry flag) —carry out of bit 3

• ZF (zero flag) — set to 1 if result is 0; to 0 if result is nonzero

• SF (sign flag) —MSB of result• OF (overflow flag) — set if carry

in to MSB is not equal to carry out from MSB)

0011 0100 1101 1100

+0000 0111 0010 1110

0011 1100 0000 1010

CF = 0

PF = 1

AF = 1

ZF = 0

SF = 0

OF = 0

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Register organization of 8086Example – 2

• CF (carry flag) — carry out of MSB

• PF (parity flag) — set to 1 if low-order 8 bits (low order byte) contain even number of 1’s

• AF (auxiliary carry flag) —carry out of bit 3

• ZF (zero flag) — set to 1 if result is 0; to 0 if result is nonzero

• SF (sign flag) —MSB of result• OF (overflow flag) — set if

carry in to MSB is not equal to carry out from MSB)

1111 1111 1110 0101

+1111 1111 1011 0001

1 1111 1111 1001 0110

CF = 1

PF = 1

AF = 0

ZF = 0

SF = 1

OF = 0

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Flag RegisterControl flags

• TF (trap flag) — if set, a trap is executed after each instruction

• IF (interrupt enable flag) — if set, a maskable interrupt can be recognized by the CPU; otherwise, these interrupts are ignored.

• DF (direction flag) — used by string manipulation instructions; if clear to 0, then process string from low address to high; if set to 1, then process string from high address to low.

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General Purpose Register

• In 8086 there are 4- general purpose registers i.e., AX,BX,CX,DX.

• These registers are of 16-bit size and can be used either as a whole 16-bit register ( the letter X used in the representation of the register indicates that the complete

16 – bit register is being used) or the upper and lower bytes can be accessed separately ( the letters H and L indicates the higher order and lower order bytes respectively in the representation of the registers )

• The general purpose registers can be used to store both operands and temporary results and each of them can be accessed as whole or as sub-registers.

8086 25

Register organization of 8086General Purpose Register

• In addition to serving as general purpose registers AX,BX,CX,DX have special uses as addressing, counting, and I/O roles.

• The special uses of the general purpose registers is:

AX used as accumulator BX used as a base register in address

calculation for some of the instructions CX used as an implied counter by certain

instructions DX used to hold the I/O address during

certain I/O operations.

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Register organization of 8086Queue Register

NoOpcode

From memory

Opcode 2nd

Byte

Opcode Queue

123456

Repeat the same procedure

for successive contents of queue

Take second byte From queue as Opcode,decode

2nd byte of opcode

Execute it with data bytes ,As decoded by decoder

Execute it with data bytes

Decoded byDecoder

Decode 1st byte To decide opcodeLength &update

QueueIs it

Single?

Yes

Update Queue

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Register organization of 8086 Queue Register

Filling of instruction Queue

• When first instruction starts from the even address

• When first instruction starts from the odd address

Entering

instruction

1st fetch

2nd fetch

3rd fetch

1st ins

2nd ins

3rd ins

1st fetch

3rd fetch

2nd fetch

Entering

instruction

4th fetch

3rd ins

1st ins

2nd ins

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Register organization of 8086 Queue Register

• If the opcode of instruction i.e., 1st byte of instruction is starting from even address, we need single memory reference to fill Queue with 2-bytes.

• If the 1st byte of instruction is in odd address, we need two memory references are required, one memory access for low-order byte and the next for high-order byte.

• Thus time is saved if words are stored at only even addresses.

• In case of branching instructions i.e., JMP and CALL instructions the whole Queue is flushed and then reloaded starting from a new address.

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Register organization of 8086• Instruction pointer: (IP)

The instruction pointer register holds the 16-bit offset or effective address of the next code byte to be fetched by the BIU from the CODE segment.The CODE segment register holds the upper 16-bits of the starting address of code segment from which the BIU is currently fetching instruction code bytes.The value contained in the IP is referred to as an offset because this value must be offset from (added to) the segment base address in CS to produce the required 20-bit physical address sent out by the BIU.During branching instruction execution immediately after queue is flushed off the first instruction in the branch will be directly available to the EU and while this is being executed, the queue register is filled.

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. The starting address of the segment :348A0

Code byte address: 38AB4

the offset between actual Code byte and starting address is :

38AB4-348A0=4214.

The alternate way to represent the 20-bit physical address of code byte is CS:IP

.

4489FTop of CODE Segment

CODE Byte

Start of CODE segment

38AB4

348A0

IP

3 4 8 A

4 2 1 4

4BA3 8

0

Hard-Wired

Zero

8086 31

Register organization of 8086• Pointers and Index registers:

The Pointer registers Stack Pointer (SP) and Base Pointer (BP) are present in EU.The Index registers Source Index (SI) and Destination Index (DI) are also present in EU.The SP, BP, SI and DI all are 16-bit registers.The pointer registers contain the offsets with in the segments as follows:IP Offset within the Code segment.BP Offset within the Data segment.SP Offset within the Stack segment.The index registers are used for storing Offset incase of Indexed, Based indexed, and Relative Based indexed addressing modes.

8086 32

Register organization of 8086• The SI register is generally used to store the offset of

source data ( array of characters / numbers/ string) in data segment and the register DI is used to store the offset of destination data string (characters/ numbers) present in Data segment or Extra segment.

• The index registers are usefully particularly for string manipulation instructions.

• The registers SI and DI can also be used as general purpose registers.

• Segment Registers:The segment registers are used to store the 16-bit segment base address.For 20-bit physical address calculation the contents of segment register is multiplied by (10)16 or (16)10 and offset is added to it.

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• The list of various segment registers is as follows:

CS Code Segment Register

DS Data Segment Register

ES Extra Segment Register

SS Stack Segment Register

• Register Pairs:

Apart from using the internal registers individually, for some operations certain registers are used in combination to form an 32-bit register combinely

The following are a typical combinations of registers which are allowed and explicitly used in 8086 programs:

CS : IP => This pair gives the physical address of the next location from where the next instruction is to be fetched.

8086 34

Register organization of 8086• DS:SI => This pair is used to refer to the 20-bit address for

pointing towards 20-bit physical address of a source string in case of string manipulation instructions

• ES : DI => This pair is also used to refer data address for pointing towards 20-bit physical address of a destination string in case of string manipulation instructions.

• SS : SP => Stack memory is referred to by this register pair, SS holds the memory segment of stack and SP holds the offset in that segment

PUSH instruction increments the 20-bit physical address pointed by this pair and POP instruction decrements the 20-bit physical address pointed by this pair.

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Register organization of 8086• SS : BP => Stack memory is inspected/ referred by this

pair. PUSH and POP instructions does not affect them.

• DX : AX => This pair is called the Extended Accumulator, whenever a 16-bit number is multiplied by another 16-bit number then the resultant product will be of 32-bit length; In-order to accommodate this 32-bit result the DX register is automatically appended to the AX register.

In order to support a 32-bit by 16- bit division using DIV instruction the 32-bit dividend which is to be divided is combinely placed in this register pair; After the division operation is completed the results i.e., remainder is placed in DX register and the Quotient is placed in AX register.

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Memory Organization of 8086• Memory Segmentation

Advantages of memory segmentation

Segmentation types

Non-overlapping Segmentation

Overlapping Segmentation

• Physical Address and Effective address

• Physical memory organization

Even Address

Odd Address

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Memory Organization of 8086• The processor provides a 20-bit address to memory which

locates the byte being referenced. The memory is logically organized as a linear array of 1 million bytes, addressed as 00000(H) to FFFFF(H).

• In 8086 as there are 20-bit address bus it can address directly upto 1 Mbytes of addresses but to handle this 20-bit address internally all the registers of BIU has to be 20-bits but this will increase the internal hardware logic as well as the space required by the BIU,thus to avoid this problem the concept of segmentation is introduced.

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Memory Organization of 8086

• Segmentation:Logically dividing the whole 1 MB memory into smaller segments such that instead of referring to the whole 20-bit address one can use and address with lesser bits for accessing the memory location.For this to happen there should be an base/ starting address stored at some place and then address range of addresses with reference to that base address which requires lesser bits to be used to refer to an location.As the 8086 microprocessor is an 16-bit processor the segmentation will also use only 16-bit registers hence the whole 1 MB memory can be divided into segments of 64KB (maximum)(the address spaces which can be addressed using an 16-bit offset).

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Memory Organization of 8086• Thus the whole memory is logically divided into 16

segments of 64 KB locations each.

• The base address of the segment is stored in the segment registers of 16-bit each placed in BIU.

• The offset of the location is stored in any of the pointer registers depending on the addressing mode used.

• The default pointer register for code segment register is IP.

• The base addresses of the segment may be assigned as 0000H to F000H respectively and the offset address values are from 0000H to FFFFH so that the physical address ranges from 00000H to FFFFFH.

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Memory Organization of 8086• Advantages of memory segmentation:

One advantage to have separate data and code segments is that, one program can work on several different sets of data. This is done by reloading data segment register to point to new data.

It allows programs to be loaded and run anywhere in memory.

It allows programs to be attended and recompiled independently.

It allows programs to be relocatable. It lends itself to sharing among processes. It lends itself to protection. It simplifies the handling of growing data structures. It reduces the number of bits required to address a

memory location.

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• Types of the segments:

The segments in the 8086 memory organization is of two types:

Non-Overlapping segments

Overlapping segments

The classification of the types of segments is made depending on how the base address is specified.

• Non-Overlapping Segments:

The simplest and conventional approach is to let both the code and data reside in an contiguous area in memory and put stack in some fixed area which always starts from a fixed address.

8086 42


• But when the system is working in multi-programming environment, there may be several programs in memory simultaneously. For multi-programming it is better to keep the contiguous chunks of memory as small as possible and thus it is better to separate the code from data.

• The option of making the code and data contiguous is always present, because the contents of CS,DS and ES can always be made equal.

• When working with time-sharing environment several users are executing different programs if there is no memory space these programs are shuttled back and froth between the memory and mass storage. As they take turns using memory they are dynamically put into different places in memory so that CS should be able to update according to changes.

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• Similar is the case with data and stack.

• When ever the new logical segment is started only after all the 64KB locations of present segment is completed such type of segmentation is known as Non-Overlapping Segments.

Data Segment

Code Segment

Stack Segment

Extra Segment

Base address of Code Segment

Base address of Data Segment

Base address of Stack Segment

Base address of Extra Segment

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• Overlapping segments :

When the amount of data is not of size 64 KB then the unused part of the memory is waste so to overcome the problem of this memory wastage, Overlapping segments are used.

In Overlapping segments the next segments starts before the present segment 64-KB are completed.

Thus the unused part of the memory as in case of Non-overlapping segmentation but, however the programmer has to take care in selecting the starting address of the next segment such that the starting address of the new segment is divisible by 1610 or 1016

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.

Segment-1

Segment-2

Base address of Segment-1

End of Data/Code

Starting of segment-2

Ending of segment-1

Ending of segment-2

64 KB

64 KB

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• Physical address and effective address: Physical Address:

The actual 20-bit address that can be transferred on to 20-bit address bus.

Effective Address:

The offset/ Displacement/ Distance from the starting address of segment is known as effective address.

Physical Address = ( Segment register contents) X 1610

+ Effective Address / Offset

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Memory Organization of 8086• Physical Address Generation:

Data MemoryDS

2000 0H

2FFFFH

2FFFEH

2FFFDH

2FFFCH

2FFFBH

22003H

22002H

22001H

20003H

20002H

20001H

EA

0000H

0001H

0002H

0003H

2001H

2002H

2003H

FFFBH

FFFCH

FFFDH

FFFEH

FFFFH

8086 48

Memory Organization of 8086• Base Address:

The 20-bit starting memory location address of any memory segment is called as base address.

• Physical Address:Actual 20-bit address of any memory location is called as physical address.The physical address of any memory location is always fixed.

• Effective Address:The displacement or offset of any memory location measured from the base address is called as effective address. EA (Effective Address) is stored in 16-bit registers so maximum value of effective address will be FFFFH.So one memory segment will consists of 216 = 64 K locations.

8086 49

Memory Organization of 8086• EA ranges from 0000H to FFFFH. The combination of

base address and effective address (BA:EA) is called as logical address.

Microprocessor will always transfer 20-bit physical address to select any memory location. This physical address is generated by 8086 is as given below:

16-bit

Memory Pointer

Σ

0000 20-bit

16-bit

20-bitPA =

EA = +

BA =

8086 50

Memory Organization of 8086• 8086 involves a set of registers, they are general purpose,

Segment, pointers and Index registers and Flag register.

In 8086, physical address is of 20-bit length but its registers are of just 16-bit length. To overcome this, segmentation is necessary, there are four types of segment registers i.e., Code Segment register, Data Segment register, Extra Segment register and Stack Segment register.

When Code Segment register carries the upper 16-bits of segment, an instruction pointer holds the 16-bit address of the next Code byte within the segment. The value available in the instruction pointer is referred as an offset of Code segment.

8086 51


• Physical Memory Organization:

The 1Mbytes memory is physically organized as Odd bank and Even bank, each of 512 Kbytes addressed in parallel by processor.

Byte data with Even address is transferred on D7-D0, while the byte data with Odd address is transferred on D15-D8 bus lines.

The processor provides two enable signals (BHE)’ and A0

for selection of either Even or Odd or Both the banks. The instruction stream is fetched from memory as words and is addressed internally by the processor as necessary.

8086 52


• If the processor fetches a word ( consecutive two bytes ) from memory, there are different possibilities likes:Both bytes may be Data operands.Both bytes may be Opcode bits.One of the bytes may be Opcode while the other may

be data.

In all the possibilities opcodes and operands are identified by the internal decoder circuit which further derives the signals those act as input to the timing and control unit. The timing and control unit then derives all the signals required for execution of the instruction.

8086 53

Memory Organization of 8086• When BIU fetches a word, the number of fetch cycles

required depends on whether the starting byte is located at Odd address or Even address.

• For a byte starting at Even address, to fetch a word a single memory cycle is enough.

• For a byte starting at Odd address, to fetch a word two memory cycles are required, i.e., one for lower byte and the next for the higher byte.

• Thus always it is preferable to keep or start our structure/ program at a even address.

• Fro structures like Stack they must be initialized at an even address for efficient operation.

8086 54


• Certain locations in memory are reserved for specific CPU operations such as the locations FFFF0H to FFFFFH are reserved for operations including jump to initialization program and I/O- Processor initialization.

• The locations 00000H to 003FFH are reserved for Interrupt Vector Table , thus known as interrupt structure.

• The interrupt structure provides space for a total of 256 interrupt vectors.

Each interrupt vector need 4 bytes i.e., two bytes for CS and two bytes for IP in the interrupt vector table.

Thus 256 types of interrupts require 256 X 4 = 03FFH (1 K bytes) locations for the complete interrupt vector table.

8086 55

Pin Configuration Of 8086

INTEL8086

GND

VCC

CLK

_____TEST

BHE / S7

INTR

NMI

AD0 – AD15

AD16–AD19/

S3 – S6

MN / ___ MX

___ ___HLDA RQ / GT1

___ ___

HOLD RQ / GT0

READY

RESET

___RD

ALE QS0____

INTA QS1

M /__ __

IO S2

DT/_ _ R S1

____ __

DEN S0

___ _____WR LOCK

GND

8086 56

Pin Definitions Pin(s) symbol In/Out/ Description

tri-state

1&20 GND ground

2-16 AD14-AD0 I/O-3 outputs address during the first part of the bus cycle and inputs or outputs data during the remaining part of bus cycle.

17 NMI I Non-maskable interrupt request- positive- going edge triggered. This interrupt does not check

whether IE flag is a logic 1.

18 INTR I maskable interrupt request- level triggered

19 CLK I clock-33%duty cycle, 5 MHz for 80868 MHz for 8086-2, 10MHz for 8086.

8086 57

Pin Definitions

21 RESET I A 1 on reset line terminates activity, clears PSW, IP, DS, SS, ES and the instruction queue, and sets the CS to FFFF. The processor begins resets service routine at FFFF0,

clear IE flag. when it is dropped to 0.signal must be 1 for at least 4 clock cycles.

22 READY I Acknowledgement from a memory or I/O interface that the input data will be put on the data bus or output data will be accepted from the data bus within the next clock cycle. CPU and bus control logic can complete the current bus cycle.

______23 TEST I used in conjunction with wait instruction in

multiprocessing environment. A wait instruction will cause the CPU to idle, except for processing interrupts, until a 0 is applied to this pin.

24-31 -- -- defined for minimum and maximum mode

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Pin Definitions

32 RD 0-3 indicates a memory or I/O read is to be performed.

33 I CPU is in minimum mode when strapped to +5V and maximum mode when grounded.

34 O-3 If 0 during first part of bus cycle, indicates that at least one byte of the current transfer is to made on pins AD15-AD8. If 1 the transfer is made on AD7-AD0. Status S7 is output during the later part of the bus cycle.(S7 hasn't assigned a meaning).

___MN / MX

____BHE / S7

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Pin Definitions 35-38 A19/S6 - O-3 during the first part of the bus cycle the

A16/S3upper 4 bits of the address are output and

During the remainder of the bus cycle status is output. S3 & S4 indicate the

segment register being used as follows: S4 S3 Register 0 0 ES 0 1 SS 1 0 CS or none 0 0 DSS5 gives the current setting of IF.S6 is always 0.

39 AD15 I/O-3 same as AD14-AD0

40 VCC -- supply voltage +5V ±10%.

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Minimum mode system

Transceivers(2 8282s)

optional

Reset

ALE

BHE’

Ready

___MN / MX

CLK

+5V

Clock(8284A)

AddressLatches

(3 8282s)

8086

A19-A16

AD15-AD0

Address bus

Data bus

Control bus

DEN’DT / R’

M/IO’WR’RD’

HOLDHLDAINTRINTA’

BHE’

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Minimum mode system___

24 INTA O-3 Indicates recognition of an interrupt request.

25 ALE O outputs a pulse at the beginning of bus cycle and is to indicate an address is available on the address pins.

____

26 DEN O-3 output during the latter portion of bus cycle and is to inform the transceiver that CPU is ready to send or receive data.

___

26 DT / R O-3 indicates to the set of transceivers whether they are to transmit or receive data.

__

26 M / IO O-3 distinguish memory transfer (logic 1) from an I/O transfer (logic 0).

__

26 WR O-3 when 0, it indicates a write operation is being performed.

27 HOLD I Receives a bus request from bus masters.

28 HLDA O outputs a bus grant to a requesting master.

8086 62

Maximum mode system CLK VCC GND

__ CLK AEN S0

__ 8288 Bus

s1 Controller __

S2

CEN DEN __ DT / R ALE

AD0 - AD15, A16/s3 – A19/s6

QS1, QS0

_______MRDC______MWDC______AMWC______IORC

_______IOWC______AIOWC_____INTA

_____MCE / PDEN

______ALE

__DT / R_____DEN

______LOCK______

BHE___RD

READY

5V

INTR _____ TEST NMI RESET

8086MPU

___ M/N MX

___ ___ ___ ___RQ / GT1 RQ / GT0

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Maximum mode system24,25 QS1,QS0 O Reflects the status of the instruction queue.

__ __ __

26 – 28 S0,S1,S2 O-3 Indicates the type of transfer to take place during the current bus cycle. __ __ __

S2 S1 S0 QS1 QS0 Indication

0 0 0 Interrupt acknowledge 0 0 No operation

0 0 1 Read I/O port 0 1 First byte of op-code

0 1 0 Write I/O port from the queue

0 1 1 Halt 1 0 Empty Queue

1 0 0 Instruction fetch 1 1 Subsequent byte from 1 0 1 Read memory the queue.

1 1 0 Write memory

1 1 1 Inactive – passive

_____

29 LOCK O-3 Indicates the bus will not be released to other potential bus masters until the instruction with prefix LOCK is executed.

___ ___

30 RQ / GT1 I/O for inputting bus requests and outputting bus grants.

___ ___ ___ ___ ___ ___

31 RQ / GT0 I/O same as that RQ / GT1 except that a request on RQ / GT0 has higher priority.

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