Unit 3 8086 Programming 8086 Registers RCETMicroprocessor & Microcontroller3.
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Transcript of Unit 3 8086 Programming 8086 Registers RCETMicroprocessor & Microcontroller3.
8086 Registers
RCET Microprocessor & Microcontroller 3
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
General Purpose Registers
• Normally used for storing temporary results • Each of the registers is 16 bits wide (AX, BX, CX, DX)• Can be accessed as either 16 or 8 bits AX, AH, AL
RCET Microprocessor & Microcontroller 4
AX - the AccumulatorBX - the Base RegisterCX - the Count RegisterDX - the Data Register
General Purpose Registers• AX
– Accumulator Register – Preferred register to use in arithmetic, logic and
data transfer instructions because it generates the shortest Machine Language Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations
• BX– Base Register– Also serves as an address registerRCET Microprocessor & Microcontroller 5
General Purpose Registers
• CX– Count register– Used as a loop counter– Used in shift and rotate operations
• DX– Data register– Used in multiplication and division– Also used in I/O operations
RCET Microprocessor & Microcontroller 6
Pointer and Index Registers
• All 16 bits wide, L/H bytes are not accessible
• Used as memory pointers– Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in register SI to register AH
• IP is not under direct control of the programmerRCET Microprocessor & Microcontroller 7
Flag Register
RCET Microprocessor & Microcontroller 8
Carry
Parity
Auxiliary Carry
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Memory segmentation and addressing
• Von – Newman architecture & Harvard architecture
• Program Memory & Data Memory
• Need for Segmentation– To implement Harvard architecture– Easy to debug– Same Interfacing ICs can be used– To avoid overlap of stack with normal memory– Compatible with 8085
RCET Microprocessor & Microcontroller 9
Memory Address Generation• The BIU has a dedicated adder for determining
physical memory addresses.
RCET Microprocessor & Microcontroller 11
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Segment : Offset Address
• Logical Address is specified as segment:offset
• Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address.
• Thus the physical address of the logical address A4FB:4872 is:
A4FB0 + 4872
A9822RCET Microprocessor & Microcontroller 12
Segments, Segment Registers & Offset Registers
• Segment Size = 64KB
• Maximum number of segments possible = 14
• Logical Address – 16 bits
• Physical Address – 20 bits
• 2 Logical Addresses for each Segments.
– Base Address (16 bits)
– Offset Address (16 bits)
• Segment registers are used to store the Base address of the segment.
RCET Microprocessor & Microcontroller 13
Segments, Segment Registers & Offset Registers
• 4 Segments in 8086– Code Segment (CS)
– Data Segment (DS)
– Stack Segment (SS)
– Extra Segment (ES)
RCET Microprocessor & Microcontroller 14
SEGMENT SEGMENT REGISTER OFFSET REGISTER
Code Segment CSR Instruction Pointer (IP)
Data Segment DSR Source Index (SI)
Extra Segment ESR Destination Index (DI)
Stack Segment SSR Stack Pointer (SP) / Base Pointer (BP)
3-17
Accessing Data Memory
There are number of methods to generate the memory address when accessing data memory. These methods are referred to as Addressing Modes Examples:
— Direct addressing: MOV AL, [0300H]
1 2 3 4 00 3 0 02 6 4 01
DS
Memory address
(assume DS=1234H)
— Register indirect addressing: MOV AL, [SI]
1 2 3 4 00 3 1 02 6 5 01
DS
Memory address
(assume DS=1234H)
(assume SI=0310H)
Addressing Modes
• Operands in an instruction– Registers AX
– Numbers immediate 12H
– Memory
• Direct addressing [3965]
• Register indirect [BX]
• Based relative addressing mode [BX+6], [BP]-10
• Indexed relative addressing mode [SI+5], [DI]-8
• Based indexed addressing mode
Operand types
1) Register - Encoded in instruction • Fastest executing • No bus access (in instr. queue) • Short instruction length
2) Immediate - Constant encoded in instruction • 8 or 16 bits • No bus access (in instr. queue) • Can only be source operand
3) Memory – in memory, requires bus transfer• Can require computation of address• Address of operand DATA is Called
EFFECTIVE ADDRESS
Effective Address• Computed by EU
• In General, Effective address = displacement + [base register]+ [index register]
(if any) (if any)
• Any Combination of These 3 Values
– Leads to Several Different Addressing Modes
• Displacement– 8 or 16 bit Constant in the Instruction– “base register” Must be BX or BP – “index register” Must be SI or DI
Direct Addressingmov [7000h], ax
mov es:[7000h], ax
opcode mod r/m displacement
effective address
ds:7000h ax
es:7000h ax
26 A3 00 70
A3 00 70
prefix byte - longer instruction - more fetch time
Register Indirect Addressingmov al, [bp] ;al gets 8 bits at SS:BP
mov ah, [bx] ;ah gets 8 bits at DS:BX
mov ax, [di] ;ax gets 16 bits at DS:SI
mov eax, [si] ;eax gets 32 bits at DS:SI
opcode mod r/m
BX
effective addressBP
SI
DI
Based Indirect Addressing
mov al, [bp+2] ;al gets 8 bits at SS:BP+2
mov ah, [bx-4] ;ah gets 8 bits at DS:BX-4
BX
effective address
BP+
opcode mod r/m displacement
Indexed Indirect Addressingmov ax, [si+1000h] ;ax gets 16 bits at DS:SI+1000h
mov eax, [si+300h] ;eax gets 32 bits at DS:SI+300h
Mov [di+100h], al ;DS:DI+100h gets 8 bits in al
DI
effective address
SI+
opcode mod r/m displacement
Based Indexed Indirect Addressingmov ax, [bp+di] ;ax gets 16 bits at SS:BP+DI
mov ax, [di+bp] ;ax gets 16 bits at DS:BP+DI
mov eax, [bx+si+10h] ;eax gets 32 bits at DS:BX+SI+10h
mov cx, [bp+si-7] ;cx gets 16 bits at SS:BP+SI-7
DI
effective address
SI+
opcode mod r/m displacement
BX
BP+
Addressing Mode Examples
mov al, bl ;8-bit register addressingmov di, bp ;16-bit register addressingmov eax, eax ;32-bit register addressingmov al, 12 ;8-bit immediate, al<-0chmov cx, faceh ;16-bit immediate, cx<-64,206mov ebx, 2h ;32-bit immediate, ebx<-00000002hmov al, LIST ;al<-8 bits stored at label LISTmov ch, DATA ;ch<-8 bits stored at label DATAmov ds, DATA2 ;ds<-16 bits stored at label DATA2mov al, [bp] ;al<-8 bits stored at SS:BPmov ah, [bx] ;ah<-8 bits stored at DS:BXmov ax, [bp] ;ax<-16 bits stored at SS:BPmov eax, [bx] ;eax<-32 bits stored at DS:BXmov al, [bp+2] ;al<-8 bits stored at SS:(BP+2)mov ax, [bx-4] ;ax<-16 bits stored at DS:(BX-4)mov al, LIST[bp] ;al<-8 bits stored at SS:(BP+LIST)mov bx, LIST[bx] ;bx<-16 bits stored at DS:(BX+LIST)mov al, LIST[bp+2] ;al<-8 bits stored at SS:(BP+2+LIST)mov ax, LIST[bx-12h] ;ax<-16 bits stored at DS:(BX-
18+LIST)
Register
Immediate
Direct
Based
More Addressing Mode Examples
mov al, [si] ;al<-8 bits stored at DS:SImov ah, [di] ;ah<-8 bits stored at DS:DImov ax, [si] ;ax<-16 bits stored at DS:SImov eax, [di] ;eax<-32 bits stored at DS:DImov ax, es:[di] ;ax<-16 bits stored at ES:DImov al, [si+2] ;al<-8 bits stored at DS:(SI+2)mov ax, [di-4] ;ax<-16 bits stored at DS:(DI-4)mov al, LIST[si] ;al<-8 bits stored at DS:(SI+LIST)mov bx, LIST[di] ;bx<-16 bits stored at DS:(DI+LIST)mov al, LIST[si+2] ;al<-8 bits stored at DS:(SI+2+LIST)mov ax, LIST[di-12h] ;ax<-16 bits stored at DS:(DI-18+LIST)mov al, [bp+di] ;al<-8 bits from SS:(BP+DI)mov ah, ds:[bp+si] ;ah<-8 bits from DS:(BP+SI)mov ax, [bx+si] ;ax<-16 bits from DS:(BX+SI)mov eax, es:[bx+di] ;eax<-32 bits from ES:(BX+DI)mov al, LIST[bp+di] ;al<-8 bits from SS:(BP+DI+LIST)mov ax, LIST[bx+si] ;ax<-16 bits from DS:(BX+SI+LIST)mov al, LIST[bp+di-10h] ;al<-8 bits from SS:(BP+DI-16+LIST)mov ax, LIST[bx+si+1AFH] ;ax<-16 bits from DS:(BX+SI+431+LIST)
Indexed
BasedIndexed
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0005IP
5678DI
Inst. Queue
1000:0005
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0005IP
5678DI
Inst. Queue
10005
2300000
00001
10000
10001
10002
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10008
95
::
45
98
27
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88
07
F4
8A
::
20020
20021
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20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0005IP
5678DI
Inst. Queue
10005
LOW
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
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07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WRHIGH
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0005IP
5678DI
Inst. Queue
10005
88
LOW
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
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07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WRHIGH
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0005IP
5678DI
Inst. Queue
88
10005
88
LOW
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
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88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WRHIGH
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0005+1IP
5678DI
Inst. Queue
88 2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
INC. PC
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006IP
5678DI
Inst. Queue
88 2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
INC. PC
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006IP
5678DI
Inst. Queue
88 2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
DECODE
mov [bx], ?
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006IP
5678DI
Inst. Queue
88
CS:IP
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006IP
5678DI
Inst. Queue
88
1000:0006
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006IP
5678DI
Inst. Queue
88
10006
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006IP
5678DI
Inst. Queue
88
10006
LOW
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WRHIGH
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006IP
5678DI
Inst. Queue
88
10006
07
LOW
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WRHIGH
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006IP
5678DI
Inst. Queue
8807
10006
07
LOW
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WRHIGH
FETCH
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0006+1IP
5678DI
Inst. Queue
8807 2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
INC. PC
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0007IP
5678DI
Inst. Queue
8807 2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
INC. PC
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0007IP
5678DI
Inst. Queue
8807 2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
DECODE
mov [bx], al
A19
A0
:
D7
D0
:
MEMR
MEMW
1234
BP
ES
DS
SS
CX
BX
AX
34CD
AB12
1AB3
2000
0000
0023
3F1C
FCA1
SP
DX
1243
CS
SI
1000
0007IP
5678DI
Inst. Queue
8807
DS:BX
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
EXECUTEmov [bx], al
A19
A0
:
D7
D0
:
MEMR
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EXECUTEhlt
8086 Instruction set summary
• Data transfer operations
• Arithmetic operations
• Logic operation
• Control operations
• String operations
• Machine control
Data Transfer Instructions• Very Common Instruction: mov desti, source
• Allowed Operands Destination SourceMemory AccumulatorAccumulator MemoryRegister RegisterRegister MemoryMemory RegisterRegister ImmediateMemory ImmediateSeg. Reg. RegisterSeg. Reg. MemoryRegister Seg. Reg.Memory Seg. Reg.
Arithmetic/Logic Instructions
• Basic Mathematical Operations
– Signed/Unsigned Integer Only– Default is 2’s Complement– Computes Result AND Modifies Status Flags
• Logic Instructions
– Bit Level– Word Level– Computes Results AND Modifies Status Flags
Arithmetic Instruction Summary
add ax, bx ;axax+bx and set flagsadc ax, bx ;axax+bx+CF(lsb) and set flagsinc ax ;axax+1 and set flagsaaa ;ASCII Adjust after Additiondaa ;Decimal (BCD) Adjust after Additionsub ax, bx ;axax-bx and set flagssbb ax, bx ;ax(ax-CF)-bx and set flagsdec ax ;axax-1neg ax ;ax(-1)*(ax) -- 2’s Complementcmp ax, bx ;Flags are set according to ax-bxdas ;Decimal (BCD) Adjust after Subtractionaas ;ASCII Adjust after Subtractionmul cx ;dx:ax ax * cx (unsigned)imul cx ;dx:ax ax * cx (2’s complement)aam ;ASCII Adjust after Multiplicationdiv cl ;alax/cl Quot. AND ahax/cl Rem.idiv cx ;ax(dx:ax)/cx Quot. AND dx Rem.aad ;ASCII Adjust after Division
Addition Instruction Types
add ax, bx ;axax+bx and set flagsadc ax, bx ;axax+bx+CF(lsb) and set flagsinc ax ;axax+1 and set flagsaaa ;ASCII Adjust after Additiondaa ;Decimal (BCD) Adjust after
Addition add al, bl ;alal+bl and set flagsadd bx, 35afh ;bxbx+35afhadd [bx], al ;ds:(bx)ds:(bx)+al add cl, [bp] ;clcl+ss:(bp)add al, [ebx] ;alal+ds:(ebx)add bx, TEMP[di] ;bxbx+ds:(TEMP+di)
Increment Examples
inc bl ;blbl+1 and set flags
inc BYTE PTR [bx] ;Byte at ds:(bx)ds:(bx)+1
New MASM Directive: BYTE POINTER
00ffh 0000h
inc [bx] ;Word at ds:(bx)ds:(bx)+1
00ffh 0100h
inc [DATA1] ;ds:(DATA1)ds:(DATA1)+1
Add with Carry
add ax, cx ;axax+cx and flags setadc bx, dx ;bxbx+dx+CF(lsb) and flags set
33-bit Sum Present in CF:bx:ax
BX
DX
AX
CX
1 1
0 1
CF=1
BX AXCF
Decimal Adjust after Addition
• For BCD Arithmetic
• “Corrects” Result
0110 6 +01117 1101 13should be 0001 0011 (1101 is illegal BCD)
•2 Digits/Word Intel Refers to as “Packed Decimal”
•daa Uses Implicit Operand, al Register
•Follows add, adc to “Adjust”
Decimal Adjust after Addition Example
mov dx, 1234h ;dx1234 BCDmov bx, 3099h ;bx3099 BCDmov al, bl ;al99 BCDadd al, dl ;alcdh illegal BCD, need 34+99=133daa ;al33h (33 BCD) and CF=1mov cl, al ;cl33 BCDmov al, bh ;al30 BCDadc al, dh ;al30h+12h+1=43hdaa ;al43h (43 BCD) not illegal BCD this timemov ch, al ;cx=4333h BCD for 1234+3099
ASCII Adjust after Addition
• For Addition Using ASCII Encoded Numbers
30h through 39h Represent ‘0’ through ‘9’
• ax is Default Source and Destination for aaa
31 ‘1’ +39 ‘9’ 6a ‘10’should be 3130h (6ah is incorrect ASCII result ‘j’)
mov ax, 31h ;ax0031h=‘1’add al, 39h ;ax31h+39h=006ah=‘<nul>j’aaa ;ax0100h (this is BCD of result)add ax, 3030h ;Convert from BCD to ASCII
;ax0100h+3030h=3130h=‘10’
Subtraction Instruction Types
sub ax, bx ;axax-bx and set flagssbb ax, bx ;ax(ax-CF)-bx and set flagsdec ax ;axax-1neg ax ;ax(-1)*(ax) - 2’s Complementcmp ax, bx ;Flag is set according to ax-bx
das ;Decimal (BCD) Adjust after Subtraction
aas ;ASCII Adjust after Subtraction
Allowable Operands for add, sub
Gen Reg
Gen Reg
Mem Loc
Immediate
+-
Gen Reg
Mem Loc
Immediate
+-
Destination Source
Subtract with Borrow, sbb
sub ax, di ;axax-di and CF gets borrow bitsbb bx, si ;bx(bx-CF(lsb))-si and flags set
32-bit Difference Present in bx:axCF Indicates If Difference is Negative
BX
SI
AX
DI
CF
BX AXCF
Multiplication
• 8086/8088 One of First to Include mul/div Instruction
• Allowable Operands: Bytes, Words, DoubleWords
•Allowable Results: Words, DoubleWords, QuadWords
•OF, CF Give Useful Information
•AF, PF, ZF, SF Change but Contents Unpredictable
•Multiplicand Always in al, ax
•mul - Unsigned Mnemonic
•imul - Signed Mnemonic
Multiply Instructions
• Product can be Twice the Size2 3 = 6 (same size)
2 8 = 16 (double size, EXT)
•OF=CF=0 means product is same size as result (faster)•OF=CF=1 means EXT product size (slower)•AF, PF, ZF, SF Contents Unpredictable
mul bl ;axal*bl, Unsignedmul bx ;dx:axbx*ax, Unsignedimul bl ;axal*bl, Signedimul bx ;dx:axbx*ax, Signed
Division
• 8, 16, 32 bit Operands (32 bit is 386+)• No Immediate Addressing Mode• No Flag Bits Change Predictably• Can Cause Two Types of Error:
1) Divide by 0 (Mathematically Undefined)
2) Divide Overflow (Wordlength Problem)
• Operands: Divisor is Programmer Specified• Dividend is Implied• Quotient, Remainder Implied
Size Dividend Quotient Remainder8 bits ax al ah16 bits dx:ax ax dx32 bits edx:eax eax edx
Division Instruction Examples
• idiv Signed and div Unsigned
dividend / divisor = quotient, rmdr
div cx ;dx:ax is divided by value in cx;unsigned quotient is placed in ax;positive remainder is placed in dx
idiv ebx ;edx:eax is divided by value in ebx;signed quotient is placed in eax;remainder (ALWAYS same sign as ;dividend) is placed in edx
Logic Instruction TypesBITWISE LOGICAL
not ax ;1’s Complement-Logical Invertand ax, bx ;Bitwise logical and operationor ax, bx ;Bitwise logical inclusive-or operationxor ax, bx ;Bitwise logical exclusive-or operationtest ax, fffh ;Bitwise and but result discarded
SHIFTshl ax, 4 ;Logical shift leftsal ax, 3 ;Arithmetic shift leftshr ax, 4 ;Logical shift rightsar ax, 3 ;Arithmetic shift right
ROTATErol bx, 3 ;Rotate leftror cx, 4 ;Rotate rightrcl ax, 1 ;Rotate left through carry
rcr dx, 6 ;Rotate right through carry
Bit Level Logicand, or, xor, not, test
• Affect Status Flags as Follows:1) Always Clears CF and OF2) SF, ZF, AF, PF Change to Reflect Result
• Common Usage:
and ax, ax ;clear CF and OF
xor ax, ax ;clear ax=CF=OF=PF=AF=SF=0 and ZF=1 ;does more than mov ax, 0h ;faster than push 00h then popf
Shiftsshl - Logical Shift Left
REGCF 0
REG CF0
REGCF 0
REG CF
shr - Logical Shift Right
sal - Arithmetic Shift Left (same as logical)
sar - Arithmetic Shift Right (sign bit is preserved)
MSB
Rotatesrol - Rotate Left
REGCF
rcl - Rotate Through Carry Left
ror - Rotate Right
rcr - Rotate Through Carry Right
REGCF
REGCF
REGCF
Program Control Instructions
•Generally modify CS:IP •Causes modification in execution sequence (of instructions)• When such a program flow change occurs:
a) Instructions in the BIU inst. queue become invalid
b) BIU directly fetches CS:IP instruction from memory
c) While EU executes new instruction, BIU flushes/refills inst. queue
• Classificationa) Jumps - Unconditional control transfers (synchronous)b) Branches - Conditional control transferc) Interrupts - Unconditional control transfers (asynchronous)d) Iteration - More complex type of branch
Control Instruction Summary
UNCONDITIONALjmp LABEL ;next instruction executed has LABELcall LABEL ;next instruction executed has LABELret ;next instruction executed is after the callhlt ;nothing executed until RESET signal
ITERATIONloop LABEL ;cx cx - 1, jump to LABEL if cx > 0loope/loopz LABEL ;same as loop but ZF=1 also requiredloopne/loopnz ;same as loop but ZF=0 also required
INTERRUPTSint <immed8> ;Invoke the int. handler specified by immed8 into <immed8> ;same as int but OF=1 alsoiret ;Return from interrupt handler
CONDITIONAL to follow
Simplest Control Instruction, jmp
jmp LABEL ;LABEL is offset address of instruction ;in the code segment
3 Forms of jmp
SHORT - 2 bytes, allows jump to ±127 locations from current address
NEAR - 3 bytes, allows jump to ±32K locations from current address
FAR - 5 bytes anywhere in memory
EB disp
E9 disphi displo
EA IP lo IP hi CS lo CS hi
Conditional Control Instruction SummarySimple Flag Branches
CONDITIONAL
jc LABEL ;jump on carry (CF=1)jnc LABEL ;jump on no carry (CF=0)je/jz LABEL ;jump if ZF=1 - jump if equal/zerojne/jnz LABEL ;jump if ZF=0 - jump not equal/jump if zerojo LABEL ;jump if OF=1 - jump on overflowjno LABEL ;jump if OF=0 - jump if no overflowjs LABEL ;jump on sign flag set (SF=1)jns LABEL ;jump if no sign flag (SF=0)jp/jpe LABEL ;jump if PF=1 - jump on parity/parity evenjnp/jpo LABEL ;jump if PF=0 - jump on no parity/parity odd
Jump based on single flag
Conditional Control Instruction SummaryBranches for unsigned comparisons
Jump is based on flags used for unsigned number comparison (based on C, Z flag)
CONDITIONALja/jnbe LABEL ;jump if CF=ZF=0 - jump above-jump not below/equaljae/jnb LABEL ;jump if CF=0 - jump above/equal-jump not belowjb/jnae LABEL ;jump if CF=1 - jump below-jump not above/equaljbe/jna LABEL ;jump if CF=1 or ZF=1 - jump equal - jump zero
Typical use: cmp al,bljb there ; jump if al is ‘below’ bl
; unsigned comparison
Conditional Control Instruction SummaryBranches for signed comparisons
Typical use: cmp al,bljl there ; jump if al is less than bl
; signed comparison
Jump is based on flags used for signed number comparison (based on Z, S, V flags)
CONDITIONAL
jg/jnle LABEL ;jump if ZF=0 and (SF=OF) - jump greater/not less ; nor equal
jge/jnl LABEL ;jump if SF=OF - jump greater-equal/not less thanjl/jnge LABEL ;jump if SF OF - jump less than/not greater nor
; equal jle/jng LABEL ;jump if ZF=1 or SF OF - jump less or equal/not
; greater than
Iteration Instruction, loop
• Combination of decrement cx and conditional Jump• Decrements cx and if cx0 jumps to LABEL
Example:
ADDS PROC NEARmov cx, 100 ;cx 64h - number of words to addmov si, OFFSET BLOCK1 ;si offset of BLOCK1 (in ds)mov di, OFFSET BLOCK2 ;di offset of BLOCK2 (in es)cld ;Auto-increment si and di, DF=0
AGAIN: mov bx, di ;bx di, save offset of BLOCK2lodsw ;ax ds:[si], sisi+2, didi+2add ax, [bx] ;ax ax + ds:[bx]mov di, bx ;di bx, restore di with
; offset in BLOCK2stosw ;es:[di] ax, sisi+2, didi+2loop AGAIN ;cx cx - 1, if cx0 jump to AGAINret ;ip ss:[sp]
ADDS ENDP
Procedures• Group of instructions that perform single task
– (can be used as) a SUBROUTINE
call - invokes subroutine - pushes ipret - returns from subroutine - pops ip
• Must specify
NEAR - intrasegmentFAR - intersegment
• Difference is op-code of ret
NEAR - c3h - pops IPFAR - cbh - pops CS, pops IP
call Instruction
• Differs from jmp since return address on stack
NEAR call: 3 bytes - 1 opcode and 2 for IP FAR call: 5 bytes - 1 opcode, 2 for IP and 2 for CS
• call with operand - can use 16-bit offset in any register except segment registers
call bx ;pushes ip then jumps to cs:[bx]
call Instruction - Example
mov si, OFFSET COMPcall si
.
.
.COMP PROC NEAR
push dxmov dx, 03f8hin al, dxinc dxout dx, alpop dxret
COMP ENDP
ret Instruction
NEAR - pops 16-bit value places in IPFAR - pops 32-bit value places in CS:IP
• Type is determined by PROC directive• Other form of ret has immediate operand (8 bit)
The immediate operand is added to the SP after popping the return address
Example
ret 6
String Transfer Instructions
• String Forms:
movsb ;move string byte by bytemovsw ;move string word by word
EXAMPLE:movsb ;Copies 8 bits at DS:SI to ES:DI
Other String Instructions
lodsb ;loads al with contents of ds:si;Inc/Dec si by 1 depending on DF
lodsw ;loads ax with ds:si ;Inc/Dec si by 2 depending on DF
stosb ;loads es:di with contents of al;Inc/Dec di by 1 depending on DF
stosw ;loads es:di with contents of ax;Inc/Dec di by 2 depending on DF
String Scan Instruction, scas•scasb, scasw• Compares al, ax• Does an integer subtraction - result not saved• Generally used with a REPEAT prefix•DF controls auto-increment/decrement•Example:
mov di, OFFSET BLOCK ;di address of memory location BLOCKcld ;DF 0, auto-increment modemov cx, 100 ;cx 64h, initialize counter to 100xor al, al ;clear alrepne scasb ;test for 00h in location es:di
;if es:di not equal to 00h then; cx cx - 1, di di + 1, repeat;else if cx = 00h; do not repeat test;else if es:di equals 00h; ZF = 1, do not repeat test
Compare String Instruction, cmps
•cmpsb, cmpsw• Compares 2 sections of memory• Does an integer subtraction - result not saved• Generally used with a REPEAT prefix•si, di auto-increment/decrement depending on DF•Example: Test two strings for equivalence
;Assume that ds and es are already set-up (NOTE:ds can equal es)lea si, LINE ;si gets offset of location labeled LINElea di, TABLE ;di gets offset of location labeled TABLEcld ;DF=0, auto-increment modemoc cx, 10 ;initialize counter register to 10repe cmpsb ;while ds:si=es:di decrement cx and incr. si, di
;if cx=0 stop testing;after complete, if cx not equal 0, then;strings do not match