78.Hysteresis Modulation of Multilevel Inverters

1396 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

Hysteresis Modulation of Multilevel InvertersAnshuman Shukla, Member, IEEE, Arindam Ghosh, Fellow, IEEE, and Avinash Joshi

Abstract—The hysteresis modulation for power electronic con-verters is attractive in many different applications because of itsunmatched dynamic response and wide command-tracking band-width. Its application and benefits for two-level converters are wellunderstood, but the extension of this strategy to multilevel convert-ers is still under development. This paper summarizes and reviewsthe various hysteresis modulation approaches available in the liter-ature for multilevel converters. The pros and cons of various tech-niques are described and compared for tracking the reference sig-nal in order to attain an adequate switching optimization, excellentdynamic responses and high accuracy in steady-state operation. Byusing the recently developed multilevel hysteresis modulation ap-proaches, the advantages of using several accessible dc potentialsin a multilevel inverter have been fully exploited. All of these hys-teresis modulation approaches are tested for tracking a currentreference when applied to a five-level inverter. The relevant simu-lation and experimental results are also presented. This study willprovide a useful framework and point of reference for the futuredevelopment of hysteresis modulation for multilevel converters.

Index Terms—Hysteresis modulation, multiband (MB), multi-offset band (MOB), multilevel converter, time-based (TB).

I. INTRODUCTION

THE hysteresis modulation for power electronic convertersare preferred for applications, where performance require-

ments are more demanding such as to achieve good dynamicresponse, unconditional stability, and wide command-trackingbandwidth [1], [2]. In this approach, the controlled system vari-able is compared against hysteresis band(s) to create the switch-ing commands for the converter. This control has been widelyused to control the conventional two-level converter, showingits robustness and simplicity in a lot of applications [3]–[13]. Abrief description of the standard two-level hysteresis control foroutput current regulation is presented in the following.

The objective of standard two-level hysteresis current con-trol is to switch the converter transistors in such a manner thatthe converter load current tracks a reference within a specifiedhysteresis band. Consider a single-phase half-bridge inverter, asshown in Fig. 1(a) for two-level hysteresis current control. InFig. 1, two dc sources of magnitudes Vdc/2 are considered at

Manuscript received March 2, 2010; revised July 28, 2010; acceptedSeptember 9, 2010. Date of current version June 22, 2011. Recommendedfor Publication by Associate Editor Leon M. Tolbert.

A. Shukla is with Power Technology, ABB Corporate Research,Vasteras 72178, Sweden (e-mail: [email protected], [email protected]).

A. Ghosh is with School of Engineering Systems, Queensland University ofTechnology, Brisbane 4001, Australia (e-mail: [email protected]).

A. Joshi is with Department of Electrical Engineering, Indian Institute ofTechnology Kanpur, Kanpur 208016, India (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2010.2082001

Fig. 1. (a) Two-level half-bridge inverter. (b) Two-level hysteresis control.

the dc link of inverter and their common point (n, neutral point)is grounded. The net controllable output voltage of the inverteris uVdc/2, where u is defined as the control input and representsthe switching logic of inverter. It assumes the values +1 and−1 for the two-level inverter of Fig. 1(a). The inverter outputvoltage van can be represented as follows:

van =uVdc

2= Ria + L

diadt

+ vback (1)

where ia is the load current, vback is the back EMF voltage, andL and R are the load inductance and resistance, respectively[see Fig. 1(a)]. As vback increases or as larger reference currentslopes are required, larger average values of van need to beused. Since the voltage across the load resistance is often small,this value can often be neglected. Introducing a term diref/dt,where iref is the current reference to be tracked, (1) becomes asfollows:

d(ia − iref )dt

≈ uVdc/2 − vback

L− diref

dt. (2)

It is evident from (2) that the current error (ce = ia − iref ) canbe reduced by increasing or decreasing van , depending on thepolarity of ce . Fig. 1(b) represents the implementation logic forthis correct voltage-level selection for a two-level inverter usinghysteresis control. It can be seen that as the measured current(ia ) becomes greater than its reference (iref ) by the hysteresisband “h,” the inverter output voltage (uVdc/2) is switched to itslowest level (−Vdc/2, u = −1) in order to decrease the current[according to (1)]. Likewise, when ia becomes less than iref by“h”, uVdc/2 is switched to its highest level (Vdc/2, u = +1)in order to increase the current. For the inverter of Fig. 1(a), uassumes the value +1 for the switching logic S1 = 1, S2 = 0and −1 for S1 = 0 and S2 = 1. A three-phase system can alsobe simply implemented using three independent single-phasehysteresis current regulators.

Based on the two-level hysteresis control logic described ear-lier, the control input u can be defined as follows:

if (ce (t) ≥ +h) , then u(t) = −1

else if (ce (t) ≤ −h) , then u(t) = +1. (3)

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SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1397

Fig. 2. (a) Five-level cascaded H-bridge inverter. (b) Five-level diode-clampedinverter. (c) Five-level flying capacitor inverter.

It should be noted that h is a suitable hysteresis band, whosesize is determined by the maximum allowable switching fre-quency of the switching devices, as well as the maximum per-mitted level of current distortion. A low value of h may lead toincreased switching actions, henceforth, larger switching losses,while a large value of h may result in increased distortion in thecontrolled current. Therefore, a tradeoff is always required indesigning the hysteresis band size.

As only two dc voltage levels are available, the two-level hys-teresis control is relatively straightforward with each hysteresisboundary being mapped essentially to one converter-phase-legswitched state. However, for multilevel converters, as a largernumber of output voltage levels are available, the task is to selecta particular voltage-level output to force the control variable tozero on an instantaneous basis once it exceeds certain bound-ing limits. Therefore, a multilevel hysteresis modulator (MHM)requires additional logic to select the appropriate voltage levelat any time instant so as to confine the control signal within aspecified hysteresis band.

The starting point toward the design of an adequate MHMcould be the following: according to the instantaneous valueof the controlled system variable (uc ), the controller shouldsuggest what is the most suitable voltage level required. At anyinstant, when uc exceeds a hysteresis limit, the next higher (orlower) voltage level should be selected in an attempt to force itwithin the specified limits. However, this new converter voltagelevel may not be adequate to return uc to the specified limits.When this happens, the converter should switch to the nexthigher (or lower as appropriate) voltage level, and the processshould cease only when the correct voltage level is selectedthat reverses the direction of uc . To exemplify it further, oneof the standard multilevel inverter topologies, the single-phase-leg five-level configurations of which are shown in Fig. 2, canbe considered [14]. For a five-level inverter, van in (1) may bedefined as van = nVdc , where n = 1/2, 1/4, 0, −1/4, and −1/2,as a five-level inverter may select between voltage levels Vdc/2,Vdc/4, 0, −Vdc/4, and −Vdc/2 for the net dc-link voltage ofVdc . Then, in a similar manner as described earlier, ce can bekept limited to a specified band by selecting a higher or lowervoltage level than its present output depending on the polarityof ce [15]–[34].

Fig. 3. MB five-level hysteresis current control.

To implement the logic for correct voltage-level selection,various schemes available in the literature have been describedin the following sections on the basis of a single-phase five-levelinverter. In Section II, the multiband (MB) MHM scheme ispresented, which has the feature of floating voltage levels at theboundaries of the band with symmetric inner bands placement.In Section III, the multioffset-band (MOB) approach is pre-sented, which allots fixed voltage levels at the band boundariesand needs to check the slope as well as the band region of thecurrent error. A modification to this approach is also presented,so that it can be easily extended for higher level inverter systemsand tracks the reference more efficiently. Further, a time-based(TB) approach for MHM is presented in Section IV, which canbe used to put a limit on maximum switching frequency as wellas to achieve improved performances. The detailed simulationand experimental results for all these schemes have been pre-sented to validate their functioning. Furthermore, a comparativeevaluation of these schemes has been also presented.

II. MB HYSTERESIS MODULATION

The MB hysteresis modulation scheme for the multilevel con-verters uses symmetrical hysteresis bands to control the switch-ing so that the inner band causes switching between adjacentlevels, while the outer band causes an additional switching levelchange whenever necessary. The process, first proposed in [15]and later used in [22], [26], [31], [32], is shown in Fig. 3 in theform of current regulation. Whenever the current error crossesthe inner boundary B, the inverter output is decreased or in-creased by one level (depending on which hysteresis boundaryhas just been crossed). Generally, this voltage change will causethe current error to reverse its direction without reaching thenext outer band. However, if the error does not reverse, it willcontinue through the boundary of B to the next outer boundary(placed at ΔB out of B). At this point, next higher or lower levelvoltage will be switched. This process continues as discussedearlier until the current error direction reverses. It is importantto note that if the voltage level applied at a boundary crossing ofthe current error is insufficient to force the error back, no nextvoltage level is applied as the error again crosses this boundarynext time after the previous voltage level change with the same


Fig. 4. MB five-level hysteresis modulation. (a) Current error and hysteresisband plots. (b) Inverter output voltage.

slope. The error in that case is allowed to go until the next volt-age level change at next higher or lower boundary crossing ofthe error to force it back as is evident from Fig. 3.

To further illustrate the principle of MB scheme, simulationstudies are performed on a five-level inverter, supplying an RLload of R = 35 Ω and L = 30 mH with the dc-link voltage of80 V. The back EMF voltage (vback) is taken as zero and theinverter devices are assumed nearly ideal. The output currentof inverter (ia ) is controlled using the MB hysteresis scheme(see Fig. 3) to follow a sinusoidal reference having peak-to-peak values of ±1.0 A. Corresponding to Fig. 3, the hysteresisband sizes are taken to be B = 0.04 A and B1 = B2 = 0.02 A.These values are taken for simplicity by following the consid-erations presented in [16]. All the simulation results presentedin this paper for hysteresis modulation have been obtained byusing the same set of parameters for a five-level inverter. Fig. 4shows the simulation results obtained with the MB scheme. Itis evident that the error is contained within the allotted bandsby the corresponding voltage levels appearing at the output ofthe inverter. The error trajectory can be similarly followed byreferring it from Fig. 3.

Fig. 5 shows the simulation results obtained under the sameload conditions as earlier, but imposing a current reference ofhalved amplitude at 45 ms in the simulation run, and thus,testing it for a transient condition. If the rms value of the currentrequired is lower (the load being the same), the rms value of thevoltage must be lower. Fig. 5 shows that the control techniqueis self-adapting in an automatic and natural way; therefore, theconverter feeds the load by using the lower voltages levels only[±Vdc/4 and 0, Fig. 5(c)]. It is also seen from Fig. 5(c) thatas soon as the step reference change occurs, the correspondingextreme voltage level (−Vdc/2) appears at output of the inverterto rapidly force the current error back within the specified bands.It should be noted that if the change in reference is not that large,following a step change in the demanded current, the controllerwill remain in the corresponding switching state required tofollow the reference as closely as possible until the currenterror reaches the hysteresis band. Hence, the advantages of amultilevel topology are fully exploited by this scheme. The fast-

Fig. 5. Transient performance of MB scheme. (a) Current error and hysteresisband plots. (b) Reference and measured load current. (c) Inverter output voltage.

Fig. 6. Overall structure of the experimental setup.

transient response of the current regulator can be appreciatedfrom the results shown in Fig. 5(b).

A. Experimental Setup

An experimental setup is used to test the MHM schemes dis-cussed in this paper. A prototype of a single-phase five-levelinsulated gate bipolar transistor (IGBT)-based diode-clampedinverter is built in the laboratory. The overall structure of theexperimental setup is shown in Fig. 6. The main power cir-cuits consist of a single-phase five-level voltage source diode-clamped inverter, load, and dc-link circuit. The inverter dc bus issupported by a separately controllable dc supply obtained froma single-phase transformer and diode rectifier circuit. The dc-link voltage and load parameters of the inverter are kept same as


considered earlier in the simulation studies, i.e., Vdc = 80 V andR = 35 Ω, L = 30 mH, respectively. In Fig. 6, HV2–HV5 de-notes the Hall effect voltage transducers for sensing the dc-linkcapacitor voltages and HC1 represents the Hall effect currenttransducer sensing the inverter load current (ia ). Each semi-conductor switch shown in Fig. 6 consists of an IGBT withan antiparallel diode. The IGBT modules used is MitsubishiCM75DY-24 H. This is a 1200 V/75 A IGBT with two IGBTs/diodes in each module. For simplicity, the same IGBT modulesare also used as clamping diodes with a shorted gate in the in-verter, as shown in Fig. 6. The presence of back EMF wouldserve to create more variation in switching frequency, but with-out affecting the nature of the current error trajectory. Therefore,for simplicity, back EMF voltage source has not been used.

In the experimental setup, a chopper circuit for the dc capaci-tor voltages equalization has also been used, as shown in Fig. 6.Its working principles and operational features can be referredfrom [35]. Without any dedicated control or additional hardware,the dc-link capacitor voltages tend to unbalance under most ofthe operating conditions in a diode-clamped inverter [35], [36].This chopper circuit of Fig. 6 keeps the dc-link capacitor volt-ages balanced so that the inverter is able to generate five differentand correct voltage levels. It is also important to mention herethat the chopper action is unaffected by the different hysteresismodulation methods used in this paper. The dc-link capacitorsare Cd1 = Cd2 = Cd3 = Cd4 = 220 μF and the chopper circuitparameters are R1 = R2 = 2.0 Ω and L1 = L2 = 20 mH. Fur-ther structural and operational details of the chopper are notgiven here as these are not in the context of this paper.

In Fig. 6, the block diagram for PC interfacing and othercontrollers are also shown. The low-voltage signals from thetransducers connected to the power circuits are used as inputsto various controllers. The inverter load current signal is ac-quired by a PC (P−1 V, 2.4 GHz) through AD converter (ADC)channels of a standard data acquisition card (NIDAQmx PCI-6259) [37]. A sinusoidal reference input (iref ) is also fed throughthe ADC channels. Based on these quantities, a program writ-ten in Borland C++ is implemented for the control tasks. Thecorresponding switching decision signals are generated at thedigital-output port of the DAQ and are passed to the IGBTdriver circuits after introducing a lockout delay using blankingcircuits. IGBTs require gate voltage signal in order to estab-lish collector to emitter conduction or nonconduction. A single-phase five-level inverter topology associated with the choppercircuit of Fig. 6 needs 12 gate drivers. Mitsubishi M57959 Lhybrid IGBT driver modules are chosen to perform this task.This is a high-speed component that is endowed with a voltagelogic-level input and insulated by a high-speed optocoupler thatprotects against the event of a short circuit [38].

For the MB scheme described earlier, the current refer-ence and hysteresis band sizes are considered same (1.0 A,B = 0.04 A, and B1 = B2 = 0.02 A) as considered earlier inthe simulation studies presented. Fig. 7(a) shows the perfor-mance of the MB hysteresis current controller. As expectedand described earlier corresponding to the simulation results inFig. 4, the controller is able to keep the current error in thedefined hysteresis band. Fig. 7(b) shows the load current along

Fig. 7. Experimental results showing the MB hysteresis modulation perfor-mance. (a) Inverter output voltage and current error. (b) Inverter output voltageand controlled load current.

with the output voltage. By comparing the experimental resultswith those of the simulation results presented earlier, it can besaid that the experimental results match closely with the simu-lation results, as expected.

An advantage of this MB hysteresis control is that the (n − 1)bands used here for an n-level inverter center about the zero-error axis. In this case, the average value of the current errorapproaches zero even when current ripple periods are consid-ered [15]. Therefore, no dc-tracking error is introduced intothe output current (no analog offset compensation circuitryrequired).

III. MOB HYSTERESIS MODULATION

As opposed to the MB scheme, which uses symmetricallyplaced hysteresis bands for current error regulation, the MOBscheme uses the bands placed with an offset around the zero-current error line. The advantage of using the offsets is thatdifferent bands can be easily implemented. Also, the corre-sponding logic can also be easily programmed/implemented ina way that if the voltage appearing at the boundary of a bandis insufficient to force the error back, it is allowed to move tothe other band. As opposed to the previously presented scheme,fixed voltage levels are applied in MOB scheme as the currenterror crosses a boundary of the band with a certain slope. In thissection, first the conventional MOB scheme is presented, andthen, its modified version is presented, which offers improvedperformances.

A. Conventional MOB Hysteresis Modulation

A MOB scheme was proposed in [17] and [26] on the basisof a three-level inverter. In this scheme, the current can be con-trolled using n − 1 offest bands for an n-level inverter. Fixedvoltage levels are switched at each of the offset boundaries whenthe current error crosses the boundary of an offset band in a di-rection, away from the zero error line. A possible two-offsetband arrangement (B1 , B2) for controlling a three-level inverteris shown in Fig. 8. It is shown in the figure that as the error(Ce ) touches the corresponding boundaries of B1 and B2 , fixedoutput voltage levels are switched. The switching takes placewhen sign of the error and its slope at the boundary of a bandare same, and the previous switching had not taken place at thesame boundary of the same band. For example, positive errorand positive slope at p1 and negative error and negative slope


Fig. 8. Three-level MOB hysteresis modulation.

Fig. 9. Five-level MOB hysteresis modulation.

at p2 cause the switching (see Fig. 8). It can be followed that 0voltage level is switched at the inner limits of B1 , B2 , −Vdc/2at the upper limit of B1 , and +Vdc/2 at the lower limit of B2 . Itcan also be seen from Fig. 8 that the selection of voltage levelsfor limiting the current error occurs from lower to higher valuethrough a step and without skipping any intermediate level. Thisconfirms an optimized use of the available voltage levels.

The MOB scheme seems to work well for a three-level in-verter, as it utilizes all the available voltage states in an optimizedmanner to confine the current error within the limits defined bythe outer boundaries (B1 and B2 in Fig. 8). However, if the samescheme with the same logic sequence is applied to any higherlevel inverter, its optimization is lost [16]. To exemplify it, letus consider a five-level multioffset hysteresis current regulationwith Fig. 9 showing a possible current error trajectory alongwith the offset-band arrangements and corresponding switchedoutput voltage levels. By following the scheme of [17], it re-quires four bands (B1 − B4) and as the current error touchesthe corresponding boundaries of B1 − B4 , fixed output voltagelevels are switched. It can be followed that 0 V is switched at thelower limits of B1 , B3 and upper limits of B2 , B4 ,−Vdc/4 at theupper limit of B1 , +Vdc/4 at the lower limit of B2 , −Vdc/2 atthe upper limit of B3 and +Vdc/2 at the lower limit of B4 . Thelimitation, when using this scheme for a higher level invertercan be seen by looking at the current error path from F to G.It is evident that a voltage-level transition from −Vdc/2 to 0 Voccurs at G, thereby, skipping the level −Vdc/4. This results ininverter output voltage with large steps and large voltage stressacross the devices at the switching instants.

Fig. 10. MOB five-level hysteresis current control with fixed voltage appliedat the band crossings of the current error. (a) Current error trajectory along withthe allotted bands. (b) Inverter switched output voltage.

To get a further insight into operational performance of thefive-level hysteresis control of Fig. 9, a simulation study isperformed using this scheme with the same inverter parameters,load parameters, reference current value as considered in theprevious section and the hysteresis band sizes of B1 = B2 =0.06 A and B3 = B4 = 0.08 A. Fig. 10 shows the simulationresults under this case, where it is evident that this control resultsin a poor quality voltage waveform. To justify this observation,let us first focus on the current error trajectory in Fig. 10(a).As suggested earlier, between the points ta and tb , the errorvariation outputs the voltages 0 and +Vdc/4. As the error movesaway from tb , it touches the lower boundary of B1 (see Fig. 10)at tc . By definition, at tc , 0 voltage level is switched. However,before tc , the output voltage was +Vdc/4 and at tc , the erroris moving away from the zero line in the negative direction.Therefore, +Vdc/2 was required to force the error in oppositedirection. But due to the logical sequence of control, 0 voltagelevel is applied at tc , resulting in further increase in the negativeslope of the current error away from the zero line. The error thentouches the lower boundary of B2 , and then, B4 . This resultsin consecutive switching of +Vdc/4 and +Vdc/2, respectively.This operation is repeated in the consecutive switching cyclesand the voltage waveform is degraded. It is also evident that inthis process, the intermediate level +Vdc/4 is skipped as thecurrent error travels from tf to the upper boundary of B2 .

It should be noted that since the current error remains in theallotted bands, the controlled current follows its reference. It isthe voltage waveform, which is degraded. However, as is evidentfrom Fig. 10, the error is bounded within a smaller band (B1or B2) in the region when switching the voltage levels 0 and±Vdc/4, while due to the control actions of this scheme, theerror is bounded within a larger band (B3 or B4) in the regionwhen it is required to output one of the two extreme voltagelevels (±Vdc/2). This results in variable-tracking performancein a single cycle of the current waveform itself.

B. Modified MOB Hysteresis Modulation

To overcome the drawbacks of the multilevel control of Fig. 9,a modified MOB (MMOB) hysteresis control is presented [16].The band placement and functioning of MMOB scheme for afive-level inverter is shown in Fig. 11. In this scheme, the currenterror is required to be bounded mainly between the bands B1


Fig. 11. MMOB five-level hysteresis modulation.

and B2 , which are displaced by a small offset ΔB. Further, twoadditional offsets of the same width ΔB are placed out of B1and B2 to provide a reliable and robust control. In general, a totalnumber of n − 2 offsets are required for an n-level inverter inboth the positive- and negative-current-error regions. It differsfrom the MOB method in the decision logic of output voltagelevels at the crossing points of current error and correspondingboundaries of the hysteresis bands and also in the total numberof bands required.

In the MMOB approach, the applied output voltage at the bandcrossing points of current error is not fixed, but depends on theprevious voltage level, i.e., just before the crossing point. In thisscheme, the next voltage level is applied if a positive/negativeboundary of B1 or B2 or ΔB is crossed with positive/negativeslope for the first time. If this action is insufficient, the error willcross the same boundary second time. In such a situation, no ac-tion is taken until the next higher or lower boundary of anotherband is reached. This reduces the number of switching. If the cur-rent error crosses the positive boundary of a band with positiveslope, next lower (than the previous) voltage level is switched(e.g., at A in Fig. 11). Similarly, if the error crosses the nega-tive boundary of a band with negative slope, next higher (thanthe previous) voltage level is switched (e.g., at M in Fig. 11),with the earlier stated constraints applied. The advantage ofMMOB method of Fig. 11 over the MOB method is evident inthe manner that with MMOB method, output voltage quality isimproved and the current follows its reference with minimumchange in voltage levels needed. This guarantees that there isno skipping of the intermediate voltage levels. It should also benoted that in this scheme, the number of offset bands is decidedby the number of steps needed to switch the voltage from oneextreme (+Vdc/2 or −Vdc/2) to another extreme (−Vdc/2 or+Vdc/2, respectively) as the error travels from positive (nega-tive) to negative (positive) region. This can be further understoodby following the error trajectory from M to Q in Fig. 11.

Another simulation study is performed using the MMOBscheme with the same inverter parameters as considered ear-lier and hysteresis band sizes as B1 = B2 = 0.06 A and ΔB =0.02 A. Fig. 12 shows the results. Similar current error trajec-tory analysis can be performed in Fig. 12 to justify the better

Fig. 12. MMOB five-level hysteresis modulation. (a) Current error and thehysteresis band plots. (b) Inverter output voltage.

Fig. 13. Transient performance of MMOB modulation. (a) Current error andhysteresis band plots. (b) Reference and measured currents. (c) Inverter outputvoltage.

waveforms using the control scheme of Fig. 11. A compari-son of Fig. 12 with Fig. 10 shows that in the new scheme, theswitching always occurs between adjacent levels and no voltagelevel is skipped. Also, as opposed to MOB scheme, the current-tracking performance remains uniform throughout a completeload current cycle in MMOB scheme (see Fig. 12), as the cur-rent error is mostly bounded within the hysteresis bands of samewidth. It should be noted that, in Fig. 10, the controller acts asdesired when switching between +Vdc/4, 0, and −Vdc/4 anddegrades when higher voltage levels (±Vdc/2) are needed tobe switched. This indicates that fixed voltage-level switching asin [17] works fine for the three-level inverter and needs modifi-cation (as in Fig. 11) for higher level inverters.

Fig. 13 shows the simulation results, obtained under the sametransient condition, as considered in the previous sections. It isevident from Fig. 13 that the control technique is self-adaptingin an automatic and natural way in the same manner as discussedearlier. Hence, the advantages of a multilevel topology are fullyexploited by this scheme as well. The fast-transient response ofthe current regulator can be appreciated from the results shownin Fig. 13(b). As the band sizes are small, it is difficult to dis-tinguish between the load current and the alternating reference[dashed line in Fig. 13(b)], which also confirms that the trackingis exact.


Fig. 14. Experimental results showing the MOB hysteresis modulation per-formances. (a) Inverter output voltage and current error with the MOB method.(b) Inverter output voltage and current error with the MMOB method. (c) Loadcurrent with the MMOB method. (d) Inverter output voltage and load currentwith halved hysteresis band sizes and with the MMOB method.

The experimental investigations are carried out to validate theMOB and MMOB schemes with the same experimental setupas discussed in the previous section. The system parameters aresame as considered in the simulation studies presented earlier.Fig. 14(a) shows the performance of MOB modulation. As ex-pected and described earlier corresponding to the simulationresults in Fig. 10, though the controller is able to keep the cur-rent error in the defined hysteresis bands, it suffers from poorinverter output voltage due to skipping of the intermediate volt-age levels. Fig. 14(b) and (c) shows the performance of MMOBmodulator with the same parameters. In Fig. 14(d), the resultsshow the performance of MMOB modulator with halved valuesof B and ΔB. Its better performance can be appreciated fromthe results shown and can be justified from the discussions pre-sented earlier. It should be noted that the load current shownin Fig. 14(c) is almost same with both the MOB and MMOBmethods as both are able to limit the error within the specifiedbands. The experimental results confirm the correctness of sim-ulation and validate the similar behaviors described previouslyin the simulated cases. It should also be noted that since in boththe conditions, the current error is bounded between the allottedlimits, the controlled current waveform in all the cases resem-bles with the one presented in Fig. 14(c). Further, the trackingof the reference load current in the two cases can be confirmedby looking at the current errors presented in Fig. 14(a) and (b).

As can be seen from Figs. 8–14, one disadvantage of thisscheme is that the offset placements of the hysteresis bands aboutzero error introduce a steady-state tracking error. In steady state,the average value of the current error in Fig. 12(a) approacheszero only if the fundamental periods are considered. It doesnot increase the total harmonic distortion (THD) value of thecurrent, but causes a decrease in the fundamental harmonic com-ponent. This problem may become a severe one if more thanfive voltage levels are to be employed in which case a nonnegli-

Fig. 15. TB five-level hysteresis current control.

gible phase lag between the load current and its reference mayoccur [15]. To counteract this dc offset, an offset compensationstrategy to ensure zero average current error within each switch-ing period is required for improved performance. Usually, this isachieved by adding a compensating factor of half the hysteresisband offset magnitude to the load current reference [15], [17].This technique is robust, but has the general limitation of requir-ing increasingly complex analog circuitry for implementing themultiple hysteresis bands and offset compensation as the num-ber of voltage level increases. Therefore, the MOB hysteresismethod has not found wide applications.

IV. TB HYSTERESIS MODULATION

As discussed earlier, although the MOB schemes are easyto implement [15], it requires offset compensation signals tobe added to the controlled system variable, since the bands arenot symmetric about zero. The MB scheme, presented earlierin Section II, does not suffer from this steady-state-trackingerror problem, but may still not have evenly symmetric currenterror waveform, especially for nonsinusoidal current references.In the following, a TB MHM is first described, which workson the principle of controlling the system variable within asingle band so that any type of current offset can be avoided.Then, a modified TB approach for MHM is discussed, whichshows much better performances in terms of tracking as well ascan be used with a limit on the maximum allowable switchingfrequency.

A. TB Multilevel Hysteresis Modulation

A TB multilevel hysteresis control scheme was proposedin [15] to use only one hysteresis band to detect an out-of-bounds current error. Digital logic is used to select the “correct”voltage level in response. Upon detecting the error exceeding theupper (or lower) hysteresis limit, the inverter output is switcheddown (or up) one voltage level so as to return the error back tozero, as earlier. But if the new inverter switched state is inad-equate to reverse the error back to zero, the output is switchedfurther down (or up) until the current-error direction reverses. Apossible current error trajectory and inverter switched output fora five-level inverter are shown in Fig. 15. Referring to Fig. 15,the objective of this method is to force the current error in amanner so that it remains within band B. It is evident that the


Fig. 16. TB five-level hysteresis modulation. (a) Current error and the hys-teresis band plots. (b) Inverter output voltage.

inverter output is switched one level up or down as the currenterror touches the boundary of B. If this changed output is insuf-ficient to force the error back toward zero (as at W ), next higheror lower voltage level is switched at the next crossing point ofthe error and the band limit (as at X). From Fig. 15, it is obviousthat the technique does not create the steady-state tracking errorof the MOB approach.

To improve the performance and robustness of this technique,a current error slope detection algorithm was used in [18] toswitch the voltage levels. An outer band was also placed to allowswitching to the extreme voltage levels for rapid current errorreduction during transient conditions (at ΔB out of B, Fig. 15).An additional band placement was also introduced in [19] forhigher level inverters. Further, a lockout delay (TB control) wasproposed to be added (in [20]) in the switching process for a fixedduration (say, t1) immediately after an inverter state changes tocompensate for short delay between the generation of gatingsignals and sensing of the current error and its derivative. ThisTB approach can be seen in Fig. 15 between the instants Y andZ. It is evident that as the error keeps on increasing even ifa voltage level change has occurred at Y , after a certain timedelay (t1 , between the instants Y and Z), another voltage levelchange at Z forces the error in the opposite direction.

To further illustrate the principle and functioning of thescheme of Fig. 15, simulation studies are performed using thisscheme with the same system conditions as considered earlierand B = 0.04 A and ΔB = 0.02 A. Fig. 16 shows the resultsobtained. With the system parameters under consideration, itis evident that the current error is confined within band B byselecting the voltage levels one after another in the manner dis-cussed earlier.

To look into detail, the functioning of this scheme and ob-serving the TB control, another simulation study is performedwith the same parameters and two small-step changes in thereference current magnitude at instants 14.013 ms (tk , Fig. 17)and at 14.23 ms (to , Fig. 17) in the simulation run. The valueof fixed delay t1 (defined earlier) is taken 0.2 ms. The corre-sponding results are shown in Fig. 17. It can be seen that at tm ,when the current error crosses the boundary of B, the inverterswitched output voltage (−Vdc/4) is insufficient to force it backwithin B, and therefore, the error keeps on increasing. How-ever, when the time period for which the error remains outsideB with positive slope exceeds t1 , next lower voltage level is

Fig. 17. Control details of the TB hysteresis modulation. (a) Current errorand hysteresis band plots. (b) Inverter output voltage. (c) Time interval betweenconsecutive switching instants (in microsecond).

switched to provide extra force on the error to return back [e.g.,−Vdc/2 is switched at tn in Fig. 17 (c)]. In this way, the TBcontrol is operative to control the current using the n numberof available voltage levels for an n-level inverter. Now, at to ,when a relatively larger change in reference magnitude is im-posed, the current error comes out of the defined outer band attp [see Fig. 17 (a)]. As stated earlier, this outer boundary at ΔBbelow B is placed to allow switching to the extreme voltagelevels for rapid current error reduction during transient condi-tions. Therefore, as can be seen from Fig. 17 (b), the extremepositive voltage level (+Vdc/2) is switched at tp to rapidly forcethe error back within B. The resulting error trajectory can besimilarly analyzed as detailed earlier.

Although the technique of [15] with the improvements of[18]–[20] offers good performance, it needs to be further modi-fied for better performance under all loading conditions and forvery narrow hysteresis band sizes. Under certain loading condi-tions and/or for very narrow hysteresis band sizes, the currenterror variations are rapid. In these cases, the error may not re-verse suddenly at the boundaries of B (if it has to), but maytake some finite time (say, t2) depending on the applied volt-age level, hysteresis band size, and the load parameters. Thistype of phenomena may also occur under synchronous detuningproblem, which may occur in hysteresis control operation [21].For these cases, let us suppose t3 be the time interval for whichthe current error slope is positive (or negative). Now, if t3 ismore than the fixed delay t1 (defined earlier), the next higher orlower voltage level is switched after t1 according to the switch-ing logic of [20]. This means that unnecessary voltage-leveltransition has taken place as the voltage level appearing just atthe boundary of B was sufficient enough to force the currenterror direction (though, after t2). Therefore, it can be said thatthe current error slope detection with TB control may affect thehysteresis controller performance depending on various factors.A possible solution is to set a value of fixed delay t1 , which islarge enough for any t3 . This means that the switching process isceased for a large t1 , each time after the inverter output voltage is


Fig. 18. Modified TB five-level hysteresis current control.

switched. However, the value of t1 is required to be tuned basedon the parameters of the selected sensing device and differentia-tor logic [20]. Further, it has to be sufficiently small consideringthe size of ΔB (e.g., for the case when the error moves from theboundary of B toward outer boundaries at ΔB, Fig. 15). Theseconsiderations result in a very small value of t1 . Therefore, forvarying load and under high-switching frequency operation, thisis not a reliable solution. Another limitation of this scheme isthat the two processes: 1) ceasing of the switching process fort1 after a voltage level change at B and 2) switching the voltagelevel if the current error slope is still positive (negative) after t1from a voltage level change at B, are locked through t1 . Since t1is mostly dependent upon sensor parameters (which are fixed)and the current error slope is mostly load dependent (which canvary), the approach certainly lacks robustness. Further, sincethis approach needs to measure the derivative of the currenterror, noise amplification may occur at the sensing end of thecontroller, which needs extra hardware to filter it out [20].

B. Modified TB Hysteresis Modulation

To counter the limitations of the aforementioned TB scheme,an efficient modified TB multilevel hysteresis control schemewas proposed in [16] and is shown in Fig. 18. This approachrequires (n − 2) outer bands at ΔB from their inner ones for ann-level inverter. Further, the current error slope-detection-basedcontrol (of [20]) is replaced by the algorithm of detection ofonly sign of the current error slope. The use of extra bands in themodified scheme implies that, for example, if the current errorcrosses B with a certain voltage switched at the boundary of B,the next voltage level will not be switched until the error touchesthe outer band at ΔB from B. By doing so, the situation likethat discussed in the earlier paragraph can be clearly avoided fora sufficient width of ΔB. The TB control, however, is retainedin the control process, though, for a different purpose. This isfor the case when the two consecutive crossings of the currenterror and the band limits are too small timewise. For example,as shown in Fig. 18, the time interval between the instants Pand Q is considered smaller than t1 , and therefore, anothervoltage level change does not occur at Q. Subsequently, the

error reaches at S so that a change in voltage level causes itsreversal. Therefore, in effect, this method replaces the currenterror derivative detection control by a number of fixed-widthbands.

Defining the modified scheme of Fig. 18 with respect to themethod of Fig. 15, it can be said that, the modified method re-places the combined monitoring of the vertical movement of thecurrent error and horizontal movement of the time (of [20]) byonly the single monitoring of the vertical movement of the cur-rent error in deciding to switch the next voltage level out of B.This replacement is logical as the main aim of all the hysteresiscontrol remains to check the vertical movement of the error (i.e.,away from the zero current error line). The switching decisionsare taken only at the boundaries of the bands when the currenterror moves away from the zero line. At each such crossing, theinverter output is changed by one step (e.g., from 0 to +Vdc/4,or to −Vdc/4, etc.). In the lower boundary regions, the out-put voltage state changes from lower to higher (i.e., −Vdc/2 to−Vdc/4,−Vdc/4 to 0, 0 to +Vdc/4, and +Vdc/4 to +Vdc/2) andin the upper boundary regions, from higher to lower (i.e., Vdc/2to Vdc/4, Vdc/4 to 0, 0 to −Vdc/4, and −Vdc/4 to −Vdc/2).At the outermost boundaries, the corresponding extreme outputvoltage levels (+Vdc/2 and −Vdc/2) are applied for rapid cur-rent error reduction during transient conditions. These voltage-level transitions ensure that the controlled current follows itsreference with minimum control force needed. The switchingstrategy can be further understood from Fig. 18. At point M , thecurrent error crosses the lower boundary of B. Before this point,the output voltage state was −Vdc/2. Therefore, the next highervoltage level (−Vdc/4) is applied at M . The current error thenfollows the path as shown, and at the crossing points shown inthe figure (i.e., N , etc.), voltage state transition takes place asmentioned earlier. A total number of (n − 1) bands required foran n-level inverter in this scheme can be justified by followingthe current error trajectory in Fig. 18 and the discussions pre-sented in the earlier presented schemes. It is also clear that itcan efficiently work under varying load conditions as well.

Based on the earlier discussion, the switching decisions underthis scheme can be defined with respect to Fig. 18 for an n-levelinverter as follows:

if

{Ce ≥ 0 and

dCe

dt> 0

}, then u(tk ) = u(tk−1) +

1n − 1

else if

{Ce < 0 and

dCe

dt< 0

}, then u(tk ) = u(tk−1)−

1n− 1

.

(4)

In (4), u(tk ) is the current value of the switching decision,while u(tk−1) is its immediate past value. This can be justifiedfrom Fig. 18 in which, tk−1 , tk , etc., shown on the horizontalaxis are the time instants at which Ce crosses the earlier definedboundaries of the bands. It can be seen that depending on the signof Ce and dCe/dt, the output voltage level is either increasedor decreased by Vdc/4, at the crossing points. Note that, theinverter holds its output voltage level until tk , which it attainedat tk−1 . It is also to be noted that with Ce > 0, dCe/dt < 0,and with Ce < 0, dCe/dt > 0, no voltage transition takes place


Fig. 19. Modified TB five-level hysteresis current control. (a) Current errorand hysteresis band plots. (b) Inverter switched output voltage.

at the crossing points. This is because, in these regions, thecontrol signal is heading toward zero line, which implies thatthe error between the controlled current and its reference value isreducing with the present output voltage level. Hence, no voltagetransition is required for this. Another point to be noted is that, noexact evaluation is needed for the current error slope, as only thesign of the current error slope is needed at its crossing points withthe band limits. At each sampling instant in the measurementprocess, the current value of the error is compared with itsprevious value. A positive value of this difference indicates apositive slope, while the negative value indicates a negativeslope [16]. Therefore, this scheme does not suffer from noiseamplification problem as in [20].

To get further insight into the modified TB scheme of Fig. 18and exemplify its working, simulation studies are performed ona five-level inverter with the current reference and inverter, andload parameters being the same as considered earlier and withhysteresis band sizes of B = 0.04 A and ΔB = 0.02 A. Thevalue t1 (delay in the TB control) is taken to be 200 μs. This valueof t1 is purposely taken to be almost equal to the minimum timeinterval between two consecutive switching decisions under thegiven system conditions to have a better viewing of the controllerperformance. The simulated waveforms are shown in Fig. 19.The current error variation across the hysteresis bands can befollowed from the discussions presented earlier correspondingto Fig. 18. It is evident that at tq , the error touches the upperboundary of B and the voltage level +Vdc/4 is switched at theoutput of inverter to force the error in the opposite direction.However, at tr , when the error crosses the lower boundary ofB, the next higher voltage level is not switched as the timeinterval between the instants tq and tr is less than t1 = 200 μs.Therefore, the error crosses B at tr and is forced back in theopposite direction at ts , i.e., at ΔB from the lower boundaryof B, where voltage level +Vdc/2 is switched. In this way, thecurrent is controlled to follow its reference by using the fourbands for a five-level inverter and a five-level output voltagewaveform is obtained [see Fig. 19(b)] for a sinusoidal referencecurrent.

It is evident from Fig. 19(a) that the TB control is also oper-ative in this scheme, e.g., between tq and tr . It should be notedthat in this scheme, the time differences between two consecu-tive switching is checked each time before a next voltage level is

Fig. 20. Control details of modified TB scheme. (a) Current error and hystere-sis band plots. (b) Inverter output voltages. (c) Time interval between consecutiveswitching instants (in microsecond).

applied to have a TB control. Further, the tuning of t1 along withB and ΔB should be properly done to have a good harmonicspectrum of the controlled current and voltage, while also takinginto consideration the maximum allowable switching frequency.This TB control applied to control the current in this schemecan also be applied to the other schemes discussed in previoussections.

To look into detail, the functioning of this scheme and observeits operation under a transient condition, another simulationstudy is performed with the same parameters and a small-stepchange in the reference current magnitude at instant 8.4 ms. (say,tt) in the simulation run. The value of t1 is taken 40 μs. Thecorresponding results are shown in Fig. 20. It can be seen thatas the current error comes out of the outermost boundary fol-lowing a step change in reference magnitude, the correspondingextreme voltage level −Vdc/2 is switched to rapidly force theerror within the band limits. However, the next higher voltagelevel −Vdc/4 switched at tu is insufficient to force the errorback. Therefore, it keeps on increasing and crosses the nextboundary at tv . However, no other voltage-level switching takesplace at tv as the time interval between tu and tv is less thatt1 = 40 μs [see Fig. 20(c)]. Therefore, the error keeps on in-creasing and even the next higher voltage level 0, switched attw , is insufficient to force the error back toward B. As a result,the error touches the next allotted boundary at tx and here, theswitched voltage +Vdc/2 forces it back toward B. After this,the consecutive control actions are processed as detailed earlier.In this way, the n number of output voltage levels control thecurrent to track its reference using the allotted hysteresis bandregions. It should again be noted that the relatively larger val-ues of t1 in these simulation studies are correspondingly takento highlight the TB control. In practice, its minimum possiblevalue is limited only by the factors discussed earlier.

Fig. 21 shows the simulation results, obtained under the sametransient condition, as considered in the previous sections withthe same inverter and load parameters. It is again evident fromFig. 21 that the control technique is self-adapting in an automaticand natural way in the same manner as discussed earlier. Hence,


Fig. 21. Transient performance of modified TB scheme. (a) Current error andthe hysteresis band plots. (b) Reference and measured load current. (c) Inverteroutput voltage.

Fig. 22. Experimental results of TB five-level hysteresis modulation withsmaller band sizes. (a) Inverter output voltage and current error. (b) Inverteroutput voltage and load current. (c) Inverter output voltage and time intervalbetween consecutive switchings.

the advantages of a multilevel topology are fully exploited bythis scheme as well.

The experimental investigations are carried out to validatethe TB modulation schemes with the same experimental setupas detailed in the previous sections. The system parameters aresame as considered in the simulation studies corresponding toFigs. 19 and 20. In Fig. 22, the experimental results correspondto the hysteresis band sizes of B = 0.04 A and ΔB = 0.02 Aas considered earlier, while in Fig. 23, the results correspond toB = 0.06 A and ΔB = 0.03 A. The results have been obtainedwith two different band sizes to generalize the performanceevaluation. It is evident from the figures that the current control isachieved by using the five voltage levels in the manner discussedearlier. The value of t1 = 200 μs is taken to be the same as usedin the simulation studies. It can be seen from Fig. 23(a) thatthe TB control is also operative as the time interval betweenthe band crossing of the current error at pX and pY is less

Fig. 23. Experimental results of TB five-level hysteresis modulation withlarger band sizes. (a) Inverter output voltage and current error. (b) Inverteroutput voltage and load current. (c) Inverter output voltage and time intervalbetween consecutive switchings.

than t1 . Hence, the error had to cross B and next voltage levelchange takes place at pZ , i.e., at ΔB from the lower boundaryof B. The corresponding time intervals between consecutiveswitching instants are shown in Figs. 22(c) and 23(c). As detailedearlier, this value is checked each time before a next voltage levelis applied to have a TB control. By comparing the experimentalresults of Fig. 22 with those of the simulation results presented inthe previous section, it can be said that the experimental resultsmatches closely with the simulation results as expected.

V. COMPARISON OF THE MHM SCHEMES

In the previous sections, various methods for hysteresis mod-ulation of multilevel converters have been described. As dis-cussed earlier, though the implementation of MOB method iseasier, it introduces a steady-state tracking error due to the offsetplacements of the hysteresis bands. This limitation is particu-larly more severe in the higher level inverters. To counteractthis dc offset, an offset compensation strategy to ensure zeroaverage current error within each switching period is requiredfor improved performance [15]. The MOB technique is robust,but has the general limitation of requiring increasingly com-plex analog circuitry for implementing the multiple hysteresisbands and offset compensation as the number of voltage levelincreases [15]. Further, the conventional MOB method has thelimitation of skipping of the intermediate voltage level betweentwo successive switching for higher level inverter. The MMOBmethod, however, does not suffer from this limitation and canbe applied to higher level inverter system as well. However, dueto its main limitation of introducing the steady-state trackingerror, the MOB method has not found wide applications.

The MB scheme uses symmetric bands to control the controlvariable and has the advantage that it does not create any dc-tracking error, and therefore, no analog offset compensationcircuitry is required as opposed to the MOB scheme. However,


it may require a more complex digital circuitry to select a voltagelevel when a change is required [15]. This is because it needsto classify the previous crossing point of the current error withthe boundary of the allotted band, each time at such crossingpoints. For example, by referring to Figs. 14 and 15, it canbe seen that when the current error reaches a boundary of theallotted band with the previous crossing point being on the sameboundary, no voltage-level switching takes place. In this case,the error travels to another higher or lower boundary placed atΔB from the boundary in question to change the output voltagelevel. However, if the previous crossing point had occurred ata different boundary, the voltage-level switching takes place.Therefore, this method is required to store the information ofprevious crossing point, which may require additional logicalcircuitry. However, with the various advanced logical deviceavailable, it may be programmed easily. Further, in this scheme,the current error waveform may still not be evenly symmetric,especially for nonsinusoidal current references. This is because,as is evident from Fig. 15, at each transfer of the output voltage-level zone [e.g., from 0, +Vdc/4 to +Vdc/4, and +Vdc/2 inFig. 15 (b)], the current error moves out of the inner band tothe outer band for next voltage level change [see Fig. 15 (a)].Due to this, a nonsinusoidal or changing current reference mayintroduce a net positive or negative shift in the current error, andtherefore, in the controlled current.

The TB method utilizes a single band to control the currentas discussed earlier. It does not suffer from dc-tracking errorproblem but does require extra analog and digital circuitry forcurrent error measurement as well as to apply the TB con-trol [16]. The modified TB approach, however, does not needto measure the current error, and therefore, does not suffer fromnoise amplification problem. Depending on the available num-ber of output-phase voltage levels of the inverter, it requires anumber of bands, but with the aim of containing the currenterror within the main band, i.e., the innermost band only. Italso does not need to store the information of previous crossingpoint, as opposed to the MB scheme. Therefore, the additionallogical or analog circuitry requirement is minimal. Furthermore,the maximum possible switching frequency may be set by corre-spondingly designing the width of hysteresis band. The modifiedTB scheme keeps track of the switching duration between suc-cessive switchings and may be designed to always keep it largerthan a certain allowed value. This modified TB control can beapplied to the other multilevel hysteresis schemes as well [16].The implementation of this TB control may be achieved by usinga time counter with a programmable logic device or by program-ming it within a computer program itself, as used in this paper.

A summary of the advantages and limitations of various mul-tilevel hysteresis regulation schemes presented in this paper isgiven in Table I.

To compare the tracking performances of the variousschemes, simulation studies are performed with the same sys-tem configurations and parameters as taken in the simulationstudies presented earlier in this section. For achieving compa-rable performances, the hysteresis band sizes are taken B =0.12 A and ΔB = 0.06 A for the TB scheme of Fig. 18, whichis three times as used in the earlier presented simulation studies.

TABLE IADVANTAGES AND LIMITATIONS OF THE VARIOUS MHM SCHEMES

The corresponding hysteresis band sizes for the MOB schemeis taken B1 = B2 = 0.12 A and B3 = B4 = 0.18 A and for theMB scheme is B = 0.12 A and ΔB = 0.06 A. It should be notedthat the main band for the current error regulation is taken ofsame widths in these three cases. The simulation studies showthe percent THD values of the controlled current is 5.45% us-ing the MOB scheme, 5.54% using the MB scheme, and 4.2%using the TB scheme. The better quality of the controlled cur-rent using the TB scheme is obvious, as it controls the currenterror mainly within a single symmetrically placed hysteresisband. Therefore, and also due to its various other advantages asdetailed earlier, the TB control of Fig. 18 is recommended.

VI. CONCLUSION

This paper summarizes and reviews the various hysteresismodulation techniques available in the literature for the multi-level converters. This includes, in general, the MB, MOB, andTB hysteresis modulation techniques. To generalize the exist-ing MHM techniques for higher level inverters, their modifiedversions have been also discussed. The basic principle of op-eration and logical sequence of the design choices has beendescribed for each of these schemes. The advantages of usingvarious accessible dc voltage levels have been fully exploitedby using these schemes. The various schemes considered inthis paper have been further investigated using simulation andexperimental studies for a five-level inverter system. However,these strategies can easily be extended to any multilevel inverterstructure, even in the case of n-level voltage waveforms andthree-phase systems.

This paper also presents a comparative analysis of the var-ious MHM schemes. Among these schemes, the modified TB


scheme offers a number of advantages in terms of better trackingperformance, extra control over maximum allowable switchingfrequency, etc. It can be expected that with further investigationof the MHM methods and the development of modern tech-nology, the hysteresis modulation will gain more popularity forcontrolling the multilevel converters in different applications.

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[35] A. Shukla, A. Ghosh, and A. Joshi, “Control schemes for dc capacitor volt-ages equalization in diode-clamped multilevel inverter based dstatcom,”IEEE Trans. Power Del., vol. 23, no. 2, pp. 1139–1149, Apr. 2008.

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Anshuman Shukla (S’04–M’09) received theB.Sc. Eng. degree in electrical engineering fromMuzaffarpur Institute of Technology, Muzaffarpur,India, in 2001, and the M.Tech. and Ph.D. degrees inelectrical engineering from Indian Institute of Tech-nology Kanpur, Kanpur, India, in 2003 and 2008,respectively.

Since September 2008, he has been with ABBCorporate Research, Vasteras, Sweden. In 2008, hewas a Research Associate in the Department of Elec-trical Engineering, University of South Carolina,

Columbia. His current research interests include modulation and control ofpower electronic converters and new converter topologies.


Arindam Ghosh (S’80–M’83–SM’93–F’06) re-ceived the Ph.D. degree in electrical engineering fromthe University of Calgary, Calgary, AB, Canada, in1983.

He is currently a Professor of power engineeringwith Queensland University of Technology, Brisbane,Australia. From 1985 to 2006, he was with the De-partment of Electrical Engineering, Indian Instituteof Technology Kanpur, Kanpur, India. His researchinterests include control of power systems and powerelectronic devices.

Dr. Ghosh is a Fellow of the Indian National Academy of Engineering.

Avinash Joshi received the Ph.D. degree in electricalengineering from the University of Toronto, Toronto,ON, Canada, in 1979.

He is currently a Professor of electrical engineer-ing at the Indian Institute of Technology Kanpur,Kanpur, India. From 1970 to 1973, he was with theGeneral Electric Company of India Ltd., Calcutta,India. His research interests include power electron-ics, circuits, digital electronics, and microprocessorsystems.

78.Hysteresis Modulation of Multilevel Inverters

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