CMOS DESIGN METHODS

Design methodologies (general)Three domainsBehavioralStructuralphysicalThree levels insideArchitecturalLogic/RTLPhysical

Evaluation of an I.C:Performance speed, power, function, flexibilitySize of the dieTime to design i.e cost of engineeringEasy of verification, test generation and testability

Design principlesHierarchyRegularityModularityLocality

HierarchyDivide and conquerDivide in modules and repeating untill each submodule is comprehensible prebuilt component availableVirtual components IP

RegularitySimilar submodulesAll level of design hierarchy: equal size transistors, standard cell type library, parameterized RAM, etc.Design reuse

ModularityWell defined functions and interfacesInteraction with other modules well characterizedBehavioral, structural and physical interfaces (function, signals, electrical and timing constraints)

LocalityWell characterized interfaces for the modulecorrespond to reduce global variables in HDLAdvantage for the clock

Design methodsMicroprocessor/DSPProgrammable logicGate Array and Sea of GatesCell-basedFull customPlatform-based design (SoC)

Programmable logicChips with Programmable logic structureChips with Programmable interconnectsChips with Programmable gate arrays

Programmable logic structureProgrammable array logic (AND OR)Vertical inputs, Selectively connected to AND OR gateHorizontal product termsAND OR gate feed IO cellFeed back

PAL

PLD as a Black Box

Use to implement circuits in SOP form

The connections in the AND plane are programmable

The connections in the OR plane are programmableProgrammable Logic Array (PLA)

f1 = x1x2+x1x3'+x1'x2'x3f2 = x1x2+x1'x2'x3+x1x3Gate Level Version of PLA

Example Schematic of a PAL

f1 = x1x2x3'+x1'x2x3f2 = x1'x2'+x1x2x3

Limitations of PLAs

PLAs come in various sizesTypical size is 16 inputs, 32 product terms, 8 outputsEach AND gate has large fan-in this limits the number of inputs that can be provided in a PLA

16 inputs 316 = possible input combinations; only 32 permitted (since 32 AND gates) in a typical PLA

32 AND terms permitted large fan-in for OR gates as wellThis makes PLAs slower and slightly more expensive than some alternatives to be discussed shortly

8 outputs could have shared minterms, but not required

Comparing PALs and PLAs

PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane less flexibility than PLAs

PALs are simpler to manufacture, cheaper, and faster (better performance)

PALs also often have extra circuitry connected to the output of each OR gateThe OR gate plus this circuitry is called a macrocell

Macrocell

Macrocell Functions

Enable = 0 can be used to allow the output pin for f1 to be used as an additional input pin to the PAL

Enable = 1, Select = 0 is normal for typical PAL operation

Enable = Select = 1 allows the PAL to synchronize the output changes with a clock pulse

The feedback to the AND plane provides for multi-level design

Multi-Level Design with PALs

f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag'where g = BC + B'C' and C = h below

22V1012 inputs10 I/OsProduct terms 9 10 12 14 16 14 12 10 824 pinsAMD introduced the 22V10Allowed register bypassing.All of this has been bipolar and fuses to this point

componentsRegister4:1 MUXTristate buffer2:1 MUX

CLK to output 8nsInput to combinational output 15ns

Programmable Logic: PALConnections of planes are realized with fuses or EPROM or EEPROM

22V10PAL

Programming SPLDs

PLAs, PALs, and ROMs are also called SPLDs Simple Programmable Logic Devices

SPLDs must be programmed so that the switches are in the correct placesCAD tools are usually used to do thisA fuse map is created by the CAD tool and then that map is downloaded to the device via a special programming unit

There are two basic types of programming techniquesRemovable sockets on a PCB In system programming (ISP) on a PCBThis approach is not very common for PLAs and PALs but it is quite common for more complex PLDs

Different ways to progam PALFusible linksUV erasable EPROMEEPROM

Fusible links

PROMfusible-link MROMcustom programmed by userOTP (One Time Programmable) properties: Once programmed, it cannot be erase.

Typical Logic Diagram

Erasable Programmable ROM (EPROM)When Program need special voltage (typically 10-25V)used amount time (typically 50 msec)Erasable: by Ultraviolet (UV) lightexamples2732 : 4K x 8 NMOS EPROM2764 : 8K x 8

Flash stores the data by removing or putting electrons on its floating gate . Charge on floating gate affects the threshold of the memory element. When electrons are present on the floating gate, no current flows through the transistor, indicating a logic-0. When electrons are removed from the floating gate, the transistor starts conducting, indicating a logic-1. This is achieved by applying voltages between the control gate and source or drain

Electrically Erasable PROM (EEPROM)Erase by Electrically (high voltage) eg. 21v generated from 5vWrite faster than PROM (5usec)During Write, internal circuitry automatically erases the cellFormer from Intel ex. 2816, 2864

An SPLD Programming Unit

The SPLD is removed from the PCB, placed into the unit and programmed there

Removable SPLD Socket PackagePLCC (plastic-leaded chip carrier)PLCC socket soldered to the PCB

PROM-Type Array

Full-PLA Array

What Function is This?

16L8 PAL

Counter design in 16R4 PAL

Programmable Logic: FPGA

Sea of GatesUninterrupted lines of Pand N diffusionsMetal interconnects over non used transistorsLines are interrupted connecting PMOS to Vdd and NMOS to Vss2-5 masks till three levels of metals, vias, interconnects

Cell-basedSSIMemorySystem level modules (processors, serial interfaces, etc.Mixed signal modulesPossible automatic generation of MSI modulesOption for power (1X, 2X, 4X.) and inputs

Full customSymbolic layout (old place transistors, wires, contacts with graphic editor)Silicon compilation: HDL that give all the views of a project, i.e. behavior, timing, logicalPlacement in a standard cell layout

Platform-based design (SoC)Processors, memory, I/O functions, FPGAUse of IP, hw/sw codesign

Design FlowsFrom behavioral specifications to layoutFront end till RTL synthesisBack end from structural specifications to Physical synthesis and layout

ASIC Design flowFig. 8.39

Automated Layout GenerationFig. 8.41

Layout Design: TimingFig. 8.43

Design EconomicsStotal=Ctotal/(1-m)Stotal : Selling priceTotal costNon-recurring engineering costsRecurring engineering costsFixed costs

Non-recurring engineering costsFtotal=Etotal+PtotalEngineering costsPersonnel cost (architectural design, logic, simulation, layout, timing, DRC, test)Prototype manufacturing costsComputerCAD softwareEducation Costs (per annum): Personnel $150 K,computer $ 10K, CAD tools (digital back end) $ 1 M shared

NREs - PrototypingMask costTest fixture costPackage toolingValues: Mask set for 130 nm about $500-1000Test fixture $ 1000-50.000

Recurring costsCost of single IC after the development phaseRtotal=Rprocess+Rpackage+Rtest

Rprocess=W/(NxYwxYpa)W = wafer cost (500-3000 $)N=Number dieYw=Die yield (70-90 %) =Packaging yield (95-99%)

Fixed costsData sheetsApplication notesMarketing and commercial costs

In 1970, Texas Instruments developed a mask-programmable IC based on the IBM read-only associative memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 JK flip flop for memory. TI coined the term Programmable Logic Array for this device.[2]A programmable logic array (PLA) has a programmable AND gate array, which links to a programmable OR gate array, which can then be conditionally complemented to produce an output.

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