5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter · 5.9 GHz to 23.6 GHz, Wideband, Microwave...

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5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter Data Sheet ADRF6780 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Wideband RF output frequency range: 5.9 GHz to 23.6 GHz Two upconversion modes Direct conversion from baseband I/Q to RF Single sideband upconversion from real IF LO input frequency range: 5.4 GHz to 14 GHz LO doubler for up to 28 GHz Matched 100 Ω balanced RF output, LO input, and IF input High impedance baseband inputs Sideband suppression and carrier feedthrough optimization Variable attenuator and power detector for Tx power control Programmable via 4-wire SPI interface 32-lead, 5 mm × 5 mm LFCSP microwave packaging APPLICATIONS Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE) GENERAL DESCRIPTION The ADRF6780 is a silicon germanium (SiGe) design, wideband, microwave upconverter optimized for point to point microwave radio designs operating in the 5.9 GHz to 23.6 GHz frequency range. The upconverter offers two modes of frequency translation. The device is capable of direct conversion to radio frequency (RF) from baseband I/Q input signals, as well as single sideband (SSB) upconversion from a real intermediate frequency (IF) input carrier frequency. The baseband inputs are high impedance and are generally terminated off chip with 100 Ω differential back terminations. The baseband I/Q input path can be disabled and a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz while suppressing the unwanted sideband by typically better than 25 dBc. The serial port interface (SPI) allows tweaking of the quadrature phase adjustment to allow optimum sideband suppression. In addition, the SPI interface allows powering down the output power detector to reduce power consumption when power monitoring is not necessary. The ADRF6780 upconverter comes in a compact, thermally enhanced, 5 mm × 5 mm LFCSP package. The ADRF6780 operates over the −40°C to +85°C temperature range. FUNCTIONAL BLOCK DIAGRAM VVA LOG DET ADC ×1 ×2 SPI ADRF6780 BIAS CONTROL QUAD SPLITTER BUFFER 32 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 SDTO SCLK SDIN VP18 VPBI IFIP AGND IFIN RST VDET VPDT VPRF AGND RFOP AGND RFON AGND SEN VPLO LOIN LOIP VPLO ALM AGND PWDN VPBB BBIN BBIP BBQN VATT VPRF BBQP 14106-001 Figure 1.
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Transcript of 5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter · 5.9 GHz to 23.6 GHz, Wideband, Microwave...

  • 5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter

    Data Sheet ADRF6780

    Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

    One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 20162017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

    FEATURES Wideband RF output frequency range: 5.9 GHz to 23.6 GHz Two upconversion modes

    Direct conversion from baseband I/Q to RF Single sideband upconversion from real IF

    LO input frequency range: 5.4 GHz to 14 GHz LO doubler for up to 28 GHz Matched 100 balanced RF output, LO input, and IF input High impedance baseband inputs Sideband suppression and carrier feedthrough optimization Variable attenuator and power detector for Tx power control Programmable via 4-wire SPI interface 32-lead, 5 mm 5 mm LFCSP microwave packaging

    APPLICATIONS Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE)

    GENERAL DESCRIPTION The ADRF6780 is a silicon germanium (SiGe) design, wideband, microwave upconverter optimized for point to point microwave radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.

    The upconverter offers two modes of frequency translation. The device is capable of direct conversion to radio frequency (RF) from baseband I/Q input signals, as well as single sideband (SSB) upconversion from a real intermediate frequency (IF) input carrier frequency. The baseband inputs are high impedance and are generally terminated off chip with 100 differential back terminations. The baseband I/Q input path can be disabled and a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz while suppressing the unwanted sideband by typically better than 25 dBc. The serial port interface (SPI) allows tweaking of the quadrature phase adjustment to allow optimum sideband suppression. In addition, the SPI interface allows powering down the output power detector to reduce power consumption when power monitoring is not necessary.

    The ADRF6780 upconverter comes in a compact, thermally enhanced, 5 mm 5 mm LFCSP package. The ADRF6780 operates over the 40C to +85C temperature range.

    FUNCTIONAL BLOCK DIAGRAM

    VVA

    LOGDET

    ADC

    1 2

    SPI

    ADRF6780

    BIASCONTROL

    QUADSPLITTERBUFFER

    32

    8

    7

    6

    5

    4

    3

    2

    1

    17

    18

    19

    20

    21

    22

    23

    24

    31 30 29 28 27 26 25

    9 10 11 12 13 14 15 16

    SDTO

    SCLK

    SDIN

    VP18

    VPBI

    IFIP

    AGND

    IFIN

    RST

    VDET

    VPDT

    VPRF

    AGND

    RFOP

    AGND

    RFON

    AGND

    SENVPLOLOINLOIPVPLOALM AGND

    PWDNVPBBBBINBBIPBBQNVATTVPRF BBQP 1410

    6-00

    1

    Figure 1.

    https://form.analog.com/Form_Pages/feedback/documentfeedback.aspx?doc=ADRF6780.pdf&product=ADRF6780&rev=Bhttp://www.analog.com/en/content/technical_support_page/fca.htmlhttp://www.analog.com/http://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfwww.analog.comhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdf

  • ADRF6780 Data Sheet

    Rev. B | Page 2 of 35

    TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 6

    Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6

    Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9

    I/Q Mode ....................................................................................... 9 IF Mode ........................................................................................ 14 Output Detector Performance .................................................. 19 Return Loss.................................................................................. 20

    Theory of Operation ...................................................................... 21 Baseband ...................................................................................... 21 Single Sideband (SSB) Upconversion ...................................... 21 LO Input Path.............................................................................. 21 Serial Port Interface (SPI) .......................................................... 21

    Applications Information .............................................................. 23

    Carrier Feedthrough Nulling .................................................... 23 Sideband Suppression Optimization ....................................... 23 Linearity ....................................................................................... 23 ADC ............................................................................................. 23 Wide Frequency Performance .................................................. 24 Layout .......................................................................................... 24 LO Input Driven Differential vs. Single Ended .......................... 25

    Register Summary .......................................................................... 27 Register Details: Wideband Upconverter .................................... 28

    Control Register ......................................................................... 28 ALARM_READBACK Register ............................................... 28 ALARM_MASK Register .......................................................... 29 Enable Register ........................................................................... 29 Linearize Register ....................................................................... 30 LO_PATH Register..................................................................... 30 ADC_CONTROL Register ....................................................... 31 ADC_OUTPUT Register .......................................................... 31

    Basic Connections for Operation ................................................. 32 Outline Dimensions ....................................................................... 35

    Ordering Guide .......................................................................... 35

    REVISION HISTORY 10/2017Rev. A to Rev. B Changes to Maximum Junction Temperature Parameter, Table 2 ... 6 Change to Table 4 ......................................................................................... 7 Changes to Figure 31 Caption ................................................................. 13 Changes to Ordering Guide ..................................................................... 35 5/2016Rev. 0 to Rev. A Change to Table 4 ............................................................................. 7 Changes to Figure 40 ...................................................................... 15 Changes to Figure 47 ...................................................................... 16 Changes to Figure 58 ...................................................................... 18 Change to Figure 84 ....................................................................... 33 Changes to Table 16 ........................................................................ 34 3/2016Revision 0: Initial Version

  • Data Sheet ADRF6780

    Rev. B | Page 3 of 35

    SPECIFICATIONS VPBB = VPBI = VPLO = 3.3 V, VP18 = 1.8 V, VPDT = VPRF = 5 V, TA = 25C, LO = 0 dBm differential drive; baseband I/Q amplitude = 15 dBm differential sine waves in quadrature with a 500 mV dc bias, baseband input termination with 100 externally, IF amplitude = 12 dBm differential sine waves, unless otherwise noted.

    Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RF OUTPUT FREQUENCY RANGE 5.9 23.6 GHz LOCAL OSCILLATOR (LO) INPUT

    FREQUENCY RANGE 5.4 14 GHz

    LO AMPLITUDE RANGE 6 0 +6 dBm IF INPUT FREQUENCY RANGE 0.8 3.5 GHz

    BASEBAND (BB) I/Q INPUT FREQUENCY RANGE

    DC 750 MHz

    I/Q MODULATOR PERFORMANCE Modulator Voltage Gain Maximum gain at maximum gain setting 10 13 dB Minimum gain at minimum gain setting 12 dB Output Noise Density Output carrier > 5 dBm 147 dBc/Hz Output carrier > 14 dBm 145 dBc/Hz Output carrier > 22.5 dBm 136 dBc/Hz Output Third-Order Intercept (OIP3) f1BB = 10 MHz, f2BB = 12 MHz, BB I/Q amplitude per

    tone = 15 dBm sine waves in quadrature with a 500 mV dc bias, 10 dB gain setting

    5.9 GHz to 10 GHz 24 dBm 10 GHz to 14 GHz 25 dBm 14 GHz to 20 GHz 27 dBm 20 GHz to 23.6 GHz 27 dBm

    Fifth-Order Intermodulation Distortion (IMD5)

    f1 BB = 10 MHz, f2 BB = 12 MHz, baseband I/Q amplitude per tone = 15 dBm sine waves in quadrature with a 500 mV dc bias, 10 dB gain setting

    65 dBm

    Output Second-Order Intercept (OIP2) f1 BB = 10 MHz, f2 BB = 12 MHz, baseband I/Q amplitude per tone = 15 dBm sine waves in quadrature with a 500 mV dc bias, 10 dB gain setting

    5.9 GHz to 10 GHz 65 dBm 10 GHz to 14 GHz 65 dBm 14 GHz to 20 GHz 66 dBm 20 GHz to 23.6 GHz 50 dBm

    Output 1 dB Compression Point (P1dB) 5.9 GHz to 10 GHz At 10 dB gain setting 10.5 dBm At maximum gain setting 11 dBm 10 GHz to 14 GHz At 10 dB gain setting 11 dBm At maximum gain setting 12 dBm 14 GHz to 20 GHz At 10 dB gain setting 10 dBm At maximum gain setting 12 dBm 20 GHz to 23.6 GHz At 10 dB gain setting 10 dBm At maximum gain setting 11 dBm

    LO Feedthrough At 10 dB gain setting (can be improved baseband dc offset adjustment)

    25 dBm

    Sideband Suppression At 10 dB gain setting 25 dBc

  • ADRF6780 Data Sheet

    Rev. B | Page 4 of 35

    Parameter Test Conditions/Comments Min Typ Max Unit IF UPCONVERTER PERFORMANCE

    Upconversion Voltage Gain Maximum gain at maximum gain setting 7 11 dB Minimum gain at minimum gain setting 14 dB Output Noise Density Output carrier > 5 dBm 147 dBc/Hz Output carrier > 14 dBm 145 dBc/Hz Output carrier > 22.5 dBm 136 dBc/Hz OIP3 f1 IF = 1810 MHz, f2 IF = 1812 MHz, amplitude per tone

    = 15 dBm sine waves in quadrature with ac bias, 7 dB gain setting

    23.5

    5.9 GHz to 10 GHz 27 dBm 10 GHz to 14 GHz 24 dBm 14 GHz to 20 GHz 22.5 dBm 20 GHz to 23.6 GHz 22.5 dBm

    IMD5 f1 IF = 1810 MHz, f2 IF = 1812 MHz, amplitude per tone = 15 dBm sine waves in quadrature with ac bias, 7 dB gain setting

    80 dBm

    Output P1dB 5.9 GHz to 10 GHz At 7 dB gain setting 10.5 dBm At maximum gain setting 11.5 dBm 10 GHz to 14 GHz At 7 dB gain setting 10 dBm At maximum gain setting 12 dBm 14 GHz to 20 GHz At 7 dB gain setting 9.5 dBm At maximum gain setting 12 dBm 20 GHz to 23.6 GHz At 7 dB gain setting 9.5 dBm

    At maximum gain setting 11.5 dBm LO Feedthrough At 7 dB gain setting (can be improved by baseband dc

    offset adjustment) 35 dBm

    Sideband Suppression At 7 dB gain setting 25 dBc Tx POWER DETECTOR PERFORMANCE

    Output Level Maximum 2 dBm Minimum 30 dBm

    1 dB Dynamic Range 34 dB Output Voltage

    Maximum 1 V Minimum 0.2 V

    Log Slope 25 mV/dB Time

    Rise PIN = off to 10 dBm, 10% to 90%, C7 = 10 pF (see Figure 83)

    134 ns

    Fall PIN = 10 dBm to off, 10% to 90%, C7 = 10 pF (see Figure 83)

    190 ns

    Response C7 = 10 pF (see Figure 83) 30 ns RETURN LOSS

    RF Output 100 differential 12 dB LO Input 100 differential 12 dB IF Input 100 differential 17 dB Baseband I/Q Input Impedance 1 M

    LOGIC INPUTS Input High Voltage Range, VINH VP18 0.4 1.8 V Input Low Voltage Range, VINL 0 0.4 V Input Current, IINH/IINL 100 A Input Capacitance, CIN 3 pF

  • Data Sheet ADRF6780

    Rev. B | Page 5 of 35

    Parameter Test Conditions/Comments Min Typ Max Unit LOGIC OUTPUTS

    Output High Voltage Range, VOH VP18 0.4 1.8 V Output Low Voltage Range, VOL 0 0.4 V Output High Current, IOH 500 A

    POWER INTERFACE VPBB, VPLO, VPBI 3.15 3.3 3.45 V VPBB, VPLO, VPBI Supply Current 1 LO path enabled, IF path disabled 340 mA 2 LO path enabled, IF path disabled 390 mA 1 LO path enabled, IF path enabled 490 mA 2 LO path enabled, IF path enabled 540 mA VP18 1.7 1.8 1.9 V VP18 Supply Current 1 mA VPDT, VPRF 4.75 5 5.25 V VPDT, VPRF Supply Current 1/2 LO path enabled, IF path disabled 180 mA 1/2 LO path enabled, IF path enabled 160 mA Total Power Consumption 2 LO path enabled, IF path enabled 2.58 W Power down 35 50 mW

  • ADRF6780 Data Sheet

    Rev. B | Page 6 of 35

    ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage

    VPDT, VPRF 6.5 V VPBB, VPLO, VPBI 4.3 V VP18 2.3 V

    Maximum Junction Temperature 125C Operating Temperature Range 40C to +85C Storage Temperature Range 55C to +125C Lead Temperature Range (Soldering 60 sec) 65C to +150C

    Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

    THERMAL RESISTANCE JA is thermal resistance, junction to ambient (C/W), and JC is thermal resistance, junction to case (C/W).

    Table 3. Thermal Resistance Package Type JA1 JC1 Unit 32-Lead LFCSP 32.95 1.14 C/W 1 See JEDEC standard JESD51-2 for additional information on optimizing the

    thermal impedance (printed circuit board (PCB) with 3 3 vias).

    ESD CAUTION

  • Data Sheet ADRF6780

    Rev. B | Page 7 of 35

    PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

    SDTO

    SCLKSDINVP18VPBIIFIPAGNDIFINRST

    VDETVPDTVPRF

    AGNDRFOPAGNDRFONAGND

    SEN

    VPLO

    LOIN

    LOIP

    VPLO

    ALM

    AG

    ND

    PWD

    NVP

    BB

    BB

    INB

    BIP

    BB

    QN

    VATT

    VPRF

    BB

    QP

    2423222120191817

    12345678

    9 10 11 12 13 14 15 16

    32 31 30 29 28 27 26 25

    ADRF6780TOP VIEW

    (Not to Scale)

    1410

    6-00

    2

    NOTES1. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PLANE.2. THE DEVICE NUMBER ON THE FIGURE DOES NOT INDICATE THE LABEL ON THE PACKAGE. PLEASE REFER TO PIN 1 INDICATOR FOR PIN LOCATIONS.

    PIN 1INDICATOR

    Figure 2. Pin Configuration

    Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VDET RF Detector Output. The voltage output is proportional to the decibel RF output power. The detector slope is

    nominally 50 mV/dB. 2 VPDT Power Supply Connection for the RF Detector. Decouple the VPDT pin with 100 pF and 0.1 F capacitors as

    close as possible to the pin. Note that this pin must always be supplied with 5 V. 3, 9 VPRF Power Supply Connections for the RF Path. Decouple the VPRF pin with 100 pF and 0.1 F capacitors as close

    as possible to the pins. 4, 6, 8, 19, 29

    AGND Analog Grounds. Connect these pins to a low impedance ground plane.

    5, 7 RFOP, RFON RF Outputs. These outputs are 100 differential outputs for the RF path. Frequency range is 5.9 GHz to 23.6 GHz. 10 VATT Modulator Output Attenuator Control Input. The RF voltage variable attenuator is controlled by applying a

    0 V to 2.6 V control voltage to the VATT pin. Increase the gain when VATT voltage increases. This pin is linear in dB over central gain range.

    11 to 14

    BBQN, BBQP, BBIP, BBIN

    I Channel and Q Channel Baseband Inputs. These inputs are high input impedance and are typically differentially terminated to a 100 resistor using an off chip termination. The nominal common-mode bias level on these pins must be 0.5 V.

    15 VPBB Power Supply Connection for Baseband Path. Decouple the VPBB pin with 100 pF and 0.1 F capacitors as close as possible to the pin.

    16 PWDN Power Down. The ADRF6780 powers up when the PWDN pin is at a low logic level (1.2 V). When the ADRF6780 is powered up, the SPI can also be used as a power-down capability. The PWDN pin has an internal 18 k pull-down resistor.

    17 RST Reset. This pin provides the ability to reset the SPI to the default register settings. Pull the RST pin to a logic high level in normal operation. Driving the RST pin to a logic low level loads the default SPI register settings. The RST pin has an internal 7.75 k pull-up resistor.

    18, 20 IFIN, IFIP IF Inputs. These inputs are 100 differential inputs for IF upconversion, and they must be ac-coupled. When the IF mode is set, remove the 0 R10 to R13 resistors from the I/Q lines. 21 VPBI Power Supply Connection. Decouple the VPBI pin with 100 pF and 0.1 F capacitors as close as possible to

    the pin. 22 VP18 1.8 V Power Supply. Decouple the VP18 pin with 100 pF and 0.1 F capacitors as close as possible to the pin. 23 SDIN Serial Data Input. Serial data applied to the SDIN pin is loaded into the SPI register upon a successful write

    command as indicated in the timing diagrams (see Figure 68 to Figure 70). The first most significant bit (MSB) is a control bit and it determines whether data is written to the register (logic high) or read from the serial data output pin (logic low). The SDIN pin has an internal 18 k pull-down resistor.

    24 SCLK Serial Clock. This pin is the clock input for the SPI interface. The SCLK pin has an internal 18 k pull-down resistor. 25 SDTO Serial Data Output. The SDTO pin provides a SPI readback capability. See the timing diagrams for normal

    operation (see Figure 68 to Figure 70). The SDTO pin has an internal 18 k pull-down resistor. 26 SEN Serial Enable. When the SEN input pin goes high, the data stored in the shift registers is loaded into the

    register. The SEN pin has an internal 7.75 k pull-up resistor.

    http://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdf

  • ADRF6780 Data Sheet

    Rev. B | Page 8 of 35

    Pin No. Mnemonic Description 27, 31 VPLO Power Supply Connections for the LO Path. Decouple the VPLO pin with 100 pF and 0.1 F capacitors as close

    as possible to the pin. 28, 30 LOIN, LOIP LO Inputs. These inputs are 100 differential inputs for the LO path. The LO input frequency range is 5.4 GHz

    to 14 GHz. The on-chip LO frequency doubler can be enabled via a SPI command. 32 ALM Alarm. The ALM pin indicates internal alarm conditions. The ALM pin is logic low when an alarm condition is

    detected. EP Exposed Pad. Solder the exposed pad to a low impedance ground plane.

  • Data Sheet ADRF6780

    Rev. B | Page 9 of 35

    TYPICAL PERFORMANCE CHARACTERISTICS VPBB = VPBI = VPLO = 3.3 V, VP18 = 1.8 V, VPDT = VPRF = 5 V, TA = 25C, LO = 0 dBm differential drive, polyphase filter (PPF, 1) mode below 14 GHz and differential drive doubler (2) mode above 14 GHz, VATT = 2.6 V, unless otherwise noted. I/Q MODE Baseband (BB) I/Q amplitude = 15 dBm, differential sine waves in quadrature with a 500 mV dc bias, BB I/Q frequency (fx BB) = 10 MHz, BB input termination with 100 externally, unless otherwise noted.

    40

    35

    30

    25

    20

    15

    10

    5

    0

    5

    5 7 9 11 13 15 17 19 21 23 25

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    VATT = 2.6V

    VATT = 1.5V

    VATT = 0.4V

    40C+25C+85C

    1410

    6-00

    3

    Figure 3. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for Various Temperatures, BB I/Q Amplitude = 15 dBm

    40

    35

    30

    25

    20

    15

    10

    5

    0

    5

    5 7 9 11 13 15 17 19 21 23 25

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    VATT = 2.6V

    VATT = 1.5V

    VATT = 0.4V

    1410

    6-00

    4

    4.75V/3.15V5.00V/3.30V5.25V/3.45V

    Figure 4. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for Various Supply Voltages, BB I/Q Amplitude = 15 dBm

    40

    35

    30

    25

    20

    15

    10

    5

    0

    5

    5 7 9 11 13 15 17 19 21 23 25

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    VATT = 2.6V

    VATT = 1.5V

    VATT = 0.4V

    1410

    6-00

    5

    LO = +9dBmLO = +6dBmLO = +3dBmLO = 0dBm

    LO = 3dBmLO = 6dBmLO = 9dBm

    Figure 5. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for Various LO Inputs, BB I/Q Amplitude = 15 dBm

    15

    10

    5

    0

    5

    10

    15

    0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

    CO

    NVE

    RSI

    ON

    GA

    IN (d

    B)

    VATT (V)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-00

    6

    Figure 6. Conversion Gain vs. VATT for Various RF Frequencies (fRF)

    10

    5

    0

    5

    10

    15

    5 7 9 11 13 15 17 19 21 23 25

    P1dB

    (dB

    m)

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-00

    8

    Figure 7. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various Temperatures

    10

    5

    0

    5

    10

    15

    5 7 9 11 13 15 17 19 21 23 25

    P1dB

    (dB

    m)

    RF FREQUENCY (GHz)

    4.75V/3.15V5.00V/3.30V5.25V/3.45V

    1410

    6-00

    9

    Figure 8. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various Supply Voltages

  • ADRF6780 Data Sheet

    Rev. B | Page 10 of 35

    8

    6

    4

    2

    0

    2

    4

    6

    8

    10

    12

    5 7 9 11 13 15 17 19 21 23 25

    P1dB

    (dB

    m)

    RF FREQUENCY (GHz) 1410

    6-01

    0

    LO = +9dBmLO = +6dBmLO = +3dBmLO = 0dBm

    LO = 3dBmLO = 6dBmLO = 9dBm

    Figure 9. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various LO Inputs

    10

    5

    0

    5

    10

    15

    5 7 9 11 13 15 17 19 21 23 25

    P1dB

    (dB

    m)

    RF FREQUENCY (GHz) 1410

    6-01

    1

    MAXIMUM GAIN10dB GAIN

    Figure 10. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 10 dB Gain Setting and the Maximum Gain Setting

    10

    5

    0

    5

    10

    15

    0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

    P1dB

    (dB

    m)

    BB INPUT FREQUENCY (GHz) 1410

    6-21

    1

    Figure 11. Output 1 dB Compression Point (P1dB) vs. BB Input Frequency at a 10 dB Gain Setting

    80

    70

    60

    50

    40

    30

    20

    10

    0

    5 7 9 11 13 15 17 19 21 23 25

    CA

    RR

    IER

    FEE

    DTH

    RO

    UG

    H (d

    Bm

    )

    RF FREQUENCY (GHz) 1410

    6-01

    2

    +85C, VATT = 2.6V+85C, VATT = 1.5V+85C, VATT = 0.4V

    40C, VATT = 2.6V40C, VATT = 1.5V40C, VATT = 0.4V

    +25C, VATT = 2.6V+25C, VATT = 1.5V+25C, VATT = 0.4V

    Figure 12. Carrier Feedthrough vs. RF Frequency (fRF) at Three Gain Settings and Temperatures Before Nulling

    0

    10

    20

    30

    40

    50

    60

    5 7 9 11 13 15 17 19 21 23 25

    SID

    EBA

    ND

    SU

    PPR

    ESSI

    ON

    (dB

    )

    RF FREQUENCY (GHz) 1410

    6-01

    3

    +85C, VATT = 2.6V+85C, VATT = 1.5V+85C, VATT = 0.4V

    40C, VATT = 2.6V40C, VATT = 1.5V40C, VATT = 0.4V

    +25C, VATT = 2.6V+25C, VATT = 1.5V+25C, VATT = 0.4V

    Figure 13. Sideband Suppression vs. RF Frequency (fRF) at Three Gain Settings and Temperatures Before Nulling

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    SID

    EBA

    ND

    SU

    PPR

    ESSI

    ON

    (dB

    )

    RF FREQUENCY (GHz) 1410

    6-01

    4

    +85C, VATT = 2.6V+85C, VATT = 1.5V+85C, VATT = 0.4V

    40C, VATT = 2.6V40C, VATT = 1.5V40C, VATT = 0.4V

    +25C, VATT = 2.6V+25C, VATT = 1.5V+25C, VATT = 0.4V

    Figure 14. Sideband Suppression vs. RF Frequency (fRF) at Three Gain Settings and Temperatures after Nulling Using

    I_PATH_PHASE_ACCURACY and Q_PATH_PHASE_ACCURACY at 25C

  • Data Sheet ADRF6780

    Rev. B | Page 11 of 35

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bc)

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-01

    7

    Figure 15. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various Temperatures,

    BB I/Q Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 10 15 20 25

    IMD

    3 (d

    Bc)

    RF FREQUENCY (GHz)

    40C, RDAC_LINEARIZE+25C, RDAC_LINEARIZE+85C, RDAC_LINEARIZE40C+25C+85C

    1410

    6-21

    5

    Figure 16. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various RDAC_LINEARIZE Settings and Various Temperatures, BB I/Q Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bc)

    RF FREQUENCY (GHz)

    4.75V/3.15V5.00V/3.30V5.25V/3.45V

    1410

    6-11

    7

    Figure 17. Third-Order Intermodulation Distortion (IMD3) vs.

    RF Frequency (fRF) for Various Supply Voltages, BB I/Q Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bc)

    RF FREQUENCY (GHz) 1410

    6-01

    9

    LO = +9dBmLO = +6dBmLO = +3dBmLO = 0dBm

    LO = 3dBmLO = 6dBmLO = 9dBm

    Figure 18. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various LO Inputs,

    BB I/Q Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

    IMD

    3 (d

    Bm

    )

    BB INPUT FREQUENCY (GHz) 1410

    6-21

    9

    Figure 19. Third-Order Intermodulation Distortion (IMD3) vs. BB Input Frequency at a 10 dB Gain Setting, BB I/Q Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    30 25 20 15 10 5 0

    IMD

    3 (d

    Bc)

    POUT (dBm PER TONE; PIN = 15dBm PER TONE)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-02

    1

    Figure 20. Third-Order Intermodulation Distortion (IMD3) vs.

    Output Power (POUT) for Various RF Frequencies (fRF), BB I/Q Amplitude = 15 dBm per Tone

  • ADRF6780 Data Sheet

    Rev. B | Page 12 of 35

    0

    5

    10

    15

    20

    25

    30

    35

    40

    5 7 9 11 13 15 17 19 21 23 25

    OIP

    3 (d

    Bm

    )

    RF FREQUENCY (GHz) 1410

    6-02

    0Figure 21. Output Third-Order Intercept (OIP3) vs. RF Frequency (fRF) at a

    10 dB Gain Setting, BB I/Q Amplitude = 15 dBm per Tone

    0

    5

    10

    15

    20

    25

    30

    35

    40

    25 23 21 19 17 15 13 11 9 7 5

    OIP

    3 (d

    Bm

    )

    BB INPUT POWER (dBm PER TONE)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-22

    2

    Figure 22. Output Third-Order Intercept (OIP3) vs. BB Input Power at a 10 dB Gain Setting for Various RF Frequencies (fRF)

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    5 (d

    Bc)

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-02

    3

    Figure 23. Fifth-Order Intermodulation Distortion (IMD5) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various Temperatures,

    BB I/Q Amplitude = 15 dBm per Tone

    POUT (dBm PER TONE; PIN = 15dBm PER TONE)

    0

    10

    20

    30

    40

    50

    60

    70

    80

    30 25 20 15 10 5 0

    IMD

    5 (d

    Bc)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-02

    4

    Figure 24. Fifth-Order Intermodulation Distortion (IMD5) vs. Output Power (POUT) for Various RF Frequencies,

    BB I/Q Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    OIP

    2 (d

    Bm

    )

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-02

    5

    Figure 25. Output Second-Order Intercept (OIP2) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various Temperatures,

    BB I/Q Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    OIP

    2 (d

    Bm

    )

    RF FREQUENCY (GHz) 1410

    6-02

    6

    LO = +9dBmLO = +6dBmLO = +3dBmLO = 0dBm

    LO = 3dBmLO = 6dBmLO = 9dBm

    Figure 26. Output Second-Order Intercept (OIP2) vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various LO Inputs,

    BB I/Q Amplitude = 15 dBm per Tone

  • Data Sheet ADRF6780

    Rev. B | Page 13 of 35

    0

    10

    20

    30

    40

    50

    60

    70

    80

    30 25 20 15 10 5 0

    OIP

    2 (d

    Bm

    )

    POUT (dBm PER TONE; PIN = 15dBm PER TONE)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-22

    7

    Figure 27. Output Second-Order Intercept (OIP2) vs. Output Power (POUT)

    for Various RF Frequencies (fRF), BB I/Q Amplitude = 15 dBm per Tone

    125

    130

    135

    140

    145

    150

    155

    5 7 9 11 13 15 17 19 21 23 25

    CA

    RR

    IER

    TO N

    OIS

    E (d

    Bc/

    Hz)

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-12

    7

    Figure 28. Output Noise Density vs. RF Frequency (fRF) at a 10 dB Gain Setting for Various Temperatures with an Output Carrier of 5 dBm

    125

    130

    135

    140

    145

    150

    155

    11 6 1 4 9 14

    CA

    RR

    IER

    TO N

    OIS

    E (d

    Bc/

    Hz)

    VATT GAIN (dB)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-02

    8

    Figure 29. Output Noise Density vs. VATT Gain for Various RF Frequencies

    (fRF) with an Input Carrier of 15 dBm

    20

    15

    10

    5

    0

    5

    0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

    P OU

    TAT

    15G

    Hz,

    MA

    X G

    AIN

    (dB

    m)

    BB FREQUENCY (GHz) 1410

    6-23

    0

    Figure 30. Bandwidth, POUT at 15 GHz and the Maximum Gain Setting vs. BB Input Frequency

    10

    8

    6

    4

    2

    0

    2

    4

    6

    8

    10

    5 7 9 11 13 15 17 19 21 23 25

    RF FREQUENCY (GHz)

    MA

    GN

    ITU

    DE

    DEL

    TA, R

    FON

    TO R

    FOP

    (dB

    )

    VATT = 2.6VVATT = 1.5VVATT = 0.4V

    1410

    6-03

    1

    Figure 31. Magnitude Delta, RFON minus RFOP vs. RF Frequency (fRF) at

    Three Different Gain Settings

  • ADRF6780 Data Sheet

    Rev. B | Page 14 of 35

    IF MODE IF frequency (IF mode) = 1900 MHz, IF amplitude = 12 dBm, input ac-coupled, unless otherwise noted.

    40

    35

    30

    25

    20

    15

    10

    5

    0

    5

    5 7 9 11 13 15 17 19 21 23 25

    P OUT

    (dB

    m)

    RF FREQUENCY (GHz)

    40C+25C+85C

    VATT = 2.6V

    VATT = 1.5V

    VATT = 0.4V

    1410

    6-03

    7

    Figure 32. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for Various Temperatures, IF Amplitude = 12 dBm

    40

    35

    30

    25

    20

    15

    10

    5

    0

    5

    5 7 9 11 13 15 17 19 21 23 25

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    VATT = 2.6V

    VATT = 1.5V

    VATT = 0.4V

    4.75/3.155.00/3.305.25/3.45

    1410

    6-03

    8

    Figure 33. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for Various Supply Voltages, IF Amplitude = 12 dBm

    40

    35

    30

    25

    20

    15

    10

    5

    0

    5

    5 7 9 11 13 15 17 19 21 23 25

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    VATT = 2.6V

    VATT = 1.5V

    VATT = 0.4V

    1410

    6-03

    9

    LO = +9dBmLO = +6dBmLO = +3dBmLO = 0dBm

    LO = 3dBmLO = 6dBmLO = 9dBm

    Figure 34. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for Various LO Inputs, IF Amplitude = 12 dBm

    15

    10

    5

    0

    5

    10

    15

    0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

    CO

    NVE

    RSI

    ON

    GA

    IN (d

    B)

    VATT (V)

    1410

    6-04

    0

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    Figure 35. Conversion Gain vs. VATT at Various RF Frequencies (fRF)

    1410

    6-03

    510

    5

    0

    5

    10

    15

    5 7 9 11 13 15 17 19 21 23 25

    P1dB

    (dB

    m)

    RF FREQUENCY (GHz)

    40C+25C+85C

    Figure 36. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 7 dB Gain Setting for Various Temperatures

    10

    5

    0

    5

    10

    15

    5 7 9 11 13 15 17 19 21 23 25

    P1dB

    (dB

    m)

    RF FREQUENCY (GHz)

    4.75V/3.15V5.00V/3.30V5.25V/3.45V

    1410

    6-13

    7

    Figure 37. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 7 dB Gain Setting for Various Supply Voltages

  • Data Sheet ADRF6780

    Rev. B | Page 15 of 35

    15

    10

    5

    0

    5

    10

    15

    5 7 9 11 13 15 17 19 21 23 25

    P1dB

    (dB

    m)

    RF FREQUENCY (GHz) 1410

    6-13

    8

    LO = +9dBmLO = +6dBmLO = +3dBmLO = 0dBm

    LO = 3dBmLO = 6dBmLO = 9dBm

    Figure 38. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 7 dB Gain Setting for Various LO Inputs

    10

    5

    0

    5

    10

    15

    5 7 9 11 13 15 17 19 21 23 25

    P1dB

    (dB

    m)

    RF FREQUENCY (GHz)

    MAXIMUM GAIN7dB GAIN

    1410

    6-13

    9

    Figure 39. 1 dB Output Compression Point (P1dB) vs. RF Frequency (fRF) at a 7 dB Gain Setting and the Maximum Gain Setting

    10

    5

    0

    5

    10

    15

    0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

    P1dB

    AT 1

    5GH

    z (d

    Bm

    )

    IF FREQUENCY (GHz) 1410

    6-24

    0

    Figure 40. Output 1 dB Compression Point (P1dB) at 15 GHz vs. IF Frequency at a 7 dB Gain Setting

    80

    70

    60

    50

    40

    30

    20

    10

    0

    5 7 9 11 13 15 17 19 21 23 25

    CA

    RR

    IER

    FEE

    DTH

    RO

    UG

    H (d

    Bm

    )

    RF FREQUENCY (GHz) 1410

    6-04

    7

    +85C, VATT = 2.6V+85C, VATT = 1.5V+85C, VATT = 0.4V

    40C, VATT = 2.6V40C, VATT = 1.5V40C, VATT = 0.4V

    +25C, VATT = 2.6V+25C, VATT = 1.5V+25C, VATT = 0.4V

    Figure 41. Carrier Feedthrough vs. RF Frequency (fRF) at Three Gain Settings for Various Temperatures Before Nulling

    0

    5

    10

    15

    20

    25

    30

    35

    40

    5 7 9 11 13 15 17 19 21 23 25

    SID

    EBA

    ND

    SU

    PPR

    ESSI

    ON

    (dB

    )

    RF FREQUENCY (GHz) 1410

    6-04

    8

    +85C, VATT = 2.6V+85C, VATT = 1.5V+85C, VATT = 0.4V

    40C, VATT = 2.6V40C, VATT = 1.5V40C, VATT = 0.4V

    +25C, VATT = 2.6V+25C, VATT = 1.5V+25C, VATT = 0.4V

    Figure 42. Sideband Suppression vs. RF Frequency (fRF) at Three Different Gain Settings for Various Temperatures Before Nulling

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bc)

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-05

    0

    Figure 43. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at a 7 dB Gain Setting for Various Temperatures,

    IF Amplitude = 15 dBm per Tone

  • ADRF6780 Data Sheet

    Rev. B | Page 16 of 35

    0

    10

    20

    30

    40

    50

    60

    70

    80

    90

    100

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bc)

    RF FREQUENCY (GHz)

    40C, RDAC_LINEARIZE+25C, RDAC_LINEARIZE+85C, RDAC_LINEARIZE40C+25C+85C

    1410

    6-24

    3

    Figure 44. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at 7 dB Gain Setting for Various RDAC_LINEARIZE Settings and Various

    Temperatures, IF Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bc)

    RF FREQUENCY (GHz)

    4.45V5.00V5.25V

    1410

    6-05

    1

    Figure 45. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF)

    at a 7 dB Gain Setting and for Various Supply Voltages, IF Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bm

    )

    RF FREQUENCY (GHz) 1410

    6-05

    2

    LO = +9dBmLO = +6dBmLO = +3dBmLO = 0dBm

    LO = 3dBmLO = 6dBmLO = 9dBm

    Figure 46. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at a 7 dB Gain Setting for Various LO Inputs, IF Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

    IMD

    3AT

    15G

    Hz

    (dB

    c)

    IF FREQUENCY (GHz) 1410

    6-14

    7

    Figure 47. Third-Order Intermodulation Distortion (IMD3) at 15 GHz vs.

    IF Frequency at a 7 dB Gain Setting

    0

    10

    20

    30

    40

    50

    60

    70

    80

    30 25 20 15 10 5 0

    IMD

    3 (d

    Bc)

    POUT (dBm PER TONE; PIN = 15dBm PER TONE)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-05

    3

    Figure 48. Third-Order Intermodulation Distortion (IMD3) vs. Output Power

    (POUT) for Various RF Frequencies (fRF), IF Amplitude = 15 dBm per Tone

    0

    5

    10

    15

    20

    25

    30

    35

    40

    5 7 9 11 13 15 17 19 21 23 25

    OIP

    3 (d

    Bm

    )

    RF FREQUENCY (GHz) 1410

    6-14

    8

    Figure 49. Output Third-Order Intercept (OIP3) vs. RF Frequency (fRF) at a

    7 dB Gain Setting, IF Amplitude = 15 dBm per Tone

  • Data Sheet ADRF6780

    Rev. B | Page 17 of 35

    0

    5

    10

    15

    20

    25

    30

    35

    40

    25 23 21 19 17 15 13 11 9 7 5

    OIP

    3 (d

    Bm

    )

    IF INPUT POWER (dBm PER TONE)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-25

    0

    Figure 50. Output Third-Order Intercept (OIP3) vs. IF Input Power at a

    7 dB Gain Setting for Various RF Frequencies (fRF)

    0

    10

    20

    30

    40

    50

    60

    70

    80

    90

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    5 (d

    Bc)

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-05

    5

    Figure 51. Fifth-Order Intermodulation Distortion (IMD5) vs. RF Frequency (fRF)

    at a 7 dB Gain Setting for Various Temperatures, IF Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    90

    30 25 20 15 10 5 0

    IMD

    5 (d

    Bc)

    POUT (dBm PER TONE; PIN = 15dBm PER TONE)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-05

    6

    Figure 52. Fifth-Order Intermodulation Distortion (IMD5) vs. Output Power

    (POUT) for Various RF Frequencies (fRF), IF Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    OIP

    2 (d

    Bm

    )

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-05

    7

    Figure 53. Output Second-Order Intercept (OIP2) vs. RF Frequency (fRF) at a 7 dB Gain Setting for Various Temperatures, IF Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    OIP

    2 (d

    Bm

    )

    RF FREQUENCY (GHz) 1410

    6-05

    8

    LO = +9dBmLO = +6dBmLO = +3dBmLO = 0dBm

    LO = 3dBmLO = 6dBmLO = 9dBm

    Figure 54. Output Second-Order Intercept (OIP2) vs. RF Frequency (fRF) at a 7 dB Gain Setting for Various LO Inputs, IF Amplitude = 15 dBm per Tone

    0

    10

    20

    30

    40

    50

    60

    70

    80

    30 25 20 15 10 5 0

    OIP

    2 (d

    Bm

    )

    POUT (dBm PER TONE; PIN = 15dBm PER TONE)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-05

    9

    Figure 55. Output Second-Order Intercept (OIP2) vs. Output Power (POUT)

    for Various RF Frequencies (fRF), IF Amplitude = 15 dBm per Tone

  • ADRF6780 Data Sheet

    Rev. B | Page 18 of 35

    125

    130

    135

    140

    145

    150

    155

    5 7 9 11 13 15 17 19 21 23 25

    CA

    RR

    IER

    TO N

    OIS

    E (d

    Bc/

    Hz)

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-15

    5

    Figure 56. Output Noise Density vs. RF Frequency (fRF) at a 7 dB Gain Setting for Various Temperatures with an Output Carrier of 5 dBm

    125

    130

    135

    140

    145

    150

    155

    13 8 3 2 7 12

    CA

    RR

    IER

    TO N

    OIS

    E (d

    Bc/

    Hz)

    VATT GAIN (dB)

    fRF = 6GHzfRF = 10GHzfRF = 15GHzfRF = 20GHzfRF = 24GHz

    1410

    6-15

    6

    Figure 57. Output Noise Density vs. VATT Gain for Various RF Frequencies

    (fRF) with an Input Carrier of 12 dBm

    20

    15

    10

    5

    0

    5

    0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

    P OU

    TAT

    15G

    Hz,

    MA

    X G

    AIN

    (dB

    m)

    IF FREQUENCY (GHz) 1410

    6-15

    8

    Figure 58. Bandwidth, POUT at 15 GHz and Maximum Gain Setting vs.

    IF Frequency (fIF)

    10

    8

    6

    4

    2

    0

    2

    4

    6

    8

    10

    5 7 9 11 13 15 17 19 21 23 25

    MA

    GN

    ITU

    DE

    DEL

    TA, R

    FON

    TO R

    FOP

    (dB

    )

    RF FREQUENCY (GHz)

    VATT = 2.6VVATT = 1.5VVATT = 0.4V

    1410

    6-15

    9

    Figure 59. Magnitude Delta, RFON to RFOP vs. RF Frequency (fRF) at

    Three Different Gain Settings

  • Data Sheet ADRF6780

    Rev. B | Page 19 of 35

    OUTPUT DETECTOR PERFORMANCE

    0

    0.2

    0.4

    0.6

    0.8

    1.0

    1.2

    1.4

    35 30 25 20 15 10 5 0 5 10

    VDET

    (V)

    POUT AT 15GHz (dBm)

    40C+25C+85C

    1410

    6-06

    0

    Figure 60. Detector Output (VDET) vs. Output Power (POUT) at 15 GHz for Various Temperatures

    5

    4

    3

    2

    1

    0

    1

    2

    3

    4

    5

    35 30 25 20 15 10 5 0 5 10

    DET

    ECTO

    R E

    RR

    OR

    (dB

    )

    POUT AT 15GHz (dBm)

    40C+25C+85C

    1410

    6-06

    1

    Figure 61. Detector Error vs. Output Power (POUT) at 15 GHz for

    Various Temperatures

    0

    0.2

    0.4

    0.6

    0.8

    1.0

    1.2

    1.4

    5 7 9 11 13 15 17 19 21 23 25

    VDET

    (V)

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-06

    2

    Figure 62. Detector Output (VDET) vs. RF Frequency (fRF), 5 dBm Output Power (POUT) for Various Temperatures

  • ADRF6780 Data Sheet

    Rev. B | Page 20 of 35

    RETURN LOSS

    25

    20

    15

    10

    5

    0

    5 7 9 11 13 15 17 19 21 23 25

    RET

    UR

    N L

    OSS

    (dB

    )

    RF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-26

    3

    Figure 63. RF Output Return Loss S11 vs. RF Frequency for Various Temperatures

    25

    20

    15

    10

    5

    0

    5 7 9 11 13 15 17 19 21 23 25

    RET

    UR

    N L

    OSS

    (dB

    )

    LO FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-26

    4

    Figure 64. LO Input Return Loss S11 vs. LO Frequency for Various

    Temperatures

    25

    20

    15

    10

    5

    0

    0 1 2 3 4 5 6

    RET

    UR

    N L

    OSS

    (dB

    )

    IQ FREQUENCY (GHz)

    40C, BASEBAND I PORT+25C, BASEBAND I PORT+85C, BASEBAND I PORT40C, BASEBAND Q PORT+25C, BASEBAND Q PORT+85C, BASEBAND Q PORT

    1410

    6-26

    5

    Figure 65. I/Q Input Return Loss S11 vs. I/Q Frequency for Various

    Temperatures

    30

    25

    20

    15

    10

    5

    0

    0 1 2 3 4 5 6

    RET

    UR

    N L

    OSS

    (dB

    )

    IF FREQUENCY (GHz)

    40C+25C+85C

    1410

    6-26

    6

    Figure 66. IF Input Return Loss S11 vs. IF Frequency for Various

    Temperatures

  • Data Sheet ADRF6780

    Rev. B | Page 21 of 35

    THEORY OF OPERATION The ADRF6780 is a wideband microwave upconverter optimized for point to point microwave radio designs operating in the 5.9 GHz to 23.6 GHz frequency range. A functional block diagram of the device is shown in Figure 1. The ADRF6780 is programmed via an SPI.

    BASEBAND The input impedance of the basebands are high input impedance. These inputs are designed to operate with a 0.5 V common-mode voltage. These inputs are differentially terminated to a 100 resistor using an off chip termination.

    The linearity can be optimized by adding phase correction signals to the current output via adjusting the I_PATH_PHASE_ ACCURACY register (Register 0x05, Bits[3:0]) and the Q_PATH_ PHASE_ACCURACY (Register 0x05, Bits[7:4]) register.

    SINGLE SIDEBAND (SSB) UPCONVERSION The IF input path can be fed anywhere from 0.8 GHz to 3.5 GHz. The IF inputs path can be upconverted to 5.9 GHz to 23.6 GHz, while suppressing the unwanted sideband by typically better than 25 dBc. The IF upconversion inputs are 100 differential and must be ac-coupled. In addition, the I/Q baseband input must stay floating without any termination on their inputs.

    LO INPUT PATH The LO input path operates from 5.4 GHz to 14 GHz with a LO amplitude range of 6 dBm to +6 dBm. It is built from two modes: 1 mode (Register 0x03, Bit 2), which provides an LO output frequency equal to the LO input frequency, and 2 mode (Register 0x03, Bit 3), which doubles the LO output frequency from the LO input frequency. Note that, when enabling the LO 2 mode (Register 0x03, Bit 3), the LO 1 mode (Register 0x03, Bit 2) must be disabled.

    The LO path is designed to operate differentially. LOIP and LOIN are the inputs to the LO path. It is recommended to use the ADRF6780 with a LO differential input to achieve the best performance.

    Figure 67 shows a block diagram of the LO path.

    2 PPF

    MUX

    PPF

    AMP1LOIPLOIN

    1410

    6-07

    8

    Figure 67. LO Path Block Diagram

    SERIAL PORT INTERFACE (SPI) The SPI of the ADRF6780 allows the user to configure the device for specific functions or operations via a 4-pin SPI port. This interface provides users with added flexibility and customization. The SPI consists of four control lines: SCLK, SDIN, SDTO, and SEN.

    The ADRF6780 protocol consists of a write/read bit followed by six register address bits, 16 data bits, and a parity bit. Both the address and data fields are organized MSB first and end with the least significant bit (LSB). For a write, set the first bit to 0, and for a read, set this bit to 1.

    The write cycle sampling must be done on the rising edge. The 16 bits of the serial write data are shifted in, MSB to LSB. The ADRF6780 input logic level for the write cycle supports an 1.8 V interface.

    For a read cycle, up to 16 bits of serial read data are shifted out, MSB first. After the 16 bits of data shift out, the parity bit shifts out. The output logic level for a read cycle is 1.8 V.

    The parity bit always follows the direction of the data. If parity is not used, the transmitting end transmits zero instead of parity. The parity is odd, which means that the total number of ones transmitted during a command, including the read/write bit, the address bit, the data bit, and the parity bit, must be odd.

    Table 5. Serial Port Register Timing Parameter Description Min Typ Max Unit tDI, SETUP Data to clock setup time 10 ns tDI, HOLD Data to clock hold time 10 ns tCLK, HIGH Clock high duration 40 to 60 % tCLK, LOW Clock low duration 40 to 60 % tCLK, SEN_SETUP Clock to SEN setup time 30 ns

    tCLK, DOT Clock to data out transition time 10 ns tCLK, DOV Clock to data out valid time 10 ns tCLK, SEN_INACTIVE Clock to SEN inactive 20 ns

    tSEN_INACTIVE Inactive SEN (between two operations) 80 ns

    http://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdf

  • ADRF6780 Data Sheet

    Rev. B | Page 22 of 35

    tCLK, LOW

    tCLK, DOT

    SDINtCLK, DOV

    SDTOtDI, SETUP

    tDI, HOLD

    SCLK

    tSEN_INACTIVE

    tCLK, HIGH

    tCLK, SEN_INACTIVE

    tCLK, SEN_SETUP

    SEN

    1410

    6-07

    9

    Figure 68. Serial Port Register Timing Diagram

    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

    SCLK

    SDIN D11R/W A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 PD10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

    SEN

    1410

    6-08

    0

    Figure 69. Write Serial Port Timing Diagram

    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

    SCLK

    SDIN

    SDTO D0 PD5 D4 D3 D2 D1D10 D9 D8 D7 D6D15 D14 D13 D12 D11

    A1 A0R/W A5 A4 A3 A2

    1410

    6-08

    1

    SEN

    Figure 70. Read Serial Port Timing Diagram

  • Data Sheet ADRF6780

    Rev. B | Page 23 of 35

    APPLICATIONS INFORMATION CARRIER FEEDTHROUGH NULLING Carrier feedthrough results from minute dc offsets that occur on the differential baseband inputs. In an I/Q modulator, nonzero differential offsets mix with the LO and result in carrier feedthrough to the RF output. In addition to this effect, some of the signal power at the LO input couples directly to the RF output (this may be because of the bond wire to bond wire coupling or coupling through the silicon substrate). The net carrier feedthrough at the RF output is the vector combination of the signals that appear at the output because of these two effects. A TxDAC can externally accomplish carrier feedthrough nulling.

    SIDEBAND SUPPRESSION OPTIMIZATION Sideband results from gain and phase imperfections between the I and Q channels. Sideband also results from the quadrature error in generating the quadrature LO signals. Quadrature I and Q signals are constructed in the LO path, and the vector combination of these signals at the RF output results in suppression of the unwanted sideband. Deviation from perfect quadrature on these signals limits the amount of achievable sideband suppression.

    The ADRF6780 offers quadrature phase adjustment in the LO path quadrature signals. Make these adjustments through the I_PATH_PHASE_ACCURACY bits (Register 0x05, Bits[3:0]) and Q_PATH_PHASE_ACCURACY (Register 0x05, Bits[7:4]) bits to reject the unwanted sideband signal.

    Figure 14 shows the level of unwanted sideband signal achievable from the ADRF6780 across the I_PATH_PHASE_ACCURACY bits (Register 0x05, Bits[3:0]) and Q_PATH_PHASE_ACCURACY (Register 0x05, Bits[7:4]) bits.

    If further optimization is needed, adjust the amplitude and phase externally through a TxDAC.

    LINEARITY The linearity in the ADRF6780 can be optimized through the distortion cancellation circuit that is set up by the RDAC_ LINEARIZE bits (Register 0x04, Bits[7:0]) SPI settings. The distortion cancellation circuit connects in parallel with the baseband signal path in such a way that the fundamental is minimally affected whereas the third-order portions cancel to some degree. Adjusting the value of the RDAC_LINEARIZE bits (Register 0x04, Bits[7:0]) changes the resistance value in the cancellation path by fine tuning the amount of third-order destructively added to the main signal path. It also serves as a form or predistortion for third-order impedance generated further down in the signal path.

    Figure 16 and Figure 44 show the level of linearity improvement achievable across the ADRF6780 RDAC_LINEARIZE bits.

    ADC The ADRF6780 includes an ADC that connects to a detector. The user has an option to read the detector output from the

    detector output pin (VDET, Pin 1) or using the ADC from the SPI. Figure 71 shows normal operation at I/Q mode, an RF output of 6.7 GHz, an I/Q input of 1 MHz, and a maximum gain. Figure 72 shows normal operation at IF mode and an RF output of 6.7 GHz, an IF input of 800 MHz, and a maximum gain.

    0.05

    0.25

    0.45

    0.65

    0.85

    1.05

    1.25

    0

    50

    100

    150

    200

    250

    300

    DET

    ECTO

    R V

    OLT

    AG

    E (V

    )

    AD

    CVA

    LUE

    RF OUTPUT POWER (dBm)

    ADC VALUEDETECTOR VOLTAGE(V)

    35 31 27 23 19 15 11 7 3 1

    1410

    6-08

    9

    Figure 71. ADC Detector Output and Detector Output Power, I/Q Mode

    0.05

    0.25

    0.45

    0.65

    0.85

    1.05

    1.25

    0

    50

    100

    150

    200

    250

    300

    35 31 27 23 19 15 11 7 3 1

    DET

    ECTO

    R V

    OLT

    AG

    E (V

    )

    AD

    CVA

    LUE

    RF OUTPUT POWER (dBm)

    ADC VALUEDETECTOR VOLTAGE (V)

    1410

    6-09

    0

    Figure 72. ADC Detector Output and Detector Output Power, IF Mode

    To read back from the detector using the ADC, take the following steps.

    1. Set Bit 7 of Register 0x03 to 1 (DETECTOR_ENABLE). 2. Set Bit 1 of Register 0x06 to 1 (ADC_ENABLE). 3. Set Bit 0 of Register 0x06 to 1 (ADC_CLOCK_ENABLE). 4. Set Bit 2 of Register 0x06 to 1 (ADC_START). 5. Wait 200 s for the ADC to be ready. 6. Set Bit 8 of Register 0x0C to 1 (ADC_STATUS). 7. Set Bit 2 of Register 0x06 to 0 (ADC_START). 8. Set Bits[7:0] of Register 0x0C to read back the ADC

    value (ADC_VALUE). To read the ADC value, the ADC_CLOCK_ENABLE, ADC_ENABLE, and ADC_START bits must be enabled.

    To disable the ADC, disable the ADC_CLOCK_ENABLE, ADC_ENABLE, and ADC_START bits.

    http://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdf

  • ADRF6780 Data Sheet

    Rev. B | Page 24 of 35

    WIDE FREQUENCY PERFORMANCE Figure 73 and Figure 74 show the typical performance of the ADRF6780 when using values outside of the RF output frequency range. It is important to understand that this performance is typical and not guaranteed.

    Figure 73 was tested in I/Q mode with an RF output frequency of 1 GHz to 31 GHz. The LO input frequency was switched to LO 2 doubler mode above 14 GHz.

    Figure 74 was tested in IF mode with an RF output frequency of 1 GHz to 31 GHz. The LO input frequency was switched to LO 2 doubler mode above 14 GHz.

    65

    55

    45

    35

    25

    15

    5

    5

    1 6 11 16 21 26 31

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    MAIN TONESIDEBANDLO FEEDTHROUGH

    1410

    6-07

    3

    Figure 73. Output Power (POUT) vs. RF Frequency (fRF) in I/Q Mode at

    the Maximum Gain Setting, BB I/Q Amplitude = 15 dBm

    65

    55

    45

    35

    25

    15

    5

    5

    1 6 11 16 21 26 31

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    MAIN TONESIDEBANDLO FEEDTHROUGH

    1410

    6-07

    4

    Figure 74. Output Power (POUT) vs. RF Frequency (fRF) in IF Mode at

    the Maximum Gain Setting, IF Amplitude = 12 dBm

    LO Path 1, 2 Full Range

    Figure 75 shows the typical performance of the ADRF6780 when the LO input frequency is used within the full frequency range. It is important to understand that this performance is typical and not guaranteed.

    Figure 75 was tested with the LO path set to 1 mode and 2 mode with a 5.9 GHz to 23.6 GHz frequency range in I/Q mode. It is recommended to switch to LO 2 doubler mode above 14 GHz to achieve better performance out of the device.

    65

    55

    45

    35

    25

    15

    5

    5

    5 7 9 11 13 15 17 19 21 23 25

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    MAIN TONE (LO 1)MAIN TONE (LO 2)SIDEBAND (LO 1)SIDEBAND (LO 2)

    LO FEEDTHROUGH (LO 1)LO FEEDTHROUGH (LO 2)

    1410

    6-07

    5

    Figure 75. LO 1 Mode and LO 2 Mode, Output Power (POUT) vs.

    RF Frequency (fRF) in I/Q Mode at the Maximum Gain Setting, BB I/Q Amplitude = 15 dBm

    LAYOUT Solder the exposed pad on the underside of the ADRF6780 to a low thermal and electrical impedance ground plane. This pad is typically soldered to an exposed opening in the solder mask on the evaluation board. Connect these ground vias to all other ground layers on the evaluation board to maximize heat dissipation from the device package.

    1410

    6-09

    3

    Figure 76. Evaluation Board Layout for the ADRF6780 Package

    http://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdf

  • Data Sheet ADRF6780

    Rev. B | Page 25 of 35

    LO INPUT DRIVEN DIFFERENTIAL vs. SINGLE ENDED This section provides performance measurements that compare the ADRF6780 using a differential LO input vs. a single-ended LO input. When the device uses a single-ended configuration, LOIP drives while LOIN terminates to 50 .

    The subharmonic measurement compares the two settings. The LO input was set to doubler mode (2) at a LO frequency of 9 GHz, and the I/Q mode was set with a 10 MHz sine wave. Table 6 represents the output frequencies of the upper sideband, the lower sideband, and the LO leakage at the fundamental output as well as the subharmonic output frequency at a maximum gain.

    Table 6. LO Single-Ended vs. Differential Configuration Performance

    Mode LO Input Power (dBm)

    Fundamental Output Subharmonic Output Wanted Upper Sideband, LO I/Q (dBm)

    Unwanted Lower Sideband, LO + I/Q (dBm)

    LO Leakage (dBm)

    Unwanted Upper Sideband, LO/2 I/Q (dBm)

    Unwanted Lower Sideband, LO/2 + I/Q (dBm)

    LO/2 Leakage (dBm)

    Single Ended 10 2.20 28.83 32.36 16.26 32.85 36.16 6 2.09 25.15 33.22 18.01 35.78 35.46 0 1.94 28.36 38.08 22.83 42.97 41.50 +6 2.01 28.36 42.58 20.17 39.80 38.08 Differential 10 1.84 24.96 43.49 29.66 51.54 45.85 6 1.85 27.19 38.86 33.18 51.25 47.12 0 1.84 29.46 37.84 38.04 56.50 58.25 +6 1.85 29.55 37.70 40.08 58.46 60.16

    http://www.analog.com/ADRF6780?doc=ADRF6780.pdf

  • ADRF6780 Data Sheet

    Rev. B | Page 26 of 35

    Gain, third-order intermodulation distortion (IMD3), and sideband rejection are also measured. RF frequencies from 5 GHz to 13 GHz are produced in LO 1 mode, while LO 2 mode produced RF frequencies from 14 GHz to 25 GHz. In both differential (Figure 77 to Figure 79) and single-ended (Figure 80 to Figure 82) configurations, the total LO power was swept from 10 dBm to +6 dBm. In differential mode, the amplitude was the sum of the LOIP and LOIN inputs.

    40

    35

    30

    25

    20

    15

    10

    5

    0

    5 7 9 11 13 15 17 19 21 23 25

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    LO = 10dBmLO = 6dBmLO = 0dBmLO = +6dBm

    VATT = 2.6V

    VATT = 1.5V

    VATT = 0.4V

    1410

    6-09

    3

    Figure 77. LO Differential Input, Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for Various LO Inputs,

    BB I/Q Amplitude = 15 dBm

    RF FREQUENCY (GHz)

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bc)

    1410

    6-09

    4

    LO = 10dBmLO = 6dBmLO = 0dBmLO = +6dBm

    Figure 78. LO Differential Input, Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at a 10 dB Gain Setting (POUT 5 dBm per Tone)

    0

    10

    20

    30

    40

    50

    60

    5 7 9 11 13 15 17 19 21 23 25

    SID

    EBA

    ND

    SU

    PPR

    ESSI

    ON

    (dB

    c)

    RF FREQUENCY (GHz) 1410

    6-09

    5

    LO = 10dBmLO = 6dBmLO = 0dBmLO = +6dBm

    Figure 79. LO Differential Input, Sideband Suppression vs. RF Frequency (fRF) Before Nulling

    40

    35

    30

    25

    20

    15

    10

    5

    0

    5 7 9 11 13 15 17 19 21 23 25

    P OU

    T (d

    Bm

    )

    RF FREQUENCY (GHz)

    VATT = 2.6V

    VATT = 1.5V

    VATT = 0.4V

    1410

    6-09

    6

    LO = 10dBmLO = 6dBmLO = 0dBmLO = +6dBm

    Figure 80. LO Single-Ended Input, Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for Various LO Inputs,

    BB I/Q Amplitude = 15 dBm

    RF FREQUENCY (GHz)

    0

    10

    20

    30

    40

    50

    60

    70

    80

    5 7 9 11 13 15 17 19 21 23 25

    IMD

    3 (d

    Bc)

    1410

    6-09

    8

    LO = 10dBmLO = 6dBmLO = 0dBmLO = +6dBm

    Figure 81. LO Single-Ended Input, Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at a 10 dB Gain Setting (POUT 5 dBm per Tone)

    0

    10

    20

    30

    40

    50

    60

    5 7 9 11 13 15 17 19 21 23 25

    SID

    EBA

    ND

    SU

    PPR

    ESSI

    ON

    (dB

    c)

    RF FREQUENCY (GHz) 1410

    6-09

    7

    LO = 10dBmLO = 6dBmLO = 0dBmLO = +6dBm

    Figure 82. LO Single-Ended Input, Sideband Suppression vs. RF Frequency (fRF) Before Nulling

  • Data Sheet ADRF6780

    Rev. B | Page 27 of 35

    REGISTER SUMMARY Table 7. Register Summary

    Hex Addr Name Bits

    Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

    Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W

    0x00 Control [15:8] PARITY_EN SOFT_RESET RESERVED CHIP_ID[7:4] 0x0075 R/W

    [7:0] CHIP_ID[3:0] CHIP_REVISION

    0x01 ALARM_ READBACK

    [15:8] PARITY_ ERROR

    TOO_FEW_ ERRORS

    TOO_MANY_ ERRORS

    ADDRESS_ RANGE_ ERROR

    RESERVED 0x0000 R

    [7:0] RESERVED

    0x02 ALARM_MASK [15:8] PARITY_ ERROR_ MASK

    TOO_FEW_ ERRORS_ MASK

    TOO_MANY_ ERRORS_ MASK

    ADDRESS_ RANGE_ ERROR_MASK

    RESERVED 0xFFFF R/W

    [7:0] RESERVED

    0x03 Enable [15:8] RESERVED VGA_BUFFER_ ENABLE

    0x0157 R/W

    [7:0] DETECTOR_ ENABLE

    LO_BUFFER_ ENABLE

    IF_MODE_ ENABLE

    IQ_MODE_ ENABLE

    LO_X2_ ENABLE

    LO_PPF_ ENABLE

    LO_ ENABLE

    UC_BIAS_ ENABLE

    0x04 Linearize [15:8] RESERVED 0x0080 R/W

    [7:0] RDAC_LINEARIZE

    0x05 LO_PATH [15:8] RESERVED LO_ SIDEBAND

    RESERVED 0x0000 R/W

    [7:0] Q_PATH_PHASE_ACCURACY I_PATH_PHASE_ACCURACY

    0x06 ADC_ CONTROL

    [15:8] RESERVED 0x0000 R/W

    [7:0] RESERVED VDET_ OUTPUT_ SELECT

    ADC_ START

    ADC_ ENABLE

    ADC_CLOCK_ ENABLE

    0x0C ADC_OUTPUT [15:8] RESERVED ADC_STATUS 0x0010 R

    [7:0] ADC_VALUE

  • ADRF6780 Data Sheet

    Rev. B | Page 28 of 35

    REGISTER DETAILS: WIDEBAND UPCONVERTER CONTROL REGISTER Address: 0x00, Reset: 0x0075, Name: Control

    Enable the Parity for Write Execution Chip Revis ion

    SPI Soft Reset (SPI Soft Reset isNot Self-Reset)

    Chip ID

    0

    11

    02

    13

    04

    15

    16

    17

    08

    09

    010

    011

    012

    013

    014

    015

    0

    [15] PARITY_EN (R/W) [3:0] CHIP_REVISION (R)

    [14] SOFT_RESET (W) [11:4] CHIP_ID (R)

    [13:12] RESERVED

    Table 8. Bit Descriptions for Control Bits Bit Name Settings Description Reset Access 15 PARITY_EN Enable the Parity for Write Execution 0x0 R/W 14 SOFT_RESET SPI Soft Reset (SPI Soft Reset is Not Self-Reset) 0x0 W [13:12] RESERVED Reserved 0x0 R/W [11:4] CHIP_ID Chip ID 0x7 R [3:0] CHIP_REVISION Chip Revision 0x5 R

    ALARM_READBACK REGISTER Address: 0x01, Reset: 0x0000, Name: ALARM_READBACK

    Parity Error

    Too Few ErrorsAddress Range Error

    Too Many Errors

    0

    01

    02

    03

    04

    05

    06

    07

    08

    09

    010

    011

    012

    013

    014

    015

    0

    [15] PARITY_ERROR (R) [11:0] RESERVED

    [14] TOO_FEW_ERRORS (R)[12] ADDRESS_RANGE_ERROR (R)

    [13] TOO_MANY_ERRORS (R)

    Table 9. Bit Descriptions for ALARM_READBACK Bits Bit Name Settings Description Reset Access 15 PARITY_ERROR Parity Error 0x0 R 14 TOO_FEW_ERRORS Too Few Errors 0x0 R 13 TOO_MANY_ERRORS Too Many Errors 0x0 R 12 ADDRESS_RANGE_ERROR Address Range Error 0x0 R [11:0] RESERVED Reserved 0x0 R

  • Data Sheet ADRF6780

    Rev. B | Page 29 of 35

    ALARM_MASK REGISTER Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASK

    Parity Error Mask - Enable the AlarmOutput Pin

    Too Few Errors Mask -Enable theAlarm Output Pin

    Address Range Error Mask - Enablethe Alarm Output Pin

    Too Many Errors Mask - Enable theAlarm Output Pin

    0

    01

    02

    03

    04

    05

    06

    07

    08

    09

    010

    011

    012

    113

    114

    115

    1

    [15] PARITY_ERROR_MASK (R/W) [11:0] RESERVED

    [14] TOO_FEW_ERRORS_MASK (R/W)

    [12] ADDRESS_RANGE_ERROR_MASK (R/W)

    [13] TOO_MANY_ERRORS_MASK (R/W)

    Table 10. Bit Descriptions for ALARM_MASK Bits Bit Name Settings Description Reset Access 15 PARITY_ERROR_MASK Parity Error MaskEnable the Alarm Output Pin 0x1 R/W 14 TOO_FEW_ERRORS_MASK Too Few Errors MaskEnable the Alarm Output Pin 0x1 R/W 13 TOO_MANY_ERRORS_MASK Too Many Errors MaskEnable the Alarm Output Pin 0x1 R/W 12 ADDRESS_RANGE_ERROR_MASK Address Range Error MaskEnable the Alarm Output Pin 0x1 R/W [11:0] RESERVED Reserved 0xFFF R/W

    ENABLE REGISTER Address: 0x03, Reset: 0x0157, Name: Enable

    UC Bias Enable

    VGA Buffer EnableLO Enable

    Detector EnableLO x1 Enable

    LO Buffer EnableLO x2 Enable

    IF Mode EnableIQ Mode Enable

    0

    11

    12

    13

    04

    15

    06

    17

    08

    19

    010

    011

    012

    013

    014

    015

    0

    [15:9] RESERVED [0] UC_BIAS_ENABLE (R/W)

    [8] VGA_BUFFER_ENABLE (R/W)[1] LO_ENABLE (R/W)

    [7] DETECTOR_ENABLE (R/W)[2] LO_PPF_ENABLE (R/W)

    [6] LO_BUFFER_ENABLE (R/W)[3] LO_X2_ENABLE (R/W)

    [5] IF_MODE_ENABLE (R/W)[4] IQ_MODE_ENABLE (R/W)

    Table 11. Bit Descriptions for Enable Bits Bit Name Settings Description Reset Access [15:9] RESERVED Reserved 0x0 R/W 8 VGA_BUFFER_ENABLE VGA Buffer Enable 0x1 R/W 7 DETECTOR_ENABLE Detector Enable 0x0 R/W 6 LO_BUFFER_ENABLE LO Buffer Enable 0x1 R/W 5 IF_MODE_ENABLE IF Mode Enable 0x0 R/W 4 IQ_MODE_ENABLE IQ Mode Enable 0x1 R/W 3 LO_X2_ENABLE LO 2 Enable 0x0 R/W 2 LO_PPF_ENABLE LO 1 Enable 0x1 R/W 1 LO_ENABLE LO Enable 0x1 R/W 0 UC_BIAS_ENABLE UC Bias Enable 0x1 R/W

  • ADRF6780 Data Sheet

    Rev. B | Page 30 of 35

    LINEARIZE REGISTER Address: 0x04, Reset: 0x0080, Name: Linearize

    RDAC 8 Bits : for IMD PerformanceImprovement (0-255)

    0

    01

    02

    03

    04

    05

    06

    07

    18

    09

    010

    011

    012

    013

    014

    015

    0

    [15:8] RESERVED [7:0] RDAC Linearize (R/W)

    Table 12. Bit Descriptions for Linearize Bits Bit Name Settings Description Reset Access [15:8] RESERVED Reserved 0x0 R/W [7:0] RDAC_LINEARIZE RDAC 8 Bits: for IMD Performance Improvement (0 to 255) 0x80 R/W

    LO_PATH REGISTER Address: 0x05, Reset: 0x0000, Name: LO_PATH

    CDAC for I Phase Accuracy

    Switch to the Other LO SideBandCDAC for Q Phase Accuracy

    0

    01

    02

    03

    04

    05

    06

    07

    08

    09

    010

    011

    012

    013

    014

    015

    0

    [15:11] RESERVED [3:0] I_PATH_PHASE_ACCURACY (R/W)

    [10] LO_SIDEBAND (R/W)[7:4] Q_PATH_PHASE_ACCURACY (R/W)

    [9:8] RESERVED

    Table 13. Bit Descriptions for LO_PATH Bits Bit Name Settings Description Reset Access [15:11] RESERVED Reserved 0x0 R/W 10 LO_SIDEBAND Switch to the Other LO Sideband 0x0 R/W [9:8] RESERVED Reserved 0x0 R/W [7:4] Q_PATH_PHASE_ACCURACY CDAC for Q Phase Accuracy 0x0 R/W [3:0] I_PATH_PHASE_ACCURACY CDAC for I Phase Accuracy 0x0 R/W

  • Data Sheet ADRF6780

    Rev. B | Page 31 of 35

    ADC_CONTROL REGISTER Address: 0x06, Reset: 0x0000, Name: ADC_CONTROL

    ADC Clock Enable

    1: Enable.0: Disable.

    VDET Output Pin Select

    1: VDET Output Select Enable.0: VDET Output Select Disable.

    ADC Enable and Comparator on

    1: Enable.0: Disable.

    ADC FallEdge to Start ADCConvers ion-WriteHigh Then Low

    1: Set ADC convers ion control high.

    0:edge.ADC convers ion activated at falling

    0

    01

    02

    03

    04

    05

    06

    07

    08

    09

    010

    011

    012

    013

    014

    015

    0

    [15:4] RESERVED [0] ADC_CLOCK_ENABLE (R/W)

    [3] VDET_OUTPUT_SELECT (R/W)

    [1] ADC_ENABLE (R/W)

    [2] ADC_START (R/W)

    Table 14. Bit Descriptions for ADC_CONTROL Bits Bit Name Settings Description Reset Access [15:4] RESERVED Reserved 0x0 R/W 3 VDET_OUTPUT_SELECT VDET Output Pin Select 0x0 R/W 0 VDET Output Select Disable 1 VDET Output Select Enable 2 ADC_START ADC FallEdge to Start ADC Conversion Write High Then Low 0x0 R/W 0 ADC Conversion Activated at Falling Edge 1 Set ADC conversion control High 1 ADC_ENABLE ADC Enable and Comparator On 0x0 R/W 0 Disable 1 Enable 0 ADC_CLOCK_ENABLE ADC Clock Enable 0x0 R/W 0 Disable 1 Enable

    ADC_OUTPUT REGISTER Address: 0x0C, Reset: 0x0010, Name: ADC_OUTPUT

    Detector ADC 8 Bit Output

    ADC Busy

    1: Ready.0: Busy.

    0

    01

    02

    03

    04

    05

    06

    07

    08

    09

    010

    011

    012

    013

    014

    015

    0

    [15:9] RESERVED [7:0] ADC_VALUE (R)

    [8] ADC_STATUS (R)

    Table 15. Bit Descriptions for ADC_OUTPUT Bits Bit Name Settings Description Reset Access [15:9] RESERVED Reserved 0x0 R/W 8 ADC_STATUS ADC Busy 0x0 R 0 Busy 1 Ready [7:0] ADC_VALUE Detector ADC 8-Bit Output 0x0 R

  • ADRF6780 Data Sheet

    Rev. B | Page 32 of 35

    BASIC CONNECTIONS FOR OPERATION Figure 83 to Figure 85 show the basic connections for operating the ADRF6780 as it is implemented on the evaluation board of the device.

    1410

    6-10

    0

    AGNDVPRF

    LOIP

    VPLO

    BBI

    N

    BBQ

    N

    VPR

    F

    AGNDRFONAGNDRFOP

    VPLO

    VDET

    PW

    DN

    VPB

    B

    BBI

    PB

    BQP

    VAT

    T

    IFIN

    IFIP

    VP18SDINSCLK

    SE

    NB

    AG

    ND

    ALM

    B

    ADRF6780AGND

    RSTB

    LOIN

    SD

    TO

    VPDT

    VPBI

    TBD0402C0402DNI

    DNI

    C0603

    C0402

    B3S1000

    C0603

    C0402

    R04025.1K

    C0603

    TBD0402C0402

    DNI

    33PF 4.7NF

    R0402

    DNI

    0.1UF

    TBD0402

    0.1UF4.7NF33PF

    C0402DNI

    TBD0402

    C0402

    TBD0402C0402 DNI

    33

    0

    33PF

    TBD0402C0402DNI

    R0402

    100PFC0402

    DNI

    TBD0603TBD0402DNI

    10KDNI

    TBD0402

    33PF

    DNIC0402

    TBD0402

    DNI

    C06030.1UF

    C0402

    C040233PF

    C0402

    C0603

    C0603

    4.7NF

    C0402

    C0603

    C0603

    C0402 C0402

    33PF

    C0402

    R040250

    C04024.7NF

    0

    C0603C0402C0402

    R0402

    0.1UF

    33

    C0402

    0.1UF

    C0603

    33PF

    10KR0603

    C0402

    R040250

    R040250

    0.1UFC0402

    TBD0603

    0.1UF

    R040233

    33

    C0402

    50R0402

    R0603

    69157-102

    C0402TBD0402

    DNI

    C0402100PF

    33PF 4.7NF

    C0402

    R0402

    25-146-1000-92

    4.7NFC0402

    10PF

    DNI

    TBD0402

    R0402

    C0402

    4.7NF

    4.7NFC06030.1UF

    TBD0603

    C0402

    25-146-1000-92

    25-146-1000-92

    C37

    C27

    C16

    R5

    C35

    C34

    C32

    C30

    C29

    C25

    C24

    C21C18

    R9

    R3

    C20

    C7

    C14

    R6

    R1

    DUT

    C31

    C17

    C15

    C39

    R8

    R23

    R100

    BBIN

    C36

    C13

    C9C3

    RSTB

    C2

    C22

    C40

    C23

    R7

    R4

    R2

    C26

    R24 R25

    C28

    BBQN BBQP BBIP

    IFIN

    C8

    C4

    C41C5 IFIP

    PWDN

    C11

    R26

    C12

    C38C33

    LOIP LOIN

    C10

    C1

    C19C6

    RFON

    RFOP

    3.3V_6780

    6780_VATT

    6780_MOSI

    6780_CS

    BBIN

    BBIP

    3.3V_6780

    1.8V

    6780_SCK

    1.8V

    BBQN

    5V

    5V

    3.3V_6780

    5V

    PWDN1.8V

    BBQP

    IFINIFIP

    VDET

    6780_RSTB

    6780_MISO

    LOIP

    ALMB

    3.3V_6780

    LOIN

    6780_RFON

    6780_RFOP

    4

    25262729

    22423

    21

    1611

    28

    1514

    4

    PA

    D

    6187

    2

    20

    1

    8 1 3

    1

    1

    1

    1

    5

    1 1

    21

    19

    223

    30

    9 12 13

    32

    5

    10

    17

    23452345

    4 3 2 5 4 3 2 5 4 3 2 5 4 3 2

    1 1

    31

    1

    1

    AGNDAGND

    AGND

    AGNDAGND

    AGND

    AGND

    AGNDAGND

    AGND

    AGND

    AGND AGND

    AGND AGND

    AGND AGND

    AGNDAGND

    AGNDAGND

    AGND

    AGND

    AGNDAGND

    AGND

    AGND

    AGND

    AGND

    AGND

    AGND

    AGND

    NOTES1. WHEN THE IF MODE IS SET, REMOVE THE 0 R10 TO R13 RESISTORS FROM THE IQ LINES.

    AGNDAGND

    AGNDAGND

    R110

    R120

    R130

    AGND

    AGND

    AGND

    AGND

    2 3 4

    2 3 4

    2 23 34 4

    RED REDRED

    WHTWHT

    BLK

    GRN

    RED

    BLK

    3.3V_6780

    GND2

    1.8V3.3V5V

    VATT ALMB VDET

    GND1

    5V 1.8V

    ALMB VDET6780_VATT

    3.3V_67803.3V

    1

    1

    111

    1 1

    1

    AGNDAGND

    Figure 83. ADRF6780 Evaluation Board Schematic Page 1

    http://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdf

  • Data Sheet ADRF6780

    Rev. B | Page 33 of 35

    1410

    6-10

    1

    PROGRAMMING HEADER

    USB

    MUSB-05-F-AB-SM-A-R

    FXL4TD245BQX

    C0603

    10UF

    C321610UF 0.1UF

    C0402C0402C04020.1UF

    C04020.1UF

    R0603

    100K

    80.6

    SAMTECTSW10608GS6PIN

    R0402

    R0402

    0

    0.1UF

    R1206

    C0603

    0.1UF

    0.1UFC0603

    0R0603

    DNI

    R060310K

    100K

    LB L293-N1N2-25-Z(BLUE)

    10K PIC18F24J50-I/ML

    XP2

    R22

    XC4 XC8XC7XC6XC5

    XR6

    XU1

    R16

    R15

    XR2

    XP1 XC12

    U1

    C141

    USB

    R21

    C140

    R20

    3.3V

    3.3V

    USB_VCC

    CS2

    USB_D+

    3.3V

    PGC

    USB_D SCKMOSIMISOCS1

    USB_D+

    USB_VCC

    USB_D-

    3.3V 1.8V

    CS1MOSIMISO

    6780_SCK6780_MISO6780_MOSI6780_CS

    3.3V3.3VSCK

    PGC

    EN1

    EN1

    5

    8 PAD

    7

    9

    10

    1

    N

    P

    A

    165

    17

    15

    19

    64

    13

    3

    7

    109

    11

    1214

    8

    1

    2021

    26

    PAD

    24

    6

    21

    34

    1

    PAD1

    23

    5

    2

    PAD4

    18

    PAD3

    5

    2

    4

    6

    1314

    2

    3PAD2

    C

    22

    15

    1112

    16

    2725

    28

    34

    AGND

    AGNDPAD

    VCCB

    T_R1_N

    B0B1B2B3

    T_R2_N

    OE_N

    GNDT_R3_N

    A3A2A1A0

    T_R0_N

    VCCA

    AGND

    PINSSHIELD

    AGNDAGND

    AGND

    AGND

    AGNDAGNDAGND

    AGND

    RC2_AN11_CTPLS_RP13

    OSC2_CLKO_RA6

    RC1_T1OSI_UOE_N_RP12

    PAD

    RA1_AN1_C2INA_RP1RA0_AN0_C1INA_ULPWU_RP0

    MCLR_N

    RB7_KBI3_PGD_RP10RB6_KBI2_PGC_RP9

    RB5_KBI1_SDI1_SDA1_RP8RB4_KBI0_SCK1_SCL1_RP7

    RB3_AN9_CTEDG2_VPO_RP6RB2_AN8_CTEDG1_VMO_REFO_RP5

    RB1_AN10_RTCC_RP4RB0_AN12_INT0_RP3

    VDD

    RC7_RX1_DT1_SDO1_RP18RC6_TX1_CK1_RP17RC5_D_POS_VP

    RC4_D_NEG_VM

    VUSB

    RC0_T1OSO_T1CKI_RP11

    OSC1_CLKI_RA7

    VSS

    RA5_AN4_SS1_N_HLVDIN_RCV_RP2

    VDDCORE_VCAP

    RA3_AN3_VREF_POS_C1INBRA2_AN2_VREF_NEG_CVREF_C2INB

    Figure 84. ADRF6780 Evaluation Board Schematic Page 2

    3.3V LDO REGULATORS

    1.8V LDO REGULATORNANODAC

    1410

    6-10

    2

    3.3V3.3V_6780

    1000PF

    ADM7172ACPZ-3.3

    C06031000PF

    C0603

    0

    AD5601BCPZ

    C3216R0603

    ADM7170ACPZ-1.8

    C0603

    C0603

    C0603

    4.7UF

    10UF

    ADM7172ACPZ-3.3

    1000PF

    0R0603

    4.7UFC0603

    C0603

    C0603

    0R0603

    4.7UF

    4.7UF

    4.7UFR06034.7UF

    C0603

    0

    U5U4

    C50

    C51

    R14

    U2U3

    C43

    R18

    C42

    C47

    R17

    C46

    C45

    C44

    C49C48

    R19

    CS2

    5V3.3V_6780 3.3V

    3.3V 5V

    5V

    1.8V6780_VATTSCKMOSI

    6

    PAD

    5

    3

    61

    478

    654

    3

    12

    1

    32

    4

    7

    PAD

    8

    PAD

    52

    AGNDAGND

    AGNDAGND

    EP

    VINVIN

    GNDENSS

    SENSEVOUTVOUT

    AGND

    AGND

    PAD

    VOUTGND

    VDD

    SDINSCLK

    SYNC_N

    AGND

    AGNDAGND

    AGNDEP

    VIN2VIN1

    GNDENSS

    SENSEVOUT2VOUT1

    AGND

    AGNDAGND

    AGND

    EP

    VIN2VIN1

    GNDENSS

    SENSEVOUT2VOUT1

    Figure 85. ADRF6780 Evaluation Board Schematic Page 3

    http://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdf

  • ADRF6780 Data Sheet

    Rev. B | Page 34 of 35

    Table 16. Evaluation Board Configuration Options Component Function Default Condition VPLO3.3V, VPDT5V, VPRF5V, VPBB3.3V, VPBI3.3V, 1P8V, AGND

    Power supplies and ground Not applicable

    LOIN, LOIP, VDET, RFON, RFOP, BBIN, BBIP, BBQN, BBQN, IFIN, IFIP, VATT

    Data and clock Not applicable

    SCLK, SDIN, SENB, SDTO SPI Not applicable R2 to R5 33 series resistors for SPI pins R2, R3, R4, R5 = 33 (0402) 5V, 3.3V, 3.3V_6780, 1.8V, VDET, ALMB, VATT, GND1 to GND2

    Test points Not applicable

    PWDN Power-down function Apply 1.8 V on PWDN (Pin 2) jumper to power down the device

    R1, R9, R14, R15, R17 to R20, XR2, XR6 Shorts or power supply decoupling resistors

    R1, R9, R17, R18, R19 = 0 (0402), R8 = 5.1 k (0402), R15 = 100 k (0402), R14, R20 = 0 (0402), XR2 = 10 k (0603), XR6 = 80.6 (1206)

    R6, R7, R16, R22 Pull-up or pull-down resistors R6, R7, R22 = 10 k (0603), R16 = 100 k (0402)

    C1 to C4, C6 to C11, C13 to C15, C17, C20, C22, C23, C26, C28, C31, C33, C36, C38 to C40, C42 to C51, XC12, XC4 to XC8, C140, C141

    The capacitors provide the required decoupling of the supply related pins

    XC4, C45 = 10 F (3216), XC12 = 10 F (0603), C42, C44, C46, C48, C49, C51 = 4.7 F (0603), C1, C2, C4, C8, C22, C28, C39, C40 = 0.1 F (0603), XC5, XC6, XC7, XC8 = 0.1 F (0402), C3, C6, C10, C13, C20, C26, C36, C38 = 4.7 nF (0402), C43, C47, C50 = 1000 pF (0603), C9, C11, C14, C15, C17, C23, C31, C33 = 33 pF (0402), C7 = 10 pF (0402), C140, C141 = 0.1 F (0603)

    R10 to R13 Remove resistors when using IF inputs (IF mode)

    R10, R11, R12, R13 = 0 (0201)

    R23 to R26 Resistors provide a broadband 50 termination for baseband input data

    R23, R24, R25, R26 = 49.9 (0402)

    C5, C41 AC coupling capacitors C5, C41 = 100 pF (0402) C21 CS decoupling resistor C21 = 100 pF (0402) C12, C16, C18, C19, C24, C25, C27, C29, C30, C32, C34, C35, C37, R21

    Do not install (DNI) C16, C24, C34, C35 = 0402, C27, C37, R21 = 0603, C12, C18, C19, C25 = 0402, C29, C30, C32 = 0402

    XP1 Programming header Not applicable XP2 Mini USB connector Connect the mini USB cable to XP2 to interface

    with the SPI RSTB Reset button Click RSTB to reset the device USB Blue LED LED is blue when the USB is connected to XP2, and

    the PC and the ADRF6780 evaluation board is powered on with a 5 V supply

    XU1 Microcontroller PIC18F24J50 U1 Level shifter FXL4TD245BQX U3 to U5 3.3 V and 1.8 V regulators ADM7170 (U3) = 1.8 V regulator,

    ADM7172 (U4) = 3.3 V regulator, ADM7172 (U5) = 3.3 V regulator for ADRF6780

    U2 AD5601 nanoDAC Not applicable DUT ADRF6780, device under test Not applicable

    http://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/ADM7170?doc=ADRF6780.pdfhttp://www.analog.com/ADM7172?doc=ADRF6780.pdfhttp://www.analog.com/ADM7172?doc=ADRF6780.pdfhttp://www.analog.com/ADRF6780?doc=ADRF6780.pdfhttp://www.analog.com/AD5601?doc=ADRF6780.pdfhttp://www.analog.com/ADRF67800?doc=ADRF6780.pdf

  • Data Sheet ADRF6780

    Rev. B | Page 35 of 35

    OUTLINE DIMENSIONS

    0.450.400.35

    3.403.30 SQ3.20

    03-1

    7-20

    17-B

    1

    0.50BSC

    PIN 1INDICATOR

    32

    916

    17

    24

    25

    8

    0.05 MAX0.02 NOM

    0.20 REF

    COPLANARITY0.08

    0.300.250.18

    5.105.00 SQ4.90

    0.800.750.70

    0.20 MIN

    COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5

    3.50 REF

    BOTTOM VIEWTOP VIEW

    PKG

    -003

    530

    SEATINGPLANE

    EXPOSEDPAD

    END VIEW

    PIN 1INDIC ATOR AREA OPTIONS(SEE DETAIL A)

    DETAIL A(JEDEC 95)

    FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

    Figure 86. 32-Lead Lead Frame Chip Scale Package [LFCSP]

    5 mm 5 mm Body and 0.75 mm Package Height (CP-32-20)

    Dimensions shown in millimeters

    ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADRF6780ACPZN-R2 40C to +85C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-20 ADRF6780ACPZN-R7 40C to +85C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-20 ADRF6780-EVALZ Evaluation Board

    1 Z = RoHS-Compliant Part.

    20162017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14106-0-10/17(B)

    www.analog.com

    FEATURESAPPLICATIONSGENERAL DESCRIPTIONFUNCTIONAL BLOCK DIAGRAMREVISION HISTORYSPECIFICATIONSABSOLUTE MAXIMUM RATINGSTHERMAL RESISTANCEESD CAUTION

    PIN CONFIGURATION AND FUNCTION DESCRIPTIONSTYPICAL PERFORMANCE CHARACTERISTICSI/Q MODEIF MODEOUTPUT DETECTOR PERFORMANCERETURN LOSS

    THEORY OF OPERATIONBASEBANDSINGLE SIDEBAND (SSB) UPCONVERSIONLO INPUT PATH SERIAL PORT INTERFACE (SPI)

    APPLICATIONS INFORMATIONCARRIER FEEDTHROUGH NULLING SIDEBAND SUPPRESSION OPTIMIZATION LINEARITY ADCWIDE FREQUENCY PERFORMANCELO Path 1, 2 Full Range

    LAYOUT LO INPUT DRIVEN DIFFERENTIAL vs. SINGLE ENDED

    REGISTER SUMMARYREGISTER DETAILS: WIDEBAND UPCONVERTERCONTROL REGISTERAddress: 0x00, Reset: 0x0075, Name: Control

    ALARM_READBACK REGISTERAddress: 0x01, Reset: 0x0000, Name: ALARM_READBACK

    ALARM_MASK REGISTERAddress: 0x02, Reset: 0xFFFF, Name: ALARM_MASK

    ENABLE REGISTERAddress: 0x03, Reset: 0x0157, Name: Enable

    LINEARIZE REGISTERAddress: 0x04, Reset: 0x0080, Name: Linearize

    LO_PATH REGISTERAddress: 0x05, Reset: 0x0000, Name: LO_PATH

    ADC_CONTROL REGISTERAddress: 0x06, Reset: 0x0000, Name: ADC_CONTROL

    ADC_OUTPUT REGISTERAddress: 0x0C, Reset: 0x0010, Name: ADC_OUTPUT

    BASIC CONNECTIONS FOR OPERATIONOUTLINE DIMENSIONSORDERING GUIDE