UNIT-IV

Within a microcomputer data is transferred in parallel, because that is the fastest way to do it. For transferring data over long distances, however, parallel data transmission requires too many wires. Therefore, data to be sent long distances is usually converted from parallel form to serial form so that it can be sent on a single wire or pair of wires. Serial data is received from a distant source is converted to parallel form so that it can easily transferred on the micro computer busses.

5.1 The standards in Serial Communication:A standard may include the items as assignment of pins and its positions for signals, voltage levels, speed of data transfer, length of cables and mechanical specifications.

In serial Input/Output data can be transmitted as either current or voltage. Typically, 20ma or 60ma current flows are used in teletype equipments. When a teletype is logic ‘1’ the current flows, when it is at logic ‘0’ the current flow is interrupted. The advantage of current loop method is that signals are relatively noise free and are suitable for transmission over a distance.

Data is also transmitted as voltage. The commonly used standard is known as RS-232C. Its voltage levels are not compatible with TTL logic levels. The rate of data transmission is RS-232C is restricted to a maximum of 20Kilo baud and a distance of 50 feet.

For high speed data transmission RS-422A and RS-423A standards are used. This standard has differential amplifiers to reject noise levels and can transmit data at higher speed with longer cable.

The another EEA standard is RS-449. If specifies 37-signal pins on a main connector and 9 additional pins on an optional connector. The signals on this connector are superset of RS-232C signals.

Serial communications can be done using synchronous or asynchronous formats. In synchronous format a receiver and a transmitter are synchronized with some clock, a block of characters is transmitted along with the synchronization information. This format is used for high speed transmission greater than 20 Kbps

.

Fig: 5.1: Synchronous data transmission

The asynchronous format is character oriented. Each character carries the information of the start and stop bits. The transmission begins with one start bit (logic low) followed by a character and one or two stop bits (logic high). This is known as frame. The asynchronous format is generally used in low speed transmissions less than 20 kbps.

Fig: 5.2: Asynchronous data transmission

There are three types of serial data systems: simplex, half-duplex and full-duplex.

Simplex: In simplex transmission data is transmitted in only one direction. A typical example is a data transmission from a microcomputer to a printer.

Tx Rx

data

Tx Rx

CLK CLK

clock

sync

sync . . . . .

Start

Bit

D0

D1

D2

D3

D4

D5

D6

D7

Stop

bits

Stop

bits

Half-duplex: Half-duplex transmission means that the communication can take place in either direction between two systems, but can only occur in one direction at a time. An example of half-duplex transmission is a two-way radio system.

Full-duplex: The full-duplex means that each system can send and receive data at the same time. A normal phone conversation is an example of full-duplex operation.

5.2 Comparison of Serial Input/Output Standards:

Specifications RS-232C RS-422A RS-423A

Speed 20 K baud 10 M baud at 40 ft 100K baud at 30ft

100K baud at 4000ft 1K baud at 400 ft

Distance 50ft 400ft 4000ft

Logic ‘0’ >+3 to +25V B>Aa +4 to +6V

Logic ‘1’ <-3 to –25V B<A -4 to –6V

Receiver

i/p voltage 15V 7V 12V

5.3 Programmable communication Interface 8251 (USART):Intel’s 8251A is a “Universal Synchronous and Asynchronous Receiver and Transmitter” compatible with Intel’s processors. This may be programmed to operate in any of the serial communication modes built into it. This chip converts the parallel data into a serial stream of bits suitable for serial transmission. It is also able to receive a serial stream of bits and convert it into parallel data bytes to be read by a microprocessor.

5.3.1 Architecture and Signal Description of 8251:

Fig: 5.3: Architecture of 8251A

The data buffer interfaces the internal bus of the circuit with the system bus. The read/write control logic controls the operation of the peripheral depending upon the operations initiated by the CPU. This unit also selects one of the two internal addresses those are control address and

data address through the Signal. The modem control unit handles the modem handshake signals to coordinate the communication between the modem and the USART. The transmit control unit transmits the data byte received by the data buffer from the CPU for further serial communication.

This decides the transmission rate which is controlled by the TXC input frequency. This unit also derives two transmitter status signals namely TXRDY and TXEMPTY. These may be used by CPU for handshaking. The transmit buffer is a parallel to serial converter that receives a parallel byte and converts into a serial signal and further transmission along the communication channel. The receive control unit decides the receiver frequency as controlled by the RXC input frequency. This unit generates a receiver ready (RXRDY) signal that may be used by the CPU for handshaking. This unit also detects a break in the data string when the 8251 is in asynchronous mode. In synchronous mode, the 8251 detects SYNC character using SYNDET/BD.

5.3.2 8251A Pin Configuration:

Fig: 5.4 8251 A Pin Configuration

D0-D7: This is an 8 bit data bus used to read or write status, command word or data from or to the 8251A.

C/ D (Control Word/Data) : This input pin, together with RD and WR inputs, informs the 8251A that the word on the data bus is either a data or control word / status information. If this pin is 1, control / status is on the bus, otherwise data is on the bus.

RD: This active-low input to 8251A is used to inform it that the CPU is reading either data or status information from its internal registers.

WR: This active-low input to 8251A is used to inform it that the CPU is writing data or control word to 8251A.

CS: This is an active-low chip select input of 8251A. If it is high, no read or write operation can be carried out on 8251. The data bus is tri_stated if this pin is high.

CLK: This input is used to generate internal device timings and is normally connected to clock generator output. This input frequency should be at least 30 times greater than the receiver or transmitter data bit transfer rate.

RESET: A high on this input forces the 8251A into an idle state. The device will remain idle till this input signal again goes low and a new set of control word is written into. The minimum required reset pulse width is 6 clock states, for the proper reset operation.

TXC: (Transmitter clock Input): This transmitter clock input controls the rate at which the character is to be transmitted. The baud rate is equal to the TXC frequency in synchronous transmission mode. In asynchronous mode, the baud rate is one of the three fractions: i.e 1,1/16 or 1/64 of the TXC. The serial data is shifted out on the successive negative edge of the TXC.

TXD: (Transmitted data output): This output pin carries serial stream of the transmitted date bits along with other information like start bit, stop bits and parity bit, etc.

RXC: (Receiver clock Input): This receiver clock input pin controls the rate at which the character is to be received. In synchronous mode, the baud rate is equal to the RXC frequency. In asynchronous mode, the baud rate is one of the three fraction, i.e 1,1/16 and

1/64th of the RXC frequency. The received data is read into the 8251 on rising edge of RXC. In most of the systems, the RXC and TXC frequencies are equal.

RXD: (Receive data Input): This input pin of 8251A receives a composite stream of the data to be received by 8251A.

RXRDY: (Receiver ready output): This output indicates that the 8251A contains a character to be read by the CPU. The RXRDY signal may be used either to interrupt the CPU or may be polled by the CPU. To set the RXRDY signal in asynchronous mode, the receiver must be enabled to sense a state bit and a complete character must be assembled and then transferred to the data output register. In synchronous mode, to set the RXRDY signal, the receiver must be enabled and a character must received. If the data is not successfully read from the receiver data output register before assembly of the next data byte, the overrun condition error flag is set and the previous byte is over written by the next byte if the incoming data and hence it is lost.

TXRDY: (Transmitter Ready): This output signal indicates to the CPU that the internal circuit of the transmitter is ready to accept a new character for transmission from the CPU. The TXRDY signal is set by a leading edge of write signal if a data character is loaded into it from the CPU. In polled operation, the TXRDY status bit will indicate the empty or full status of the transmitter data input register.

DSR: (Data set Ready): This input may be used as a general purpose one bit inverting input port. Its status can be checked by the CPU using a status read operation. This is normally used to check is the Data set is ready when communication with a modem.

DTR: (Data Terminal Ready): This output may be as a general purpose one bit inverting output port. This can be programmable using the command word. This is used to indicate that the device is ready to accept data when the 8251 is communicating with a modem.

RTS: (Request to send data): This output also may be used as a general purpose one bit inverting output port that can be programmable using the command word. This is used to indicate that the device is ready to receive a data byte from the modem. This signal is used to communicate with a modem.

CTS: (Clear to Send) : If the clear to send input line is low, the 8251A is enabled to transmit the serial data provided the enable bit in the command byte is set to ‘1’. If CTS disable command occurs, which the 8251A is transmitting data, the transmitter transmits all the data written to the USART prior to disabling the CTS. If the CTS disable command occurs just before the last character appears in the serial bit string, the character will be transmitted again whenever the CTS is enabled.

TXEMPTY : (Transmitter Empty): If the 8251A, which transmitting, has no characters to transmit, the TXE output goes high and it automatically goes low when a character is received from the CPU, for further transmission. In synchronous mode, a high on this output line indicates that a character has not been loaded and the SYNC character or characters are about to be or are being transmitted automatically as “fillers”. The TXE signal can be used to indicate the end of the transmission mode.

SYNDET/BD (synch Detect / Break Detect): This pin is used in the synchronous mode for detecting SYNC characters (SYNSET) and may be used as either input or output. This can be programmed using the control word. After resetting, it is in the output. When used as an output, the SYNDET pin will go high to indicate that the 8251A has located a SYNC character in the receive mode.

In asynchronous mode, the pin outs as a break detect output. This goes high whenever the RXD pin remains low through to consecutive stop bit sequence.

Initializing an 8251A:

To initialize on 8251A we must send first a mode word and then a command word to the control register address for the device.

D7 D6 D5 D4 D3 D2 D1 D0

Framing Control

00 Not valid

01 Stop bit

10 11/2 Stop bits

Parity Control

X0 No parity

01 odd parity

Character length

00 5_bits

01 6_bits

10 7_bits

Baud rate factor

00 Syn mode

01 Asyn modeX1

10 Asyn modeX16

a)

D7 D6 D5 D4 D3 D2 D1 D0

`

`

b)

D7 D6 D5 D4 D3 D2 D1 D0

DSR

SYNDET F O P TXEMPT RXRD TXRD

EnableHunt Mode

1= Enable Search

for SYN

character

Internal Reset

1=Resets 8251 to mode

Request To Send

Error Reset

1=Reset Error Flags

Set Break

Character

1= Forces

TXD low

Receive Enable

1= Enable

0=Disable

Data Terminal Ready

1= Enable DTR

Transmit Enable

1=Enable EH

IR RTS ER SBRK

RXE DTR TXEN

/

BRKDET

E E E Y Y Y

C)

Fig 5.5: Formats of 8251A mode, command and status words.

a) Mode word b) Command word c) Status word

Fig 5.5 shows the format for these words and for the 8251A status word which is read from the same address. Baud rate factor, specified by the two least significant bits of the mode word, is the ratio between the clock signal applied to the TXC-RXC inputs and the desired baud rate. If bits D0 and D1 are both 0’s, the 8251 A is programmed for synchronous data transfer. In this case the baud rate will be same as the applied TXC and RXC. The other three combinations for these 2 bits represent asynchronous transfer. A baud rate factor of 1 can be used for asynchronous system both use the same TXC and RXC. The character length specified by bits D2 and D3 in the mode word includes only the actual data bits, not the start bit, parity bit or stop bit(s). If parity is disabled, no parity bit is insisted in the transmitted bit string. If the 8251A is programmed for 5, 6 or 7 data bits, the extra bits in the data character byte read from the device will be (xeros) 0’s.

After sending the mode word to an 8251A, we must then send it a command word. A 1 in the least significant bit of the command word enable the transmitter section of the 8251A and the TXRDY output. When enabled, the 8251A TXRDY output will be asserted high if the CTS input has been asserted low, and the transmitter holding buffer is ready for another character from the CPU. The TXRDY signal can be connected to an interrupt input on the CPU of an 8259A, on an interrupt basis. When a character is written to the 8251A data address, the TXRDY signal will go low and remain low until the holding buffer is again ready for another character. Putting a 1 in bit 01 of the command word will cause the DTR output of the 8251 A to be asserted low. This signal is used to tell a modem that a terminal or computer is operational. A 1 in bit D2 of the command word enables the RXRDY output pin of the 8251A. If enabled, the RXRDY go high when the 8251A has a character in its receiver buffer to be read. This signal can be connected to an interrupt input so that characters can be read in on an interrupt basis. The RXRDY output is reset when a character is read from the 8251A.

Putting a 1 in bit D3 of the command word causes the 8251A to output a character all 0’s, which is called a break character. A break character is sometimes used to indicate the end of a block of transmitted data. Sending a command word with a 1 in bit D4 causes the 8251A to reset the parity, overrun, and framing error flags in the 8251A status register. A 1 is bit D5 of the command word will cause the 8251A to assert its request - to - sent (RTS) output low. The signal is sent to a modem to ask whether the modem and the receiving system are ready for data character to be sent.

Putting a 1 in bit D6 of the command word causes the 8251A to be internally reset when the command word is sent. After a software reset command is sent in this way, a new mode word must be sent.

The D7 bit in the command word is only used when the device is operating in synchronous made. A command word with a 1 in this bit position tells the 8251A to look for specified sync character (s) in a stream of bits being shifted in. If the 8251A finds the specified sync characters, it will assert its SYNDET/BD pin high.

Sending and Receiving Characters with an 8251 A:

Data characters can be sent to and read from the 8251A in an interrupt basis or on a polled basis. To send character on an interrupt basis, the TXRDY pin of the 8251A is connected to an interrupt input on the processor of an 8259A priority-interrupt controller. The transmitter and TXRDY output are enabled by putting a 1 in bit D1 of the control word sent to the 8251A during initialization. When the CTS input of the 8251A is asserted low and the 8251A buffer is ready for a character, the TXRDY pin will go high. If the processor and 8259A interrupt path is enabled, the processor will go to an interrupt – service procedure, which writes a data character to the 8251A data address writing a data character causes the 8251A to reset its TXRDY output until the buffer is again ready to receive a character. A counter can be used to keep track of a how array characters have been sent.

In a similar manner characters can be read from on 8251A on an interrupt basis. In this case the RXRDY output of the 8251A is connected to an interrupt input of the processor or an 8259A and this output is enabled by putting a 1 in bit D2 of the command word sent during initialization. When a character has been shifted into 8251A and the character is in the receiver buffer ready to be read, the RXRDY pin will go high. If the interrupt chain through the 8259A and the processor is enabled, the processor will go to an interrupt procedure which

reads in the data character. Reading a data character from the 8251A cause, it to reset the RXRDY output signal. This signal will stay low until another character is ready to be read.

To send characters to an 8251A on a polled basis , the 8251A status register is read and checked over and over until TXRDY bit (D0) is found to be a 1.

5.4 RS-232C Serial Standard:

The devices used to send serial character are often referred to as “data communication equipment or DCE “. The terminals or computers that are sending or receiving the data are referred to as “data terminal equipment or DTE”. To ensure an orderly flow of data between the DTE and DCE, a serial interface is placed between them. This interface coordinates the flow of data, control signals and timing information between the DTE and the DCE.

The RS-232 interface specifies a 25 pin connector and its signals are divided into 4 groups.

1. Data signals2. Control signals

3. Timing signals 4. Ground signals

The voltage levels for all RS-232C signals are as follows: A logic high, or mark, is a voltage between –3V to –15V under load (-25v no load). A logic low or space is a voltage between +3V to +15V under load (+25V no load), but normally used voltage levels are 12V.

Fig 5.6RS-232C Pin Diagram

26 1

25 2

24 3

23 4

22 5

21 6

20 7

19 8

18 9

17 10

16 11

15 12

Protective ground

Transmitted data(TXD)

Receive Data(RXD)

Request to Send(RTS)

Clear to Send(CTS)

Data Set Ready(DSR)

Signal Ground

Received line Signal Detector

Reserved for Data Set Testing

Unassigned

Secondary Read line Signal Detector

Secondary Clear to Send

Power Supply

Unassigned

Transmit signal element timing

Data Signal Rate Selector

Ring Indicator

Signal Quality Detector

Data Terminal ready

Secondary request to send

Unassigned

Receiver Element timing

Secondary Received Data

Secondary Transmit Data

Transmit Signal Element Timing

In this interface data lines use negative logic and control lines use positive logic, so all the signals available in this standard are not compatible with TTL levels because of this incompatibility of the data lines with the TTL logic the voltage translators are used to bring the RS-232C voltage levels to TTL levels. The line drivers are used in case of transmission and in case of reception line receivers are used. The generally used line driver is MC1488 and line receiver is MC1489.

The MC 1488s require + and – supplies, but the MC 1489 require only +5V.

5.5 IEEE 488 (GPIB)

This standard specifies the signals on the link, the type of connector to be used and the way that messages are passed back and forth such standard was first put into the IEEE and it was given the number 488. This IEEE 488 is often referred to as the 488 standard or General Purpose Interface Bus (GPIB).

Specifications of IEEE 488 Bus Standards:

1. Up to 15 devices may be on the bus.

2. The signals on the bus must have defined voltage levels and shapes.

3. Signals are base band with a maximum rate of 1MHz.

4. Total cable length is 20mts (600 feet). The cable has 24 wires, 8 for data, 6 for control and 8 for ground. Data is sent is parallel form 1 byte at a time.

5. Each instrument on the bus has a unique address which is set by the user. With small switches built into the instrument. These addresses are used to direct messages of an instrument or to indicate to the receiving instrument to the senders. It is possible to have there identical units on the bus at different addresses.

6. Devices on the bus are categorized as listeners, talkers or controllers. The controller sends messages and receives them. There can be only one controller in a system. The controller is usually a small computer with an interface to the IEEE 488 bus. The listeners are devices which can only receive messages and the talkers can only send them. An instrument can be a talker or listener depending on its function.

5.6 Prototyping:

Microprocessor based products are hardly ever built and tested as complete system during the initial stages of design. If the system is completely built is difficult to trouble shoot it. Therefore a system is built and tested in stages, each subsystem such as keyboard, display and memory should be built and tested separately as an independent module. The two different types of testing principles are:

1. Borrowing resources from a working system.2. Substitution.

These principles can used in testing each subsystem of a microprocessor based product. A working subsystem can provide an environment similar to the complete prototype system and it is generous enough to share its resources with hardware module to be built. Such a working system is called an In_ circuit emulator.

5.6.1 Trouble Shooting Tools:

In bus oriented systems there is a constant flow of data which continuously changes logic states. This flow of data is controlled by the software instructions therefore to examine what is happening inside the system. The special instruments that are capable of capturing data in relation to instructions are required. The instruments are emulator, logic state analyzer and signature analyzer.

In_circuit Emulator:

In_circuit emulation is the execution of a prototype software program in prototype hardware under the control of a software development system. To perform in_circuit emulation the microprocessor is removed from the prototype design mode and a 40_pin cable from an in_circuit emulator is plugged into the socket previously occupied by the microprocessor. The in_circuit emulator performs all the functions of the replaced microprocessor in addition it allows the prototype hardware to share on its resources such as software, memory, and I/Os. It provides a window for looking into the dynamic, realtime operation of the prototype hardware.

To test a subsystem such as I/O and memory using an in_circuit emulator.

The minimum prototype hardware required is a 40_pin microprocessor socket without microprocessor and a power supply. All other resources can be borrowed from in_circuit emulator as more and prototype hardware is built, the fewer and fewer resources from the

in_circuit emulator is required. In the final stage the total software and hardware are integrated for testing.

Features of In_circuit Emulator:

It is a software ao hardware trouble shooting instrument. It can be stand alone system or part of a software development system. A small program can be entered directly into the emulator or a program can be transferred into the emulator from host computer system through an RS232 serial link. Once the program is loaded , user can interact with the emulator through keyboard or a terminal. The emulator has its own software commands to perform various debugging functions. The main capabilities of in_circuit emulator are:

1. Downloading- These facilities are provided to transfer programs between a software development system or a host computer and the in_circuit emulator.

2. Resources sharing- The in_circuit emulator allows the system being tested to share its memory and I/O ports.

3. Debugging tools- It has debugging tools like, break point, mnemonic display, inline assembly and register display/modification.

5.7 The Microcomputer Development System (MDS):

The microcomputer development system(MDS) is a device that is used in the laboratory for the development of microprocessor based systems. An MDS has peripherals, large memory, mass storage systems such as floppy disk and hard disk, debugging facilities, printers and so on.

Generally an MDS is modular in design. It may have a member of hardware and software supports. Some of them are optional. The hardware and software supports are selected depending on the requirement.

The hardware devices generally available with an MDS are CPU, memory (RAM and ROM), CRT display, Keyboard, floppy disk system, hard disk system, printer, EPROM programmer, emulator and ROM simulator.

The software supports available with an MDS system are OS, Monitor, Text Editor,

Assembler or Macro assembler, Compiler for high level languages like C, FORTRAN, PASCAL, COBOL and BASIC.

These MDSs are suitable for the developments of most of the 8-bit and 16-bit microprocessor based systems.

EPROM programmer:

The user can write a permanent program either in a PROM or EPROM. A special

equipment for programming of PROM or EPROM is called EPROM programmer.

The MDS systems are provided with universal EPROM programmer.

Emulator:

In_circuit emulator is an aid which allows a microprocessor based system to be directly attached to an MDS system for testing.

ROM simulator:

While developing a program the programmer may design to use a ROM though it

does not exist in the system. The simulator can be connected to the system. The simulator behaves as ROM for the user’s system. These are software supports available with the execution of commands like load, verify and display data.

Simulator:

It is a software aid which is used to simulate the behavior of a microcomputer on other computer.