4B8: Electronic System Design · 4B8: Electronic System Design Dr Ken Teo ([email protected])...

4B8: Electronic System DesignDr Ken Teo ([email protected])

4B8: Electronic System Design

Dr Ken Teo (~8L)Dr Peter Spreadbury (~4L)


Content

K.T. P.S. K.T.Also microcontrollers


Assessment• Coursework (25%)

– Michaelmas Term, week 5-7– PSPICE simulation of 1 ‘textbook’ circuit and 1

‘student’ circuit– 3 page report

• Written exam (75%)– Easter term– 1.5 hours– 3 out of 5 questions


Low frequency precision amps• Imperfections of op-amps

– Common mode gain– Input offset voltage– Input bias current– Temperature effects

• Instrumentation amplifier configuration and its applications


1.1. Non ideal input• Op-amp front-end is differential amplifier

‘Long tail pair’

Define CMRR = |Ao/Acm|

vin1

e

co r

RA2

=

e

cCM rR

RA+

−=12

eCM

O

rR

AACMRR 1≈=

(re small)

vout

vin2

RC

R1


1.1. BJT Non ideal input

VB1

• Current source –good CMRR

• Sets IB = IC/β• If VB1 = VB2,

VO1 = VO2• In practice, no,

imperfect transistors

• Some op-amps offset adjust

• Not preferred, use laser trimmed

VB2

VO1 VO2

IB IB

+VCC


Analog Devices OP-90


1.1. FET Non ideal input• IG1 and IG2 are

reverse leakage currents

• FET – reverse biased p-n

• MOSFET – gate leakage

• Double every 10C • Mismatch tends to

be worse than BJT

IG1 IG2


1.2. Input offset voltage• If op-amp inputs shorted, expect zero output• In practice, Voffset (output) α closed loop gain• Define: Vio

coef. etemperatur voltageoffset input average

TVio

=α

∆α=


1.2. Input offset voltage• If op-amp inputs shorted, expect zero output• In practice, Voffset (output) α loop gain• Define: Vio

coef. etemperatur voltageoffset input average

TVio

=α

∆α=

• Low gain circuits, Vio not crucial

• High gain / precision circuits, must consider Vio

• Can trim with offset pot

• BUT – ok for fixed temperature

– external R introduces noise / drift

• Use laser trimmed, low offset devices


1.3 Input bias current / offset current

• Bias current (temperature dependent) cause voltage drops

( )

2b1bos

2b1bb

21

iii2

iii

input define 0,V VWhen

−=

+=

==

NB: Must provide ib path

NB: Best if R1= R2


1.3. Op-amp input model

( )ioO VVVGVgeneral,In

+−= −+


1.3. Op-amp input model

( )

( ) ( )[ ]

( ) ( )[ ]io11b22b21

io2b221b11O

ioO

VRiRiVVG

ViRViRVGV

:connected circuit input the With

VVVGV

+−+−=

+−−−=

+−= −+

Ideal op-amp Error terms


1.4. Data for LM741A

Vio

α

ib

iio

ib


1.4. Data for op-amps

BJT

FET

Inst. Amp


1.5. Note on Noise Gain• Which input to put Ve?

⎟⎟⎠

⎞⎜⎜⎝

⎛ +=

=+⎟⎟⎠

⎞⎜⎜⎝

⎛+

2

21eO

e21

2O

RRRVV

0VRR

RV⎟⎟⎠

⎞⎜⎜⎝

⎛ +=

2

21eO R

RRVV

Does not matter, and Ve is just multiplied by gain


Example• Estimate error VO

LM741C

Vio = 2 mVα= 1.5 µV/CIb= 80 nART = 20 C

Ib

Ib flows through 120K || 1M2 || 1M12 ~ 100K

Error due to Ib = 100K x 80nA = 8 mV

Error due to Vio = 2 mV

Ve = 10mV


Example

Ib

V1 = V2 = 0(definition of Ib)

Ve

mV120101.12V1.12V

02M1VV

M1K120V

K120V:VatKCL

eO

Oeeee

=×==

=−

++

+

To reduce Ve,1) add RB = 100K2) use smaller resistances3) or last resort, trim it

RB


Example• Vio at 20C = 0, no bias current effects, Ve at 70C?

Input offset current effect: IOS = 0.5nA x 50C = 25nA

Ve = 25nA x 100K = 2.5mV

VO = 12 x 2.5 = 30mV

Input offset voltage effect: Vio = 15µV/C x 50C = 0.75mVVO = 12 x 0.75 = 9mV

Total offset change = 30 + 9 = 39mV


1.6. CMRR

CM

O

O

CM

OCMCMO

-

-CM

-

AA CMRR

gain aldifferenti Awhere gain mode common Awhere

AVAVV VVV amplify), to want we(what Difference

2VV Vvoltage, input mode Common

inputs. amplifier the at Vand Apply V

=

=

=

∆+=∴−=∆

+=

+

+

+


1.6. Common mode errors

( )

( )( )( )

2A2A1 Awhere

A2-A1 Awhere 2V)AA(VAA V :to leads This

VAVA Vpaths, gain identical-non ButAVV V ,Ideally

O

CM

21CM21O

21O

-O

+=

=

∆++−=

−=

−=

−+

+


Example• Ideal op-amp, difference amp gain 20, with

R2=R4 and R1=R3, but 1% error in R3.

V1

V2

VOR2 = 20 R1

R2 = R4

R3 = 1.01 R1


Example

( )( )

dB86CMRR & 200RR 200, gain For

dB665.1999AACMRR

01.099.1920A

995.192

2099.19A

V20V99.19VRRV

RRR

R01.1RRRRRVV

RRV

RRR

RRRVV

12

CM

O

CM

O

12O

1

21

1

21

121

2122O

1

21

1

21

43

42O

===

===∴

=−=∴

=+

=∴

−=

⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟

⎠

⎞⎜⎜⎝

⎛ +⎟⎟⎠

⎞⎜⎜⎝

⎛++

=

⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟

⎠

⎞⎜⎜⎝

⎛ +⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

V1

V2

VO


Example• Exposes single op-amp inadequacies:

– Input resistances low, if gain is high– Precise resistance matching required, or

CMRR is bad– Different source resistances upset resistor

matching– Gain not easily adjustable

(change 2 R’s)


1.7. Instrumentation Amp• Good difference amp with high CMRR and

symmetrical input resistance, set gain with R2

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛ +⎟⎟⎠

⎞⎜⎜⎝

⎛−=

2

12

4

321O R

R2RRRVVV


1.8. Integrated inst amp


Example• Strain gauge in desert, -10C to 55C• Gain = 500, input RC has R = 10K• INA114, so:

Change in Vo due to Vio temp effect = 1mV/C x 500 = 0.5 mV/CChange in Vo due to Ib temp effect = 8pA/C x 10K x 500 = 0.04 mV/CCombined variation due to temp effect = 0.54 mV/C

If we say device is trimmed (no offset) at 20C, then variation (-30/+35) is-16.2mV @ -10C to 18.9mV at 55C


Example• INA114, gain=10. Ve = 0.5V @ 50Hz/200kHz

For G = 10, CMRR @ 50Hz = 115dBCMRR @ 200kHz = 60dB

kHz200@mV50Hz50@uV9

)f(CMRR105.0V

CMRRAA

AA CMRR

O

OCM

CM

O

==

×=

=

=


Applications• Thermocouples (eg. K-type, 4mV change

from 0C to 100C)• Microphones• Strain gauges • ECG, nerve signals• NB. Remember to provideinput for bias current

4B8: Electronic System Design · 4B8: Electronic System Design Dr Ken Teo ([email protected])...

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