Data Conversion Circuits - University of Cambridge · 4B8: Electronic System Design Dr Ken Teo...

4B8: Electronic System DesignDr Ken Teo ([email protected])

Data Conversion Circuits

Ken Teo


Aim

• Overview of data acquisition systems• Analyse the performance of various design

strategies for system components• Evaluate errors contributed by system

components


System overview


1. Switching and sampling• Analog switches – BJT’s and FET’s• BJT not preferred as:

– base current merges with collector current– VCE needs to be overcome

• MOSFET preferred as:– Gate is ‘isolated’ (ie. like an isolated switch)– No gate-source forward conduction


MOSFET Characteristics

VGS=10V

VGS=0V

Linearregion

FET in linear region = voltage controlled resistance, MΩ to Ω

0 10V5V

10Ω

10MΩ


Switching circuit

• Roughly linear only if:– Voltage swing is small– Rs >> rds

– No current drawn, ie. RL >> RS, rds

D S

G

Vsig

Vsig

VGS

-10 0 +1020 10 0

RS


CMOS analog switch

-10V

+10Vn-channel

p-channelp-channel

Vsig-10 0 +100 -10 -20

20 10 0n-channelp-channel

n-channel

n // presistance(ie. switch)

• rds roughly constant with signal level• Eg. DG409 CMOS switch, rds ~ 40Ω


MOSFET switch

n-channel

leakage


Non-ideal MOSFET• Finite on-resistance

– Note rds vs Vsig not perfectly flat– Eg. DG409 rds 40-100Ω

• Charge injection from Gate to Channel– Gate to channel is a capacitor, i=C(dV/dt)– Charge injected Q=C(Vhi-Vlo) ~ 20pC, for DG409

VGVhiVlo

Vi/o


Non-ideal MOSFET• Leakage current

– Through reverse-biased source/drain to substrate– DG409 ~ 1nA @ 25C (increases with T)

• Susceptible to damage when signal applied in the power down condition– When off, source/drain to substrate current can kill

device– Need limiting resistors and diodes


Non-ideal MOSFET• Finite switching time

– Propagation delays, eg. DG409 ~ 250ns


Analog Multiplexer

• Ideally, A1A0 and E selects V1-V4

• In reality, there is ron and leakage currents for 2-4


Sample and Hold• Ideally, wish to instantaneously ‘sample’ an input

and ‘hold’ with each ‘control’ command• Some are called ‘track & hold’ – they track the

input until hold command.

MOSFET switchLeakage*

1) op-amp bias current2) capacitor3) MOSFET switch


Circuit problems• Input drives a capacitive load• Capacitor will slowly leak due to self

discharge, and leakage through amplifier and switch

• Capacitor will display dielectric absorption• Charge injection from control input ends

up in the signal path


Measures of performance

signal

sample ∆

∆∆

⊕⊕

δ

δ

For a large C, Small hold stepLarge acquisition timeSmall droop rate


On dielectric absorption• Capacitor which seems fully discharged all

of a sudden has a voltage re-appear when it is open-circuited


Example• 4-channel S&H• Acquisition time (to

0.1%), hold step, droop rate?

• Neglect OP27 slew rate (small signal)

• OP27 leakage = 10nA• DG409, so Rswitch=40Ω

leakage = 1nA charge injection = 20pC propagation delay = 0.25µs


Example• Acquisition time (due to delay + charge)Typical RC charge up circuitV = Vin (1 – e(-t/CR))0.999 = 1 – e(-t / (10nFx40Ω))

t = 2.76µsTotal time = prop. delay + charge up time

= 3µs


Example• Hold step (due to charge injection)20pC charge injected onto 10nF capacitorQ = CV, ie. V = 2mV

• Droop rate (due to leakage)Total leakage (OP27+switch) = 11nAi = C (dV/dt), ie. 11nA = 10nF (dV/dt)Droop rate = dV/dt ~ 1.1 V/sec


PIC16C7x analog input

• Manufacturer states RS (max) = 10kΩ, RSS = 7kΩ • 8 bit ADC, so 256 levels• For ½ LSB, error is 1/2/256 = 1/512, acq. time?

R = 10+1+7 = 18kΩ, so as before, V=Vin(1-e-t/CR), which gives 5.8µs


High performance S&H• Capacitor and switch within a closed loop

amplifier system. • Input is buffered with protection diodes

present.

Data Conversion Circuits - University of Cambridge · 4B8: Electronic System Design Dr Ken Teo...

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