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CS421ComputerPeripheraland

S. TripathyIIT Patna

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Salient features

A pin ua in ine pac age.

It requires +5V power supply. 8086 has a 20 bit address bus

can access upto 1 MB memory locations . -

A19. It can support upto 64K I/O ports.

t prov es , - t reg sters. It can prefetch upto 6 instruction bytes from memory

and ueues them to s eed u instruction execution operates in two modes.

Minimum and Maximum.

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Pindiagramof8086

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- ere e o g o r v o

Common to both minimum and maximum modes S eciall included in minimum confi uration Specially included in maximum configuration

gna s ommon o o mo e AD15-AD0 : These are the time multiplexed memory/

I/O address and data lines. Address remains on the lines during T1 state, while the

data is available on the data bus during T2, T3, Tw andT4.

These lines are active high and float to a tristateduring interrupt acknowledge and local bus holdacknowled e c cles.

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, , ,

multiplexed address and status lines. During T1 these are the most significant address lines for

memory opera ons. During I/O operations, these lines are low. Durin memor or I/O o erations status information is

available on those lines for T2,T3,Tw and T4.

, S5 indicates the condition of the IF flag bit

S4 and S3 combined to indicate which segment register is

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Commonsignals(Contd.) BHE/S7 : The bus high enable is used to indicate the transfer of data

i 1 -

BHE A0 indication

0 0 Whole word

0 1 Upper byte from /to odd address

1 0 Lower byte from/to even address

none

BHE is low during T1 for read, write and interrupt acknowledge cycles,whenever a byte is to be transferred on higher byte of data bus.

The status information is available during T2, T3 and T4. The signal is.

S7 is not used currently

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. RD Read : Indicates the eri heral that the

processor is per orming a memory or I O rea

operation. , ,any read cycle.

The signal remains tristated during the hold.

READY : This is the acknowledgement from theslow device or memory that they have completed

e a a ran er. The signal made available by the devices is

synchronized by the 8284A clock generator to providerea y nput to t e . t e s gna s act ve g .

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Commonsignals(Contd.) INTR-Interrupt Request : This is a level triggered input.

It is observed durin the last clock c cles of each instruction to determine the availabilit oft e request.

If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag.

: s npu s exam ne y a ns ruc on. If the TEST pin goes low, execution will continue, else the processor remains in an idle state.

NMI- Nonmaskable interrupt : This is an edge triggered input which causes a. .

RESET : This input causes the processor to terminate the current activity andstart execution from FFFF0H

CLK- Clock Input : The clock input provides the basic timing for processoroperation and bus control activity.

Its an asymmetric square wave with 33% duty cycle.either minimum or maximum mode.

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M/IO Memory/IO : This is a status line logically equivalent

to S2 in maximum mode. When it is low, it indicates: the CPU is having an I/O operation, and

when it is high, it indicates that the CPU is having a memory

operation. ne eco e ac ve g n e rev ou an re a n ac ve

till final T4 of the current cycle. It is tristated during local bushold acknowledge .

HOLD HLDA: When the HOLD line oes hi h it indicates to

the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold

acknowledge signal on HLDA pin, in the middle of the next clock.

INTA , DEN, ALE

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Signalpinsformaximummode S2, S1, S0 Status Lines : These are the status

lines which reflect the type of operation, being.

LOCK : This output pin indicates that other system bus master will

be prevented from gaining the system bus, while the LOCK signal is.The LOCK signal is activated by the LOCK prefix instruction andremains active until the completion of the next instruction

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SignalsinMXmode QS1, QS0 Queue Status: These lines

code-prefetch queue. -prefetch queue. Thus even the largest (6-b tes instruction can be refetched from the

memory and stored in the prefetch.

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8086 has two blocks BIU and EU. BIU

performs all bus operations such as instruction fetching, reading

and writing operands for memory . The instruction bytes are transferred to the instruction queue. BIU contains Instruction queue, Segment registers, Instruction

,

EU executes instructions from the instruction system byte queue. i i i i i

and Index register, Flag register

Both units o erate as nchronousl to ive the 8086 anoverlapping instruction fetch and execution mechanism which iscalled as Pipelining. This results in efficient use of the system bus and system

.

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Registersin8086

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. , ,instructions are executedMOV AL,35H

,

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emory rite

outputs the memoryaddress bus

be written on thedata bus ue a wr e

to memory =

8088 and M/IO = 1for 8086

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All the rocessor bus c cles consist of at least four clock

cycles. T1, T2, T3, T4.

The address is transmitted by the processor during T1. Itis resent on the bus onl for one c cle During T2, the bus is tristated for changing the direction

of bus for the following data read cycle., .

In case, the address device is slow NOT READY status /wait status Tw are inserted between T3 and T4.

e a ress a c ena e s gna s em e ur ngby the processor (minimum mode) or the bus controller

(maximum mode) depending upon the status of the MN/MX Status bits S3 to S7 are multiplexed with higher order

address bits and the BHE signal. Address is valid during T1.

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Blockdiagramof8086MPU(Minimummode)

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B

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Blockdiagramof8086MPU(Maximummode)

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MemoryReadCycle(Maximummode)

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ac a ress s

But address registersare only 16 bits long. There are four types of

memory segments. data,code, stack and anothera a eg en ca e e

extra segment , , ,

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SegmentsandCorrespondingRegistersUsedforSpecifyingOffSets

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Memoryorganization Total memory size is 1MB

Program, data and stack occupies the space rocessor can e ec ve y use - a ress, so

Program memory:

Program can be located anywhere in memory. It can be calledthrough 1MB

Data memory:

segment_name:, DS:). So limit upto 256KB Stack Memory:

Stack can be an where in the memor Reserved memory:

0000h - 03FFh are reserved for interrupt vectors.

Each interrupt vector is a 32-bit pointer in format segment:offset. FFF0h - FFFFh : After reset the processor starts from FFFF0