33408 - B.Sc IT Pro · addressing mode, controlled by PGE, is enabled for the Pentium Pro. MCE...

33408 (2½ Hours) [Total Marks: 75]

N. B.: (1) All questions are compulsory.

(2) Make suitable assumptions wherever necessary and state the assumptions made.

(3) Answers to the same question must be written together.

(4) Numbers to the right indicate marks.

(5) Draw neat labeled diagrams wherever necessary.

(6) Use of Non-programmable calculators is allowed.

1. Attempt any three of the following: 15

a. How does a Microprocessor work?

Finally it will send out the result in binary to the data bus line

b. Explain the following in terms of Compilers:-

i) Source code

ii) Object code

c. How is a flipflop or a latch used as a storage element?

https://abdullahsurati.github.io/bscit


d. What are the different internal data operations and the register of the 8085 microprocessor?

e. Describe the various buses in the 8085 microprocessor.

Diagram : 1 mrks

Data bus



Address bus

Control Bus

Explanation of the interconnection with reference to 8085 microprocessor

f. Draw a neat labelled diagram of the 8085 Microprocessor



Drawing and naming of 8 to 10 parts correctly.


a. Compare the working of an IN and OUT instruction in 8085 microprocessor



Explain diag



b. Write a short note on Memory mapped I/O techniques. Points to be covered

c. List and describe the various Arithmetic instructions in the 8085 microprocessor instruction set.



ADD , ADI, ADC ,ACI, SUB, SUI,SBB, SBI, DAD with one – two line description and

example

d. Write an assembly program to subtract the contents of memory location 2041H from 2040H and

store the difference in 2050H.

LDA 2041

MOV B,A

LDA 2040

SUB B

STA 2050

HLT

e. Compare and explain the following instruction :-

i. LDAX and STAX

LDAX load the contents of the memory location whose the address written

in BC register pair or DE register pair to the accumulator.

STAX load the contents of the accumulator to memory location whose the

address written in BC register pair or DE register pair

ii. JC and JNC

JC address :- jump or transfer control to the address if the carry flag is set

to 1 by the previous operation

JNC address :- jump or transfer control to the address if the carry flag is

not set to 1by the previous operation

iii. HLT and NOP

HLT : halt the program

NOP : NO operation

2

2

1

f. Explain the working of the instructions XRA A and the ANI FOH.

XRA A ; XOR the content of the accumulator to it self while will flush the accumulator contents

make it zero, setting all flags to default

ANI FOH ; ANDing the contents of the accumulator to the FOH will maskoff the lower nibble of

the accumulator contents eg ABH AND FOH = AOH


a. Write an assembly program for 8085 microprocessor to exchange the contents of memory

location 2020H and 2021H

LXI H, 2020 H

MOV B, M

INX H

MOV A, M

MOV M,B

DCX H

MOV M, A

HLT

b. Explain how rotate instructions can be used to check the if the hexadecimal number is odd or an

even number .

Method 1 : rotation right and checking the carry

If set then odd else even

Method 2 : ANI 01H with the number to be checked if the result is a one then odd number else

even number

Prog or flowchart or algorithm needed

c. Calculate the time delay for the 8085-based Microcomputer with 2 MHz clock frequency.



Label Mnemonics Operand T cycle

LXI B, 2384H 10

LOOP: DCX B 6

MOV A,C 4

ORA B 4

JNZ LOOP 10/7

d. Write a program to generate a Square wave of a 500 microsecond delay.



e. Explain the effect of the POP and PUSH instruction on the Stack Pointer.



f. List and describe the working of Various Calls and Returns instruction in 8085 microprocessor



a. Write an assembly program for 8085 microprocessor to convert (1111 1111) 2 to its BCD

equivalent.



INX H ; GO TO NEXT BUFFER LOCATION

RET

Explain the following instruction for 8085 microprocessor :-

i) DAA



ii) XCHG

b. Explain the working of an interrupt in 8085 microprocessor.



c. What is the function of an editor , assembler and loader?



d. List and describe of files generated after cross assembling



e. Write a short note on SIM instruction.


a. What are the features of Pentium Processor.

Pentium require a single +5.0 V power supply for operation. The power supply current averages

3.3 A for the 66 MHz version of the Pentium, and 2.91 A for the 60 MHz version. Because these

currents are significant, so are the power dissipations of these microprocessors: 13 W for the 66

MHz version and 11.9 W for the 60 MHz version. The current versions of the Pentium, 90 MHz



and above, use a 3.3 V power supply with reduced current consumption. At present, a good heat

sink with considerable airflow is required to keep the Pentium cool. The Pentium contains

multiple

VCC and VSS connections that must all be connected to +5.0 V or +3.3 V and ground for

proper operation. Some of the pins are labeled N/C (no connection) and must not be connected.

The latest versions of the Pentium have been improved to reduce the power dissipation. For

example, the 233 MHz Pentium requires 3.4 A or current, which is only slightly more than the

3.3 A required by the early 66 MHz version.

Each Pentium output pin is capable of providing 4.0 mA of current at a logic 0 level and

2.0 mA at a logic 1 level. This represents an increase in drive current, compared to the 2.0 mA

available on earlier 8086, 8088, and 80286 output pins. Each input pin represents a small load

requiring only 15 μA of current. In some systems, except the smallest, these current levels

b. List and describe the special Pentium registers

SPECIAL PENTIUM PRO FEATURES

The Pentium Pro is essentially the same microprocessor as the 80386, 80486, and Pentium,

except that some additional features and changes to the control register set have occurred. This

section highlights the differences between the 80386 control register structure and the Pentium

Pro control register.

Control Register 4

Figure 18–17 shows control register 4 of the Pentium Pro microprocessor. Notice that CR4 has

two new control bits that are added to the control register array.

This section of the text explains only the two new Pentium Pro components in the control

register 4. (Refer to Figure 18–8 for a description and illustration of the Pentium control

registers.)

Following is a description of the Pentium CR4 bits and the new Pentium Pro control bits in

control register CRM4:

VME Virtual mode extension enables support for the virtual interrupt flag in protected

mode. If VME = 0, virtual interrupt support is disabled.

PVI Protected mode virtual interrupt enables support for the virtual interrupt flag in

protected mode.

TSD Time stamp disable controls the RDTSC instruction.

DE Debugging extension enables I/O breakpoint debugging extensions when set.

PSE Page size extension enables 4M-byte memory pages when set in the Pentium, or

2M-byte pages when set in the Pentium Pro whenever PSE is also set.

PAE Page address extension enables address lines A35–A32 whenever a special new

addressing mode, controlled by PGE, is enabled for the Pentium Pro.

MCE Machine check enable enables the machine checking interrupt.

PGE Page extension controls the new, larger 64G addressing mode whenever it is set

along with PAE and PSE.

DIAGRAM

c. Describe the memory management in Pentium and Pentium pro processors

The Pentium memory system is divided into eight banks where each bank stores byte-wide

data with a parity bit. The Pentium, like the 80486, employs internal parity generation and

checking logic for the memory system’s data bus information. (Note that most Pentium systems

do not use parity checks, because ECC is available.) The 64-bit-wide memory is important to

double-precision floating-point data. Recall that a double-precision floating-point number is 64

bits wide. Because of the change to a 64-bit-wide data bus, the Pentium is able to retrieve

floating-

point data with one read cycle, instead of two as in the 80486. This causes the Pentium to

function at a higher throughput than an 80486. As with earlier 32-bit Intel microprocessors, the



memory system is numbered in bytes, from byte 00000000H to byte FFFFFFFFH.

Memory selection is accomplished with the bank enable signals ( – ). These separate

memory banks allow the Pentium to access any single byte, word, doubleword, or quadword

with one memory transfer cycle. As with earlier memory selection logic, eight separate write

strobes are generated for writing to the memory system.

A new feature added to the Pentium is its capability to check and generate parity for the

address bus (A31–A5) during certain operations. The AP pin provides the system with parity

information and the indicates a bad parity check for the address bus. The Pentium takes

no action when an address parity error is detected. The error must be assessed by the system and

the system must take appropriate action (an interrupt), if so desired.

BANKS BE7… BE0 8 BYTE WIDE

The memory system for the Pentium Pro microprocessor is 4G bytes in size, just as in the

80386DX–Pentium microprocessors, but access to an area between 4G and 64G is made possible

by additional address signals A32–A35. The Pentium Pro uses a 64-bit data bus to address

memory organized in eight banks that each contain 8G bytes of data. Note that the additional

memory is enabled with bit position 5 of CR4 and is accessible only when 2M paging is enabled.

Note also that 2M paging is new to the Pentium Pro to allow memory above 4G to be accessed.

More information is presented on Pentium Pro paging later in this chapter. Refer to Figure 18–15

for the organization of the Pentium Pro physical memory system.

The Pentium Pro memory system is divided into eight banks where each bank stores a

byte-wide data with a parity bit. Note that most Pentium and Pentium Pro microprocessor-based

systems forgo the use of the parity bit. The Pentium Pro, like the 80486 and Pentium, employs

internal parity generation and checking logic for the memory system data bus information. The

64-bit-wide memory is important to double-precision floating-point data. Recall that a

doubleprecision floating-point number is 64 bits wide. As with earlier Intel microprocessors, the

memory

system is numbered in bytes from byte 000000000H to byte FFFFFFFFFH. This nine-digit

hexadecimal address is employed in a system that addresses 64G of memory.

Memory selection is accomplished with the bank enable signals ( – ). In the

Pentium Pro microprocessor, the bank enable signals are presented on the address bus (A15–A8)

during the second clock cycle of a memory or I/O access. These must be extracted from the

address bus to access memory banks. The separate memory banks allow the Pentium Pro to

access any single byte, word, doubleword, or quadword with one memory transfer cycle. As with

earlier memory selection logic, we often generate eight separate write strobes for writing to the

memory system. Note that the memory write information is provided on the request lines from

the microprocessor during the second clock phase of a memory or I/O access.

A new feature added to the Pentium and Pentium Pro is the capability to check and generate

parity for the address bus during certain operations. The pin (Pentium) or pins (Pentium

Pro) provide the system with parity information, and the (Pentium) or pins (Pentium

Pro) indicate a bad parity check for the address bus. The Pentium Pro takes no action when an

address-parity error is detected. The error must be assessed by the system, and the system must

take appropriate action (an interrupt) if so desired.

New to the Pentium Pro is a built-in error-correction circuit (ECC) that allows the correction

of a one-bit error and the detection of a two-bit error. To accomplish the detection and

APCHK AP

AP

BE7 BE0 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0

d. Compare Core i5 and i7 processors.



e. Describe the general SPARC Architecture.

SPARC is a CPU instruction set architecture (ISA), derived from a reduced

instruction set computer (RISC) lineage. As an architecture, SPARC allows for a

spectrum of chip and system implementations at a variety of price/performance

points for a range of applications, including scientific/engineering, programming,

real-time, and commercial.

Design Goals SPARC was designed as a target for optimizing compilers and easily pipelined

hardware implementations. SPARC implementations provide exceptionally high

execution rates and short time-to-market development schedules.

Register Windows SPARC, formulated at Sun Microsystems in 1985, is based on the RISC I &

II

designs engineered at the University of California at Berkeley from 1980 through

1982. the SPARC “register window” architecture, pioneered in UC Berkeley

designs, allows for straightforward, high-performance compilers and a significant

reduction in memory load/store instructions over other RISCs, particularly for

large application programs.

For languages such as C++, where object-oriented programming is dominant,

register windows result in an even greater reduction in instructions executed.

Note that supervisor software, not user programs, manages the register windows.

A supervisor can save a minimum number of registers (approximately 24) at the

time of a context switch, thereby optimizing context switch latency.

One difference between SPARC and the Berkeley RISC I & II is that SPARC

provides greater flexibility to a compiler in its assignment of registers to program

variables. SPARC is more flexible because register window management is not

tied to procedure call and return (CALL and JMPL) instructions, as it is on the

Berkeley machines. Instead, separate instructions (SAVE and RESTORE) provide

register window management.

SPARC System

Components

The architecture allows for a spectrum of input/output (I/O), memory management

unit (MMU), and cache system sub-architectures. SPARC assumes that

these elements are optimally defined by the specific requirements of particular

systems. Note that they are invisible to nearly all user application programs and

the interfaces to them can be limited to localized modules in an associated

operating system.

Reference MMU The SPARC ISA does not mandate that a single MMU design be used for all

system

implementations. Rather, designers are free to use the MMU that is most

appropriate for their application — or no MMU at all, if they wish. A SPARC

“Reference MMU” has been specified, which is appropriate for a wide range of



applications. See Appendix H, “SPARC Reference MMU Architecture,” for

more information.

Supervisor Software SPARC does not assume all implementations must execute identical

supervisor

software. Thus, certain supervisor-visible traits of an implementation can be

tailored to the requirements of the system. For example, SPARC allows for

implementations with different instruction concurrency and different exception

trap hardware.

Memory Model A standard memory model called Total Store Ordering (TSO) is defined for

SPARC. The model applies both to uniprocessors and to shared-memory multiprocessors.

The memory model guarantees that the stores, FLUSHes, and

atomic load-stores of all processors are executed by memory serially in an order

that conforms to the order in which the instructions were issued by processors.

All SPARC implementations must support TSO.

An additional model called Partial Store Ordering (PSO) is defined, which allows

higher-performance memory systems to be built.

Machines (including all early SPARC-based systems) that implement Strong

Consistency (also known as Strong Ordering) automatically satisfy both TSO and

PSO. Machines that implement TSO automatically satisfy PSO.

SPARC System

Components

The architecture allows for a spectrum of input/output (I/O), memory management

unit (MMU), and cache system sub-architectures. SPARC assumes that

these elements are optimally defined by the specific requirements of particular

systems. Note that they are invisible to nearly all user application programs and

the interfaces to them can be limited to localized modules in an associated

operating system.

Reference MMU The SPARC ISA does not mandate that a single MMU design be used for all

system

implementations. Rather, designers are free to use the MMU that is most

appropriate for their application — or no MMU at all, if they wish.

Supervisor Software SPARC does not assume all implementations must execute identical

supervisor

software. Thus, certain supervisor-visible traits of an implementation can be

tailored to the requirements of the system. For example, SPARC allows for

implementations with different instruction concurrency and different exception

trap hardware.

Memory Model A standard memory model called Total Store Ordering (TSO) is defined for

SPARC. The model applies both to uniprocessors and to shared-memory multiprocessors.

The memory model guarantees that the stores, FLUSHes, and

atomic load-stores of all processors are executed by memory serially in an order

that conforms to the order in which the instructions were issued by processors.

All SPARC implementations must support TSO.

An additional model called Partial Store Ordering (PSO) is defined, which allows

higher-performance memory systems to be built.

Machines (including all early SPARC-based systems) that implement Strong

Consistency (also known as Strong Ordering) automatically satisfy both TSO and

PSO. Machines that implement TSO automatically satisfy PSO.

f. What are the various instruction format in the SPARC Architecture?



1. Arithmetic/Logical/Shift instructions

opcode reg1,reg2,reg3 !reg1 op reg2 -> reg3

opcode reg1,const13,reg3 !reg1 op const13 -> reg3

• All "action" instructions (add, sub, and, or, etc.) take three operands.

• The destination is always the third operand.

• The middle operand may be a 13-bit signed constant (-4096...+4095).

• Otherwise, all operands are registers.

• Examples:

add %L1,%L2,%L3 !%L1+%L2->%L3

add %L1,1,%L1 !increment L1

sub %g0,%i3,%i3 !negate i3

sub %L1,10,%G0 !compare %L1 to 10 (discard result)

add %L1,%G0,%L2 !move %L1 to %L2 (add 0 to it)

add %G0,%G0,%L4 !clear L4 (0+0 ->%L4)

• To do the above things in the 680x0, 6 different opcodes would be needed (move, add,

addi, clr, neg, cmp)

2. Load/Store Instructions

opcode [reg1+reg2],reg3

opcode [reg1+const13],reg3

• Only load and store instructions can access memory.

• The contents of reg3 is read/written from/to the address in memory formed by adding

reg1+reg2, or else reg1+const13 (a 13- bit signed constant as above).

• The operands are written in the reverse direction for store instructions, so that the

destination is always last.

• One of reg1 or const13 can be omitted. The assembler will supply $g0 or 0. (This is a

shorthand provided by the assembler. Both are always there in machine language.)

• Examples:

ld [%L1+%L2],%L3 !word at address [%L1+%L2]->%L3

ld [%L1+8],%L2 !word at address [%L1+8]->%L2

ld [%L1],%L2 !word at address [%L1]->%L2

st %g0,[%i2+0] !0 -> word at address in %i2

st %g0,[%i2] !same as above

3. Branch Instructions

opcode address

• Branch to (or otherwise use) the address given.

• There are actually 2 types of addresses (see "relocatability" later) - but they look the

same.

• Examples:



call printf

be Loop

add %L1,[%L2],%L3 !Invalid. No memory access allowed.

ld 5,%L4 !Invalid. Must be a memory access.

SPARC Fundamental Instructions

Load/Store Instructions

• Only these instructions access memory.

• All 32 bits of the register are always affected by a load. If a shorter data item is loaded, it

is padded by either adding zeroes (for unsigned data), or by sign extension (for signed

data).

• In effect, data in memory may be 1, 2, or 4 bytes long, but data in registers is always 4

bytes long.

ld - load (load a word into a register)

st - store (store a word into memory)

ldub - load unsigned byte (fetch a byte, pad with 0's)

ldsb - load signed byte (fetch a byte, sign extend it)

lduh - load unsigned halfword (fetch 2 bytes, pad)

ldsh - load signed halfword (fetch 2 bytes, sign extend)

stb - store byte (store only the LSB)

sth - store halfword (store only the 2 LSB's)

There are also two instructions for double words. The register number must be even,

and 8 bytes are loaded or stored. The MSW goes to the even register and the LSW to the

odd register that follows it.

ldd - load double (load 2 words into 2 registers)

std - store double (store 2 words from 2 registers)

Arithmetic/Logical Instructions

• All 32 bits of every register is used.

• Setting the condition code is always optional. Add "cc" to the opcode to set the condition

code. By default, it is not set.

add - a+b

sub - a-b

and - a&b (bitwise AND)

andn - a&~b (bitwise and - second operand complemented)

or - a|b (bitwise OR)

orn - a|~b (bitwise or - second operand complemented)

xor - a^b (bitwise exclusive or)

xnor - a^~b (bitwise exor - second operand complemented)

Examples:

add %L1,%L2,%L3 ;add %L1+%L2 -> %L3



subcc %L4,10,%G0 ;sub %L4-10, set cc, discard result

or %o3,0xFF,%o3 ;set lowest 8 bits of %o3 to 1's

xnor %L6,%G0,%L6 ;complement %L6 (same as NOT in 680x0)

_____________________________



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