3 D Packaging 2007 For Emc3d

Device Packaging

March 2007

Page1

Photoresists for 3D PackagingPhotoresists for 3D PackagingChallenges And SolutionsChallenges And Solutions

Robert Plass[1], Chunwei Chen[1], Rozalia Beica[2]

Stephen Meyer[1],Georg Pawlowski[1]

[1] AZ Electronic Materials Corp. USA, Branchburg NJ[2] Semitool, Kalispell, MT

www.emc3d.org

2IMAPS Device Packaging

March 2007

Outline

Introduction

Technology Background Bosch Process Photoresist Technology

Comparison of Positive vs Negative Resists

AZ® EXP 125nXT

Performance Comparison Lithography Plating

Conclusions


March 2007

Introduction

Dramatic evolution of portable consumer electronics, such as

require non-traditional packaging technologies to enable

cellular phones audio players cameras video recorder

further miniaturization expanding functionality new feature sets faster communication increasing integration of features

as required by a rapidly growing consumer base.

Consumer applications account for more than 50% of all electronic devices.


March 2007

Technology Background

Through Silicon Vias (TSV) using variations of the Bosch process

Redistribution and metallization using copper plating

Solder bumping using lead-free solders

3D packaging and integration schemes will typically relyon the following base-line technologies:

Target → Provide one photoresist material compatible with all technology requirements


March 2007

3D Packaging Process

Debonding

Substratefront (device side)

Lithography

Via EtchStripping/Cleaning

Insulator/Barrier/Seed Deposition Insulator/Barrier/Seed Deposition

Lithography

Plating/Stripping/Etching Plating/Stripping/Etching

CMP (optional) CMP (optional)

Carrier Bonding

Sequential Thinning Sequential Thinning

Insulator/Barrier/Seed Deposition

Lithography

Plating (Cu and Solder)/ Stripping/Etching

Plating (Cu and Solder)/

Pick and Place/Stacking Pick and Place/Stacking

Dicing

Dicing Debonding

Dicing

Stacking

Chip to Wafer Wafer to Wafer


March 2007

TSV: Technology Background

Highly anisotropic deep reactive ion etching (DRIE) is routinely used forMEMS mass products (‘silicon micromachining’).

-> Etch process concepts can be applied for advanced packaging.

Bosch Process – US 5,501,893 (F. Laermer, 1992).Bosch Process – US 5,501,893 (F. Laermer, 1992).

Alternating, short period process steps of somewhat isotropic silicon removal andAlternating, short period process steps of somewhat isotropic silicon removal andprotective polymer deposition using high-density, inductively coupled plasma (ICP) protective polymer deposition using high-density, inductively coupled plasma (ICP) etching systems.etching systems.

Etch step ‘bites’ into silicon (0.5 – 5 Etch step ‘bites’ into silicon (0.5 – 5 µµm), while polymer deposition minimizesm), while polymer deposition minimizeslateral etch creating vertical, high aspect ratio trenches and holes.lateral etch creating vertical, high aspect ratio trenches and holes.


March 2007

The Bosch Process

Source:L. Lea and D. HynesMEMS Manufacturing M9, 2005


March 2007

Excellent resolution / aspect ratio to minimize ‘real estate’

Fast resist processing (coat, development, strip)

Wide process latitude and reliability

TMAH development

High photospeed, no holding time

Vertical profiles

Universal plating compatibility (Cu, Ni, Au, SnAg, Pb-Free, Soak Tests)

No ‘cracking’ or ‘pull-back’ (underetch) during extended etch processes

Residue-free, simple strip after etch or via fill

High etch selectivity (> 70:1)

Inertness versus etch gas compositions (Bosch Process)

Through Silicon Vias / 3D Packaging: Photoresist Requirements


March 2007

Lithographic Methods

Positive ResistNegative Resist

A chemical change that rendersthe exposed area of the polymer soluble

A physical increase in the molecular weight of the polymer that renders the exposed area insoluble


March 2007

Photoresist Properties Comparison

Process Negative [PP] Positive [DNQ] Remarks

Max FT [µm] > 110 < 60 N >> P

Substrate Compatibility Excellent Good N >= P

Process 3 Steps >= 4 Steps N > P

Coating Uniformity < 2% RSD >= 2 % RSD N > P

Process Latitude Large Smaller N >> P

Gap Margin [µm] Wide Narrow N > P

Development Latitude Large Smaller N > P

Developer Type Organic Organic / Inorganic N < P

Plating Stability Excellent Good N > P

Stripping Special Standard N << PStandard N = P


March 2007

Lithographic Processing Time Line

Pre-

Plat

e Pre

p

Coat a

nd B

ake

Develo

p

Expo

se

Rea

dy to

Pla

te

Typical Positive Tone Process

Typical Negative Tone Process

Pre-

Plat

e Pre

p

Post

Dev

elop

Bake

Coat a

nd B

ake

Post

Exp

ose B

ake

Pre-

Expo

se D

elay

Develo

p

Expo

se

Rea

dy to

Pla

te

Time


March 2007

Total Processing Time – 50 µm FT Process

50 µm Films Positive [DNQ] Negative [PP]Coat 3 min 3 min

Bake 10 min 10 min

Hydration Delay 60 min None

Exposure 4000 mJ/cm2 2000 mJ/cm2

Post Exposure Bake* 30 sec None

Development 10 min 2 min

Post Develop Bake* 2-5 min Not required

Total Time (not counting tool transfer time) About 85 min About 15 min

* Optional


March 2007

Photoresists for Through Silicon Vias

Positive Tone

AZ® EXP 40XT-11

Negative Tone

AZ® EXP 125nXT-10

FT = 40 µmCD = 40 µmSB = 95oC/240s 115oC/240sSuss MA 200Dose Range: 400 – 800 mJ/cm2

PEB = 100oC/60sDevelopment:MIF300 3x60s puddle

Exposure Latitude400 – 800 mJ/cm2

FT = 70 µmCD = 50 – 15 µm SB = 120oC/600s

UltraTech AP 300Dose: 2000 mJ/cm2

Development:MIF300 2x60s puddle

Resolution50 – 15 µm


March 2007

8” Coating Uniformity Maps for AZ® EXP 125nXT

Mean FT: 75.3 µmUniformity: 1.07%RSD


March 2007

Film Thickness Coverage with AZ® EXP 125nXT

Single Coat Capability from 10 µm to 120 µm

10 µm FT 120 µm FT20 µm FT 40 µm FT 70 µm FT 90 µm FT

FT Dependant Dose Range: 500 – 3000 mJ/cm2


March 2007

AZ® EXP 125nXT-10 on Si & Cu @ FT = 70 µm

70 µm 60 µm 50 µm 40 µm100 µm

Si

35 µm 30 µm 25 µm 20 µm 15 µm

Si

Cu

Cu

Aspect Ratio > 5:1

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March ٢٠٠٧Page ١٧

Plating Bath Compatibility Tests

H2SO4 test (Cu Plating)

Concentration: 189 g (98% H2SO4) in 1000 mL DI waterTemperature: 25°C Soaking time: 100 min; 150 min; 180 min

H3BO3 test (Ni Plating)

Concentration: 45 g in 1000 mL DI waterTemperature: 55°CSoaking time: 10 min; 15 min; 20 min

١٨IMAPS Device Packaging

March ٢٠٠٧Page ١٨

Beforesoaking

180 min H2SO4 at 25°C

90 µm C/H, 1:1

Cu Plating Process Compatibility - Soaking Test in H2SO4

Positive Tone Resist (40 µm) Negative Tone Resist (90 µm)

١٩IMAPS Device Packaging

March ٢٠٠٧Page ١٩

90 µm C/H, 1:1

Ni Plating Process Compatibility - Soaking Test in H3BO3

Positive Tone Resist (40 µm) Negative Tone Resist (90 µm)

Beforesoaking

10 min H3BO3 at 55°C



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March ٢٠٠٧Page ٢٠

AZ® EXP 125nXT after Bosch DRIE

Photoresist

Silicon


March 2007

AZ® Exp 125nXT-10 Litho and Cu Plating Process Conditions

Exposure tool: Suss Aligner MA-200 Dose: 1200 to 3400 mJ/cm2

Developer: AZ 300 MIF, 30 sec to 138 sec, multiple puddle

Resist Thickness: 25µm, 50µm, 75µm, 100µm

Descum: 02 Plasma, Plasma Start AXIC Equipment

Cu solution: Intervia 8540

Tool: Semitool CFD 2 Reactor30°C, flow rate = 5 gpm; wafer rotation = 60 rpmDeposition rate = 0.4 - 0.8 µm/min

Stripper: AZ® 400T at 75°C for 20 min


March 2007

Plating Performance (C/H) at 25µm FT, 1200 mJ/cm2

50 µm 40 µm 30 µm60 µm

20 µm 10 µm 9 µm 8 µm

ResistC/H

CuPlate

ResistC/H

CuPlate


March 2007

Resist and Cu Plate Images

ResistPattern

CuPlate

75 µm Vias

75 µmFT

Dose: 3400 mJ/cm2

Develop: 3 x 46 Sec Puddles

25 µmFT

50 µmFT

100 µmFT

Dose: 1200 mJ/cm2

Develop: 2 x 15 Sec PuddlesDose: 1200 mJ/cm2

Develop: 3 x 25 Sec PuddlesDose: 2200 mJ/cm2

Develop: 3 x 35 Sec Puddles

8 µm Vias


March 2007

Cu Plating & Soldering with AZ® EXP 125nXT-10

FT 65µm on Cu (single coat)

90 µm C/H 70 µm L/S 40 µm C/H

Before Plating

After Cu plating

After solder plating

90 µm 40 µm 90 µm 40 µm


March 2007

How Does the Current Generation of Negative Tone TFR’s Match up

Excellent resolution / aspect ratio to minimize ‘real estate’

Fast resist processing (coat, development, strip)

Wide process latitude and reliability

TMAH development

High photospeed, no holding time

Vertical profiles

Universal Plating compatibility (Cu, Ni, Au, SnAg, Pb-Free, Soak Tests)

No ‘cracking’ ‘pull-back’ (underetch) during extended etch processes

Residue-free, simple strip after etch or via fill

High etch selectivity (> 70:1)

Inertness versus etch gas compositions (Bosch Process)


March 2007

Conclusions

▶ Thick Film Resist Technology covers a wide range of packaging needs – Through Silicon Vias (TVS) via the Bosch Process– Redistribution and metallization using copper plating– Solder bumping using lead-free solders– Au bumping (both non-cyanic and cyanic)

▶ Negative resists show advantages in processing latitude and stability

▶ Exceptional coating properties– 10 – 120 µm via single coat– Excellent uniformity ( <2% RSD)

▶ Exceptional aspect ratios (up to or beyond 5:1)

▶ Exceptional exposure latitude

▶ Exceptional chemical stability

▶ Good strippability


March 2007

Acknowledgements

▶ The authors would like to thank Robert Smith for SEM support and LEM Group at AZ Branchburg for excellent maintenance.

3

As we have heard this week everyone is talking about the dramatic growth in consumer electronics.This means that as demands for increased integration of functionality on one device accelerate we need to find ways through packaging to get more functionality in less space.

4

This will have to be done through increased efficiency of packaging.This is a limiting function for how small a device can be.We can make smaller circuits, but they cost more (and in consumer electronics price is the driving factor to get volume)But we still have to connect them and connectors will not get a lot smaller.

Solution: Better packaging.

5

If we look at the packaging process we see 3 litho steps.TSVRedistributionBumping

All with different requirements.It would be great if we could find one resist technology that has the potential to do all three levels

7

One of the more challenging steps will be TSVProblem with adhesion and resistance to Etch

10

New generations of Negative Resist do not require special (reactive) strippers

11

Less delay and shorter total time=Lower Cost of Ownership

14

How do I get such good coatings with manual hand dispense??

15

First generation showed high potential for 100+ um coatings if we could increase the solids loading

Work was done to accomplish this.

After fixing the coating issue we made some formulation modifications to allow for faster photospeed and better development of the deep trenches and vias.

16

Normally with DNQ and Chemically amplified resist you run into profile, adhesion and photospeed issues when going form Si substrates (typically used in early evaluations due to cost) to Cu wafers

No significant changes with new generation negatives

18

Positive shows slight erosion of profile at surface

19

Positive shows attack of surfaceAttack of side walls

WHY??It is not Crosslinked like a Negative resist

20

No under cuttingSlight scallopingNo “Charcoaling” of surfaceHigh selectivity

21

These pictures were generated while testing out our new tool set and we have not fully optimized the process.

Ridges on the contacts are due to optical issue with the mask not being optimized for this tool. Other masks do not show this if set up correctly.

24

Shows SEMS from a different mask and exposure tool

3 D Packaging 2007 For Emc3d

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