2500 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11 ... · Fractional-N Frequency...

2500 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

A Quantization Noise Suppression Technique for�� Fractional-N Frequency Synthesizers

Yu-Che Yang, Shih-An Yu, Yu-Hsuan Liu, Tao Wang, and Shey-Shi Lu, Senior Member, IEEE

Abstract—The first circuit implementation of quantization noisesuppression technique for �� fractionalfrequency synthe-sizers using reduced step size of frequency dividers is presentedin this paper. This technique is based on a 1/1.5 divider cell whichcan reduce the step size of the frequency divider to 0.5 and thus thereduced step size suppresses the quantization noise by 6 dB. Thisfrequency synthesizer is intended for a WLAN 802.11a/WiMAX802.16e transceiver. This chip is implemented in a 0.18- m CMOSprocess and the die size is 1.23 mm 0.83 mm. The power con-sumption is 47.8 mW. The in-band phase noise of 100 dBc/Hzat 10 kHz offset and out-of-band phase noise of 124 dBc/Hz at1 MHz offset are measured with a loop bandwidth of 200 kHz. Thefrequency resolution is less than 1 Hz and the lock time is smallerthan 10 s.

Index Terms—CMOS RF, delta-sigma (��), fractional-N fre-quency synthesizers, frequency dividers, phase-locked loop (PLL),phase noise, quantization noise suppression, WLAN, WiMAX.

I. INTRODUCTION

PHASE-LOCKED LOOP (PLL)-based frequency syn-thesizers are used in wireless communication systems.

Conventional integer-N frequency synthesizers suffer the funda-mental tradeoffs between loop bandwidth and channel spacing.To resolve this problem, fractionalfrequency synthesizersare adopted as frequency generators because they offer widebandwidth with narrow channel spacing, and allow an alter-native tradeoff among PLL design constraints for phase noise,lock time, and reference spur [1]–[5]. Since the fractional-frequency synthesizer is able to generate a fractional divisionratio, the output frequency needs not to be an integer multipleof the reference frequency. Therefore, a smaller division ratiocan be chosen and results in lower in-band phase noise.

A fractionalfrequency synthesizer is usually based on afractional divider composed of a modulator and a frequencydivider with integer division ratio. The modulator generatesa pseudo-random bit sequence to switch the frequency divider’sdivision ratio so that the desired fractional division ratio is ob-tained. However, since the intrinsic moduli of the divider remain

Manuscript received January 11, 2006; revised July 12, 2006. This work wassupported by the National Science Council under Grant NSC95-2220-E-002-015.

Y.-C. Yang and S.-S. Lu are with the Department of Electrical Engineering,National Taiwan University, Taipei, Taiwan, 10617, R.O.C. (e-mail: [email protected]).

S.-A. Yu is with Columbia University, New York, NY 10027 USA.Y.-H. Liu is with Realtek Semiconductor Corporation, Hsinchu 300, Taiwan,

R.O.C.T. Wang is with the Department of Electrical Engineering, National Taiwan

University, Taipei, Taiwan, 10617, R.O.C.Digital Object Identifier 10.1109/JSSC.2006.883325

integers, they have constant deviations from the desired frac-tional number, which is so-called quantization error. The quan-tization error introduces the high-pass quantization noise anddegrades the phase noise of the frequency synthesizer [1], [6]. Inorder to suppress the quantization noise, one can either increasethe order of the loop filter, or decrease the loop bandwidth. Theformer method reduces the phase margin and hence endangersthe stability [7], while the latter one obviously conflicts to theoriginal goal of increasing bandwidth by fractional- synthesis.

In this paper, we present a fractionalfrequency synthesizerwith a quantization noise suppression technique. The main ideais to reduce the step size of the frequency divider in the PLL to0.5, so that the quantization noise contributed by the mod-ulator can be lowered and consequently the out-of-band phasenoise can be reduced. This general idea was originally proposedby Sumi in [8] and [9] and then others [10]–[12], which differamong themselves in the realization of dividers. Based on thisconcept and our previous work [13], we present the first circuitimplementation of this general idea with experimental resultsand its application to a PLL in this paper. The experimental re-sults agree well with the theoretical prediction which will bedetailed in Section II: the out-of-band phase noise contributedby the modulator is reduced by 6 dB. Moreover, this tech-nique can also co-exist with other quantization noise suppres-sion methods using charge pump current compensation, such asthose proposed in [14] and [15] and hence the phase noise canbe further suppressed by 6 dB. Note that other researchers havealready demonstrated different techniques [16] for the reduc-tion of the quantization noise below that of voltage-controlledoscillator (VCO) noise. In such case, our approach will not helpquantization noise performance further. That is, we propose analternative method for the suppression of phase noise in casethat the out-of-band phase noise is still dominated by the quan-tization noise.

A reduced modulator adopted in common practice ofcommercial frequency synthesizer is used. The hardware of the

modulator is reduced by truncating the second and the thirdstages so that 1/3 die area and 1/3 power consumption of the

modulator can be saved.The frequency synthesizer is intended to be applied in the

802.11a WLAN/802.16e WiMAX direct-conversion transceiverusing sub-harmonic mixers to avoid the problem of local os-cillator (LO) self-mixing in receive as well as LO pulling intransmit [17]. Therefore, the required LO frequency is half ofthe RF frequency, i.e. 2575 2910 MHz and consequently thetuning range of the synthesizer is designed from 2500 MHz to3200 MHz to cover this band.

0018-9200/$20.00 © 2006 IEEE

YANG et al.: A QUANTIZATION NOISE SUPPRESSION TECHNIQUE FOR FRACTIONAL- FREQUENCY SYNTHESIZERS 2501

Fig. 1. Function block diagram of the implemented frequency synthesizer.

This paper is organized as follows. Section II discusses therelationship between quantization level and quantization noise.The circuit blocks of the frequency synthesizer are described inSection III. The experimental results are given in Section IV,and in Section V, we conclude the work.

II. QUANTIZATION LEVEL AND QUANTIZATION NOISE

A MASH3 fractionalfrequency synthesizer utilizesa modulator to produce a fractional division ratio of

by changing the divider’s modulus among, , , , , , , and ,

where is the integer modulus of the frequency divider and isthe average fractional number generated by the modulator[3]. However, the quantization noise occurs and degrades thetotal phase noise of the frequency synthesizer since the intrinsicmodulus of the frequency divider is still an integer. The powerspectral density of the phase noise contributed by themodulator can be derived as [1]

(1)

where is the desired division ratio and denotes the av-erage divider output frequency. is the rms spectral densityof the quantization noise which is the difference betweenthe fractional part of and the bit stream generated by the

modulator.

From the above equation, is proportional to the squarevalue of , which in turn is determined by the step size of

. Therefore, it is predicted that a divider with a step size of0.5 will generate 6 dB lower quantization noise than a dividerwith a step size of 1. For contrast, consider the following situa-tion where a prescaler with constant modulus is put between theVCO and the programmable divider to relax the design of theprogrammable divider [18], [19]. According to (1), this constantmodulus prescaler in conjuction with the programmable dividerwill lead to with step size larger than 1 and cause a raisein the out-of-band phase noise. To verify this point, we designa modulus combiner so that the effects of with differentstep sizes can be tested in the same frequency synthesizer (seeSection III-D).

III. CIRCUIT IMPLEMENTATION

A. Architecture

The block diagram of the proposed frequency synthesizer isshown in Fig. 1. The loop filter is off-chip so that we can ad-just the loop bandwidth to examine the functions of the 1/1.5divider cell. The whole chip consists of a VCO, a programmablefrequency divider with a step size of 0.5, a phase/frequencydetector (PFD), a charge pump (CP), a reference input buffer(I/B), a MASH3 modulator (DSM), a three-wire interfacecontrol circuit (TWIF), and inter-stage buffers. MUX1, MUX2,and MUX3 are used to change the polarity of the divided VCO


Fig. 2. Schematic of the 1/1.5 divider cell.

signal, and then the PFD and the modulator can be trig-gered at different clock edges to reduce the substrate noise cou-pling [4]. The frequency range of the frequency synthesizer is2500–3200 MHz. Because the frequency divider has a widemodulus range of 32–511.5, reference frequencies from 7 to78 MHz can be used.

B. 1/1.5 Divider Cell

There are several ways to implement the frequency dividerswith moduli having a step size smaller than one, such as thedivide-by-2/2.5/3/3.5 circuits described in [2] and [20] or thedivide-by-1/1.25/1.5/1.75 circuit in [21]. Dividers with staticfractional moduli can also be found in [22] and [23]. Both thedivide-by-2/2.5/3/3.5 and the divide-by-1/1.25/1.5/1.75 circuitutilize a 4-phase divide-by-2 circuit to generate quadrature out-puts and a phase selector to switch among different phases, butthe only difference is that the divide-by-1/1.25/1.5/1.75 circuitrequires quadrature input signals. By selecting the outputs withphase differences of 90 /45 , the step size of 0.5/0.25 can berealized.

Different from these dividers, we propose a 1/1.5 divider cell.The schematic of the 1/1.5 divider cell is depicted in Fig. 2.The key operating principle of the 1/1.5 divider cell is to triggerthe divider on the rising and falling edges of the input signal inturn. For this purpose, two latches (latch1 and latch2 or latch3and latch4), one (latch2 or latch4) enabled by the positive leveland the other (latch1 or latch3) enabled by the negative levelof the input signal, are parallel-connected and followed by amultiplexer (MUX1 or MUX2). These three functional blocksform a double-edge-triggered flip-flop (DTFF) [24]. By usingthe input signal to control latches as well as multiplexers, this ar-chitecture may have a potential timing race problem. However,since the multiplexers select the latches that are holding data, theglitches will not occur unless the input-to-multiplexer delay is

much larger than the input-to-latch delay. Because both delaysare small compared to the time constant of the output load of thelatches, the multiplexers can always switch before the latcheschange their states and hence the timing race problem does nothappen under all PVT conditions.

Modified from the conventional 2/3 divider cell, the 1/1.5divider cell also consists of two main parts: the prescaler logicand end-of-cycle logic [25]. The prescaler logic divides thefrequency of the input signal by 1 or 1.5 depending on thedelay period of the end-of-cycle logic, while the delay timeof end-of-cycle logic is based on the state of the two controlsignals MOD and FB_CTRL. When MOD and FB_CTRL areboth high, the 1/1.5 divider cell is in the divde-by-1.5 mode andthe prescaler logic swallows half extra period of the input signaldue to the delay of the end-of-cycle logic. The timing chart ofthe 1/1.5 divider cell in the divide-by-1.5 mode is illustrated inFig. 3(a), and the state diagram is shown in Fig. 3(b). Accordingto Fig. 3(b), no hidden state exists in this architecture. Wheneither MOD or FB_CTRL is low, the output signal of latch1stays high (low) and the output signal of latch2 stays low (high)and thus the 1/1.5 divider cell simply tracks the input signal,that is, the divider is in the divide-by-1 mode.

Although dividing by 1 means that this 1/1.5 divider cell justpasses the VCO signal to the following divider chain, whichmay raise a concern about wasting power and area, this cellhas an advantage that quadrature signal generation and phaseselector are not required. Accurate quadrature outputs and sym-metrical signal paths need careful layout as well as small de-vice mismatches, which is especially difficult for the first di-vider cell. Because the first divider cell operates at the highestfrequency , small mismatches lead to significant phaseerrors. Phase errors in phase switching dividers will induce un-desired fractional spurs and degrade the performance of the fre-quency synthesizer. The detailed discussion of this phenomenoncan be found in [26].


Fig. 3. (a) Timing chart of 1/1.5 divider cell in the divide-by-1.5 mode.(b) States diagram of the 1/1.5 divider cell in the divide-by-1.5 mode.

Another important issue of the 1/1.5 divider cell is theduty cycle of the input signal. According to [9] and [11], thefractional spurs appear at twice the fractional frequency in afractional frequency synthesizer whose frequency divider hasmoduli with a step size of 0.5, assuming that the duty cycle ofthe input signal is 50%. To illustrate this point, please refer toFig. 4(a) and (b). In Fig. 4(a), a frequency divider with stepsize of 1 generating a fractional modulus of 2.25 by switchingbetween 2 and 3 is shown. Since the modulus repeats everyfour reference period, the fractional spurs locate at .As for the frequency divider with step size of 0.5 [Fig. 4(b)],when a fractional modulus of 2.25 is generated, the modulusis switched between 2 and 2.5, and the modulus repeats everytwo reference period. Therefore, the fractional spurs locate at

, i.e. twice the fractional frequency of . However,if the input signal is not exactly 50% in duty cycle, then thefractional spurs will be shifted back to the fractional frequency.The reason is illustrated in Fig. 4(c). Because the frequencydivider with a step size of 0.5 is double-edge triggered, thenon-50% duty cycle causes period mismatch in the two di-vide-by-2.5 period, and thus makes the total period extend tofour reference cycle. Consequently, the fractional spurs moveto a frequency offset of . Nevertheless, the problem offractional spurs caused by this technique is not worse thanthat by the conventional frequency divider with step size of 1theoretically and experimentally (see Fig. 19).

The logic functions in the 1/1.5 divider cell are all imple-mented with the source-coupled-logic (SCL) configuration.

Fig. 4. Illustration of fractional spurs. (a) Frequency divider with step size =1. (b) Frequency divider with step size = 0:5 and input duty cycle is 50%.(c) Frequency divider with step size = 0:5 and input duty cycle is not 50%.

Fig. 5. Schematic of the combined SCL AND-latch.

Since SCL has the properties of keeping FETs biased in satura-tion region, it is more suitable for high frequency operation. Inorder to further reduce the propagation delay, the AND gates inthe 1/1.5 divider cell are merged into the latches. The schematicof the combined AND-latch is shown in Fig. 5 [25], where the


Fig. 6. Schematic of the programmable frequency divider.

transistors’ widths are labeled and the transistors’ lengths areall 0.18 m. The post-layout simulations show the 1/1.5 dividercell using the combined AND-latch can work over 4.6 GHz,whereas with AND gates and latches separated, the 1/1.5 di-vider cell can only operate under 3.5 GHz. However, the outputDC level of the SCL AND-latch in cascode configuration willbe higher than that of a single SCL latch and thus it is a commonpractice to use a level shifter. In our work, no level shifter isadded here in order to save power consumption. Instead, theDC input level of the multiplexer is designed intentionally to behigh enough so that the multiplexer can operate properly withthe SCL AND-latch. It is found experimentally (see Fig. 18)that this divider cell can function well over all process/tem-perature corners, albeit modifications of biasing conditions arenecessary when is increased. (The bias voltage can bechanged by varying the off-chip biasing resistor.)

C. Programmable Frequency Divider

The programmable divider is shown in Fig. 6 and is similarto the divider proposed in [25]. It consists of a 1/1.5 divider cellfollowed by eight divide-by-2/3 stages and a control circuit (in-cluding a MUX, a decoder, and three OR gates) that can effec-tively shorten the length of the divider thereby extending therange of the divider. In this work, with a 2-bit modulus extensionsignal, the modulus range can be extended to 32 511.5 with astep size of 0.5. Fig. 7 shows the output waveforms of the 1/1.5divider cell comparing to a typical 2/3 divider cell when they areconnected to a chain of 2/3 divider cells in a programmable fre-quency divider. Note that all the voltage signals shown in Fig. 7are in the differential mode. Shown in Fig. 7(a), when the feed-back control signal FB_CTRL is high, the output signal Fout1of the 1/1.5 divider cell is delayed by half period of the inputsignal Fin, while in Fig. 7(b), Fout1 of the 2/3 divider cell is de-layed by one period of the input signal.

To lower the power dissipation, only the first three bits (one1/1.5 divider cell and two 2/3 divider cells) of the programmablefrequency divider are realized with SCL configuration, whereas

the remaining six bits are implemented in CMOS logic and syn-thesized by digital building blocks.

D. Reduced Modulator With a Modulus Combiner

A 24-bit digital third-order modulator is adopted to gen-erate the pseudo-random number bit stream. Cooperating withthe proposed 1/1.5 divider cell, the modulator can producethe output bit stream with an average between 0 and 0.5 so thatthe step size of the frequency divider is . With a ref-erence frequency of 33 MHz, the resulting frequency resolutionof the frequency synthesizer is MHz Hz.

In this work, a reduced modulator adopted in commonpractice of commercial frequency synthesizer is used andits block diagram is shown in Fig. 8. A conventional digitalMASH3 modulator is a cascade of three accumulators ofthe same bit size. However, in practice, the second and thirdstages need not to have so many bits as the first stage does todeal with the quantization noise. Therefore, we can truncatethe second and third stages to 16 bits and 8 bits, respectively.The comparison of the reduced (the first accumulator is 24bits while the second and third accumulators are 16 bits and8 bits, respectively) and conventional (the second and thirdaccumulators are not truncated, i.e. all the three accumulatorsare 24 bits) modulators using the simulation results isshown in Fig. 9, which indicates that the performance of thereduced modulator is not degraded, yet 1/3 chip area and1/3 power consumption of the modulator can be saved.Note that the 1/3 hardware is not redundant. Deliberate removalof it will add error. However, experimentally we found that theerror is so small that it does not degrade the quantization noise.

To verify that the reduction of the quantization level can in-deed suppress the quantization noise, a modulus combiner thatcan change the quantization level of the frequency divider isdesigned. In a typical fractionalfrequency synthesizer,the modulation bits generated by the modulator are simplysummed up with the integer modulus to control the divisionratio of the frequency divider. However, in our system, if the


Fig. 7. Simulation results of the programmable frequency divider. (a) Output waveforms of the 1/1.5 divider cell. (b) Output waveforms of the 2/3 dividercell.

modulation bits are added with the integer modulus, the quan-tization level will be 0.5, which implies that we still need afunction block that can multiply the quantization level by 2, orequivalently, shift the modulation bits by 1 divider cell, to ex-amine the effect of the step size of on phase noise. For this

purpose, a modulus combiner that can shift the modulated bitsof the frequency divider is designed. The modulated bits can bechosen to be divider cell 1, 2, and 3 quantization level ,divider cell 2, 3, and 4 quantization level , divider cell 3,4, and 5 quantization level , or divider cell 4, 5, and


Fig. 8. Block diagram of the reduced �� modulator.

Fig. 9. Simulated phase noise of the reduced and conventional ��modulator.

6 quantization level . Accordingly, we can compare thephase noises with different quantization levels in the same chip.

E. VCO

Fig. 10 depicts the schematic of the LC-VCO. The core of thedifferential oscillator is formed by two complementary nMOSand pMOS devices for generating the negative transconductanceand attached to the LC tank of the VCO. Thetank consists of a differential high- (18 at 3 GHz) inductor,which is a fully symmetric spiral inductor designed for differ-ential excitation [27], and two pMOS varactors. To have a widetuning range and a small VCO gain [28], a 3-bit binary weightedcapacitors array is connected to the LC tank for coarse tuning.

Fig. 10. Schematic of the VCO.

Fig. 11. Transfer curves of the VCO.


Fig. 12. Schematic of the charge pump.

Because of their high quality factors, metal–insulator–metal(MIM) capacitors are chosen to form the capacitors array,and the capacitances are fF, fF, and

fF, respectively. To have the same quality factor foreach branch in the array, the sizes of the nMOS switches are alsoscaled as : : 1:2:4. Fig. 11 shows the VCO tuningcurves, where the VCO gain is approximately 100 MHz/V.

F. PFD, Charge Pump, and Loop Filter (LPF)

The PFD adopted in this frequency synthesizer is a tradi-tional tri-state PFD [29]. The schematic of the charge pump isillustrated in Fig. 12. Switches – are put at the sourcesof current mirrors to improve the switching speed and keepthe switching noise low [4]. The output current sources areformed by cascaded transistors ( – ) to increase outputimpedance and the control bit and can be programmedto have three different output currents. The transistor size ratioof these three branches is 1:3:4 and the corresponding outputcurrents can be 100 A, 400 A, and 800 A, respectively.The variable charge-pump current provides an alternative wayto change the loop bandwidth of the PLL.

A third-order off-chip passive loop filter is used as shown inFig. 13. The design parameters are as follows: pF,

pF, pF, k , and k .Given that the VCO gain is 100 MHz/V, the divider modulus isaround 85, and the charge pump current is 400 A, the resultingPLL bandwidth is approximately 200 kHz.

IV. EXPERIMENTAL RESULTS

The proposed frequency synthesizer was implemented in a0.18- m CMOS process. The microphotograph of the chip is

Fig. 13. Schematic of the loop filter and the design parameters.

shown in Fig. 14. The die area is 1.23 mm 0.83 mm (1 mm )excluding the measurement pads. The supply voltage is 2.3 Vfor VCO (The VCO does not oscillate below 2.3 V) and 2 V forthe other circuits and the total power consumption is 47.8 mW.All control signals are supplied through the three-wire serialinterface, and the reference frequency used is 33 MHz.

The measured phase noises at the same carrier fre-quency of 2813 MHz with quantization level andquantization level are shown in Fig. 15. For a frac-tional- frequency synthesizer, the out-of-band phase noise


Fig. 14. Microphotograph of the frequency synthesizer.

Fig. 15. Measured phase noise profiles with the same loop bandwidth.

is dominated either by the VCO or by the modulator[6]. According to our measurement results, the phase noisesof the free-running VCO are 129 dBc/Hz at 1 MHz offsetand 142 dBc/Hz at 4 MHz offset, whereas in Fig. 15 thephase noises are 124 dBc/Hz and 135 dBc/Hz at 1 MHzand 4 MHz offset (with quantization level ). Thus, theout-of-band phase noise is now dominated by the mod-ulator. Clearly from Fig. 15, with the help of the proposed1/1.5 divider cell, the out-of-band phase noise contributed bythe modulator is indeed reduced by 6 dB (from 129 to

135 dBc/Hz at 4 MHz offset), consistent with the theoreticalprediction. The 6 dB phase noise reduction effectively allowsus to design this synthesizer with a wider loop bandwidth. Toverify this, we adjust the loop bandwidth so that the out-of-bandphase noise with quantization level is the same as that withquantization level . Fig. 16 shows the experimental result.When the out-of-band phase noises are the same in both quan-tization levels, the 1/1.5 divider widens the loop bandwidth.

As we mentioned in Section III, the modulus combiner canchange the quantization level among 0.5, 1, 2, and 4. The mea-

Fig. 16. Measured phase noise profiles with the same out-of-band phase noise.

Fig. 17. Measurement results of phase noises with different quantization levels.

surement results of phase noises with these four quantizationlevels are shown in Fig. 17. It can be observed that the fourcurves have the same in-band phase noise (except for the onewith quantization level , whose quantization noise is toohigh to be suppressed below the in-band phase noise floor.),whereas the out-of-band phase noise is 6 dB higher as the quan-tization level is doubled. From these experimental results, weknow that when a fixed modulus prescaler is used in front of theprogrammable divider, the quantization level is increased andhence the quantization noise grows in proportion to the constantmodulus.

The performances over different temperature/chips/supplyvoltages are also tested. The chip was measured from 0 C to100 C and the measurement results are shown in Fig. 18(a). Itcan be observed that the in-band phase noise grows as temper-ature increases, but the out-of-band phase noise can still have a6 dB improvement after the quantization level is halved. Noticethat when the temperature is higher than 75 C, the out-of-bandphase noise is dominated by the VCO, as a result, the improve-


Fig. 18. (a) Measured phase noises at different temperatures. (b) Measuredphase noises for 10 chips.

ment is smaller than 6 dB. Fig. 18(b) shows the performance often different chips measured with quantization level . Thein-band phase noise varies from 105 dBc/Hz to 93 dBc/Hz at10 kHz offset and the out-of-band phase noise has a variation of5 dB, while the reduction of the quantization level can still havea 6 dB improvement. (The curves with quantization levelare not shown for clarity.) The frequency synthesizer was alsoevaluated at different power supply voltages ranging from 2 Vto 3 V (2.3 V to 3 V for VCO). The increment in supply voltagedoes not change the improved amount of the phase noise out ofthe loop bandwidth, but increases the power consumption from47.8 mW to 112 mW.

Fig. 19 shows the measured fractional spurs of the frequencysynthesizer. (Since the duty cycle of the VCO output is notperfectly 50%, the fractional spurs still locate at the fractionalfrequency as has been explained in Section III-B and Fig. 4.)In Fig. 19, the x-axis represents the fractional part setting.For example, 16 means the fractional part is 16/128, and thusfrom Fig. 19, the fractional spurs locates at 4.125 MHz

Fig. 19. Measurement results of fractional spurs.

TABLE IPERFORMANCE SUMMARY

33 MHz offset from the carrier frequencyare 74 dBc. When the fractional frequency is larger than6.18 MHz, the fractional spurs are smaller than the noise floorand cannot be measured. That is why the data are only collectedto 24/128. The experimental results are summarized in Table I.

V. CONCLUSION

In this paper, a quantization noise suppression technique forfractional- frequency synthesizers is presented and ver-

ified in 0.18- m CMOS technology. The experimental results


show the out-of-band phase noise contributed by the mod-ulator is reduced by 6 dB in the situation where the out-of-bandphase is dominated by the quantization noise. As out-of-bandphase noise reduced, a higher loop bandwidth can be used. Themeasurement results show 100 dBc/Hz in-band phase noisewithin the loop bandwidth of 200 kHz, and 124 dBc/Hz and

144 dBc/Hz out-of-band phase noise at 1 MHz and 10 MHzoffset frequency. The lock time is less than 10 s.

ACKNOWLEDGMENT

The authors would like to thank the National Chip Implemen-tation Center for IC fabrication, and the National Nano-DeviceLaboratory (NDL) for measurement support. Helpful discus-sions from Dr. Guo-Wei Huang at NDL and Prof. Hung-WeiChiu at National Taipei University of Technology are alsogreatly appreciated.

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Yu-Che Yang was born in Taipei, Taiwan, R.O.C, in1980. He received the B.S. degree in electrical en-gineering from National Taiwan University, Taipei,Taiwan, in 2002, where he is currently working to-ward the Ph.D. degree in electronic engineering.

His research interests include frequency syn-thesizers, mixed-signal integrated circuits, andradio-frequency integrated circuits for wirelesscommunications.

Shih-An Yu was born in Taipei, Taiwan, R.O.C., in1976. He received the B.S. and M.S. degrees in elec-trical engineering from National Taiwan University,Taipei, Taiwan, in 1999 and 2001, respectively.

During 2001 to 2003, he worked on frequencysynthesizers and other mixed-mode/RF systemsfor mobile phone and WLAN applications in VIAtechnology. During 2003 to 2005, he worked onbiosensor networks in several research projects heldby National Taiwan University and the government.He is currently pursuing the Ph.D. degree at Co-

lumbia University, New York, and collaborating with Bell Labs. His currentresearch interests are low-voltage, low-power, and high-speed systems.


Yu-Hsuan Liu was born in Kaohsiung, Taiwan,R.O.C., in 1981. She received the B.S. and M.S.degrees in electrical engineering from NationalTaiwan University, Taipei, Taiwan, in 2003 and2005, respectively.

She currently works at Realtek SemiconductorCorporation as an R&D Engineer. Her researchinterests include RF systems and RFIC design forwireless communication systems.

Tao Wang was born in Taipei, Taiwan, R.O.C., in1980. He received the B.S. degree from Chang GungUniversity, Taoyuan, Taiwan, in 2002, and the M.S.degree from National Taiwan University, Taipei,Taiwan, in 2004, both in electronics engineering, andis currently working toward the Ph.D. degree in elec-tronics engineering at National Taiwan University.

His research interests are in the areas of radio-fre-quency integrated circuits and monolithic microwaveintegrated circuits.

Shey-Shi Lu (S’89–M’91–SM’99) received the B.S.degree from National Taiwan University, Taiwan,R.O.C., in 1985, the M.S. degree from CornellUniversity, Ithaca, NY, in 1988, and the Ph.D. degreefrom the University of Minnesota at Minneapolis-St.Paul in 1991, all in electrical engineering.

He joined the Department of Electrical Engi-neering, National Taiwan University, in August 1991as an Associate Professor and was promoted to fullProfessor in 1995. His current research interests arein the areas of radio-frequency integrated circuits

(RFIC)/monolithic microwave integrated circuits (MMIC) and MEMS-RFelectronics.

2500 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11 ... · Fractional-N Frequency...

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