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Chapter 7

Hardware Description Language (HDL)

By Taweesak Reungpeerakul

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Contents

Introduction Hierarchical Modeling Concepts Basic Concepts Modules and Ports Gate-Level Modeling Dataflow Modeling Behavioral Modeling

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7.1 Introduction

HDL: a standard language described digital circuits

Model the concurrency of processes found in hardware elements

Two popular types: VHDL and Verilog HDL

No need to manually place gates to build digital circuits

Circuits designed in HDL in order to describe function and data flow

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Typical Design Flow

Production-readyMasks

Design SpecificationDesign Specification1

Behavioral DescriptionBehavioral Description2

RTL Description (HDL)RTL Description (HDL)3

SimulationSimulation4

Design IntegrationDesign Integration5

Logic synthesisLogic synthesis6

Gate-level NetlistGate-level Netlist7

Logical VerificationLogical Verification8

Auto Place & RouteAuto Place & Route9

Physical LayoutPhysical Layout10

Layout VerificationLayout Verification11

ImplementationImplementation12

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Importance of HDLs

Designs described at abstract level Cut down design cycle time Analogous to computer

programming(easy to develop and debug circuits)

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Popularity of Verilog HDLs Easy to learn and to use Hardware model defined in terms of

switches, gates, RTL, or behavior code

Several tools support Verilog Libraries provided for postlogic

synthesis simulation Allow the users to write custom C

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7.2 Hierarchical Modeling Concepts

Design Methodology 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example

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Design Methodology Two types: top-down and bottom-up Top-down:

Top-level Sub-blocks

• Leaf Cells• …• Leaf Cells (that cannot further be divided)

Bottom-up: build from available blocks and use them for higher-level blocks until top-level

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Top-down Design Methodology

Top-down

Bottom-up

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4-bit Ripple Carry Counter

Counter made up from 4 negedge T_FF

T_FF made up from negedge D_FF and inverters

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Design Heirachy

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Modulesmodule <module_name> (<module_terminal

list>);…<module_terminal >…endmodule module T_FF (q, clock, reset);

…<functionality of T_flipflop >…endmodule

Typical module

T_flipflop

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Module Instantiation

module ripple_carry_counter (q, clk, reset);

output [3:0] q; input clk, reset;

T_FF tff0 (q[0], clk, reset);T_FF tff1 (q[1], q[0], reset);T_FF tff2 (q[2], q[1], reset);T_FF tff3 (q[3], q[2], reset);

endmodule

module T_FF (q, clk, reset);output q;input clk, reset;wire d;

D_FF dff0 (q, clk, reset);not n1 (d,q);

endmodule

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Module Instantiation (2)module D_FF (q, d, clk, reset);

output q; input d, clk, reset;reg q;

always @(posedge reset or negedge clk)if (reset)

q = 1’b0;else

q = d;

endmodule

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Components of a Simulation

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Stimulus Block and Output Waveforms

module stimulus;reg clk, reset;wire [3:0] q;

Ripple_carry_counter r1 (q, clk, reset);

initial clk = 1’b0;

qlways #5 clk = ~clk;

initialbegin

reset = 1’b1;#15 reset = 1’b0;#180 reset = 1’b1;#10 reset = 1’b0;#20 $finish;

endinitial $monitor($time, “Output q =

%d”, q);

endmodule

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Output of the Simulation

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7.3 Basic Concepts

Lexical Conventions Data Types System Tasks and Compiler Directives

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Lexical Conventions Whitespace

\b, \t, \n Comments

// ข้�อความ 1 บรรทั�ด /* ข้�อความมากกว�า 1 บรรทั�ด */

Operatorsa = ~ b; // unarya = b && c; // binarya = b ? c : d; // ternary

Number<size>’<format><number>Legal format: ’d, ’h, ’b, ’oEx. 4’b1011, 8’h9cx is unknown; 6’hx z is high impedance-7’d3: 8-bit of 2’s of 3

String“Hello Verilog” // string

Appendix CList of Keywords, System

Tasks

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Data Types Value Level

0, 1, x, z Net

wire: most declaration Register

reg Vectors

[high#:low#] หร�อ [low#,high#]เช่�น reg [7:0] busA;

Integer, Real, Timeinteger, real, time

ArraysFor reg, integer, time, and

vector register Parameters

parameter port_id = 5; // constant

StringStored in reg เช่�นReg [8*18:1] string_value;

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System Tasks and Compiler Directives

System Tasks$<keyword>

$displayusage: $display(p1,p2,…,pn);

$monitorusage: $monitor(p1,p2,

…,pn);usage: $monitoron;usage: $monitoroff;

$stopusage: $stop;

$finishusage: $finish;

Compiler Directives‘<keyword>

‘define‘define SIZE 32

‘include‘include header.v

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7.4 Modules and Ports

Modules Ports

List of Ports Port Declaration Port Connection Rules Connecting Ports to External Signals

Hierarchical Names

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Modules

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Components of a Modulemodule SR_latch(Q, Qbar,

Sbar, Rbar);output Q, Qbar;input Sbar, Rbar;nand n1(Q, Sbar, Qbar);nand n2(Qbar, Rbar, Q);endmodule

module top;wire q, qbar;reg set, reset;

SR_latch m1(q, qbar, ~set, ~reset);

initialbegin $monitor($time, “set = %b,

reset=%b, q=%b\n”, set,reset,q);

set = 0; reset = 0; #5 reset =1; #5 reset =0; #5 set =1;endendmodule

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Ports List of Ports Port Declaration

input output inout //bidirection

module fulladd4(sum, c_out, a, b, c_in);

module fulladd4(sum, c_out, a, b, c_in);output [3:0] sum;output c_cout;input [3:0] a, b;input c_in;…<module internal>…endmodule

Note: If output ports hold their value, they must be declared as reg.

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Ports (2) Port Connection

Rules Connecting Ports

to External Signals

Two ways: Order list

Name

module fulladd4(sum, c_out, a, b, c_in);output [3:0] sum; output c_cout;input [3:0] a, b; input c_in;…endmodule

fulladd4 byorder(SUM, C_OUT,A, B, C_IN);

fulladd4 byorder(.a(A),.b(B), .c_in(C_IN), .sum(SUM), .c_out(C_OUT));

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7.5 Gate-level Modeling

Gate Types And/Or Gates Buf/Not Gates Example

Gate Delays Rise, Fall, and Turn-off Delays Min/Typ/Max Values Example

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Gate Types Gate Types and or xor nand nor

xnorExample:

Buf/Not Gates buf

Not

bufif/notif

and a1 (out, i1, i2);

buf b1 (out, in);

not n1 (out, in);

notif n2 (out, in, ctrl);

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Example

module f_add (sum, c_out, a,b,c_in);

output sum, c_out;input a, b, c_in;wire s1,s2,c1;

xor n1 (s1, a, b);and n2 (c1, a, b);xor n3 (sum, s1, c_in);and n4 (s2, s1, c_in);or n5 (c_out, s2, c1);endmodule

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Gate Delays Rise, Fall, and Turn-off

and #(5) a1(out,i1,i2);//delay of 5 for all transitions

and #(4,6) a2(out,i1,i2);//rise = 4, fall =6

bufif0 #(3,4,5) b1(out,i1,ctrl);//rise = 3, fall =4, turn-off =5

Min/Typ/Max Valuesand #(4:5:6) a1(out,i1,i2);// min=4, typ=5, max=6

and #(3:4:5, 5:6:7) a2(out,i1,i2);

// min: rise=3, fall=5, t-off=min(3,5)

// typ: rise=4, fall=6, t-off=min(4,6)

// max: rise=5, fall=7, t-off=min(5,7)

and #(2:3:4, 3:4:5, 4:5:6) a3(out,i1,i2);

// min: rise=2, fall=3, t-off=4// typ: rise=3, fall=4, t-off=5// max: rise=4, fall=5, t-off=6

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Example

module D (out, a, b, c);

output out;input a, b, c;wire e;

and #(5) a1 (e, a, b);or #(4) o1 (out, e, c);

endmodule

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7.6 Dataflow Modeling

Continuous Assignments Delays Expressions, Operators, and Operands Operator Types Examples

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Dataflow Modeling (2) Continuous

Assignmentsassign out = i1 & i2;assign addr[7:0] =

addr1[7:0]^ addr2[7:0];assign {c_out, sum[3:0]} =

a[3:0] + b[3:0] +c_in;

Delaysassign #10 out = i1 & i2;

Expressionsเช่�น a ^ b, i1 + i2

Operandsเช่�น count = count + 1; out1 = r1 ^ r2;

Operatorsเช่�น d1 && d2;

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Operator Types Arithmetic * / + - % Logical ! && || Relational > < >= <= Equality == != === !== Bitwise ~ & | ^ ^~

Reduction & ~& | ~& ^ ^~ Shift >> << Concatenation { } Replication { { } } Conditional ? :

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Examples

Multiplexer Full Adder Ripple Counter

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7.7 Behavioral Modeling

Structured Procedures Procedural Assignments Timing Controls Conditional Statements Multiway Branching Loops Sequential and Parallel Blocks

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Structured Procedures initial Statementmodule stimulus;reg a, b;initial begin #5 a = 1’b1; #15 b = 1’b0;endendmodule

always Statementmodule clock_gen;reg clk;initial clk = 1’b0;always #5 clk = ~clk;initial #1000 $finish;endmodule

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Procedural Assignments Blocking Assignmentreg x, y, z;reg [7:0] reg_a, reg_b;integer count;initial begin x=0; y=1; z=1; count =0; reg_a = 8’b0; reg_b = reg_a; #5 reg_a[2] = 1’b1; #10 reg_b[6:4] = {x,y,z} count = count+1;end

Nonblocking Assignment

reg x, y, z;reg [7:0] reg_a, reg_b;integer count;initial begin x=0; y=1; z=1; count =0; reg_a = 8’b0; reg_b = reg_a; #5 reg_a[2] <= 1’b1; #10 reg_b[6:4] <= {x,y,z} count <= count+1;end

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Timing Controls Regular Delay #5 a = 1’b1;

Intra-assign Delay a = #5 b + c;

Event-based @(clk) a = c; @(posedge clk) a = c; q = @(negedge clk) c;

Level-sensitivealways wait (en) #5 c = c+1;

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Conditional Statements if… else…

if (<exp>) true_statement;

if (<exp>) true_statement;else false_statement;

if (<exp1>) true_statement_1;

else if (<exp2>) true_statement2;

else default_statement;

Examplesif (!a) b = c;

if (a<0) b = c;else b = d;

if (a>0) a = b;else if (a<0) a = b+c;else $display(“a=0”);

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Multiway Branching

case (<exp>) alt1: statement1; alt2: statement2; …. default:

defult_statement;endcase

case (ctrl) 2’d0 : y = x+z; 2’d1 : y = x-z; 2’d2 : y = x*z; default :

$display(“error”);endcase

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Loops while Loopinteger c;initial begin c = 0; while (c<128) begin $display (“count =%d”, c); c = c +1; endend

for Loopinteger c;initial for ( c=0; c<128; c= c+1) $display (“count =%d”,

c);

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Sequential and Parallel Blocks Sequential Blocksreg a,c;reg [1:0] x, y;initialbegin a = 1’b0; #5 c = 1’b1; #10 x = {a, c}; #20 y = {c, a};end

Parallel Blocksreg a,c;reg [1:0] x, y;initialfork a = 1’b0; #5 c = 1’b1; #10 x = {a, c}; #20 y = {c, a};join

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Reference

S. Palnitkar, Verilog HDL: a Guid to Digital and Synthesis, SunSoft Press, 1996.