2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist...
description
Transcript of 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist...
![Page 1: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/1.jpg)
SDV SMU Dynamic Verilog Visualization2
Ralph Marczynski
Peter-Michael Seidel
Southern Methodist University
Dallas, TX 75275Computer Science and
Engineering
![Page 2: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/2.jpg)
SDV SMU Dynamic Verilog Visualization2
HDLs
Schematic Entry
Waveform
Text
![Page 3: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/3.jpg)
SDV SMU Dynamic Verilog Visualization2
HDL Design
SDV2
Schematic Visualization
Text BasedValues/Time
Dynamic Signal Propagation
Simulation
Structure Functionality
![Page 4: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/4.jpg)
SDV SMU Dynamic Verilog Visualization2
•Syntax-Error Free Verilog Hardware Description
•Structural, Behavioral, or Mixed
•Physically Feasible Design
SDV 2
![Page 5: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/5.jpg)
SDV SMU Dynamic Verilog Visualization2
Visualization Configuration
•Module Selection
•Module Placement / Geometry
•Port Orientation
•Lines Customization
SDV 2
![Page 6: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/6.jpg)
SDV SMU Dynamic Verilog Visualization2
Veriwell 2.3 Command Line Simulator
Visualization
Signal Propagation
Text Output
Visualization and Animation Front-End
Visualization Configuration
SDV 2
![Page 7: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/7.jpg)
SDV SMU Dynamic Verilog Visualization2
SIMULATION APPROACH
2 Bit Ripple Carry Adder
Independent Atomic Module Simulations with Dynamic Variable Initialization
vs.
Complete System Simulation
![Page 8: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/8.jpg)
SDV SMU Dynamic Verilog Visualization2
SIMULATION APPROACH
2 Bit Ripple Carry Adder
Independent Atomic Module Simulations with Dynamic Variable Initialization
vs.
Complete System Simulation
![Page 9: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/9.jpg)
SDV SMU Dynamic Verilog Visualization2
SIMULATION APPROACH
2 Bit Ripple Carry Adder
Independent Atomic Module Simulations with Dynamic Variable Initialization
vs.
Complete System Simulation
![Page 10: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/10.jpg)
SDV SMU Dynamic Verilog Visualization2
SIMULATION APPROACH
2 Bit Ripple Carry Adder
Independent Atomic Module Simulations with Dynamic Variable Initialization
vs.
Complete System Simulation
![Page 11: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/11.jpg)
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
{Direct ConnectionContinuous/Procedural Assignment
Function/Task
Primitive/User Defined Primitive
Output Input Dependencies
Simulation Order
Availability of Variables at TimeOf Independent Module Simulation
Determine
Guarantees
![Page 12: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/12.jpg)
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER EXTRACTION
2 Step Extraction Procedure
1. Local Dependency Dependency Among Instantiations in a
Defined Module
2. Global Dependency Dependency Considering The Entire System
Local Input/Output Instantiation Dependency
Top-Level
![Page 13: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/13.jpg)
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
In-Order Traversal Generates the Simulation
Order
1. During Visit- inputs to the Instantiation are known
Local Input/Output Instantiation Dependency
Top-Level
![Page 14: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/14.jpg)
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
Local Input/Output Instantiation Dependency
Top-Level2. Return Visit- all inputs from the module’s instantiations are known
![Page 15: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/15.jpg)
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
Local Input/Output Instantiation Dependency
Top-Level2. Return Visit- all inputs from the module’s instantiations are known
3. Final Return - all Values within the Module are resolved.
![Page 16: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/16.jpg)
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
Local Input/Output Instantiation Dependency
Top-Level 121
n
iiIS
S – Total Simulations/time unit
I – Total instantiations within module i
![Page 17: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/17.jpg)
SDV SMU Dynamic Verilog Visualization2
VARIABLE INTIALIZATION AND EVENT EXTRACTION
Variable Initialization
Event Extraction
Dynamically Created Top Level Modules
.V
.V
Event Monitoring always@
Statements
![Page 18: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/18.jpg)
SDV SMU Dynamic Verilog Visualization2
VARIABLE INTIALIZATION AND EVENT EXTRACTION
Variable Initialization
Event Extraction
Dynamically Created Top Level Modules
.V
.V
t-1t
value
value
initial begin
<assignments>
#1
<assignments>
end
t (event) = t (SDVV) + t (Veriwell) -1
![Page 19: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/19.jpg)
SDV SMU Dynamic Verilog Visualization2
VARIABLE INTIALIZATION AND EVENT EXTRACTION
Variable Initialization
Event Extraction
.V
.V
t (event) = t (SDVV) + t (Veriwell) -1
Static Module Definition
Veriwell.V
.log
Events
Log File
![Page 20: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/20.jpg)
SDV SMU Dynamic Verilog Visualization2
• OPTIMIZATIONOPTIMIZATION
• Number Of Simulations / time unit
• Data Structures• Searching/Sorting
• INTERFACE
• Graphics Enhancement• Visualization
Configuration• Text Editor• Error Detection
![Page 21: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/21.jpg)
SDV SMU Dynamic Verilog Visualization2
LIBRARY
Extension of Verilog HDL for Animation of Dynamically Re-configurable Systems
Static Module
Definitions
DEMO
![Page 22: 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist University Dallas,](https://reader035.fdocuments.us/reader035/viewer/2022062401/5a4d1b7b7f8b9ab0599b918b/html5/thumbnails/22.jpg)
SDV SMU Dynamic Verilog Visualization2
SDV Homepage www.engr.smu.edu/~ralphm/sdvv
Ralph [email protected]
Peter-Michael [email protected]
2
Marczynski’s Homepage www.engr.smu.edu/~ralphm
THANK YOU