2+ M.tech Raghav Resume
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1 RAGHAVENDRA S. SOLANKY Add: C-106, Gamma-1, Mobile: +91-9810549508, 9958279769 Greater Noida -302022 E-mail: [email protected] U.P (India) [email protected] OBJECTIVE Interested in working as a member of a motivated development team involved in challenging projects, where I can exercise my existing skill set to the best and also gather new skills to reinforce my knowledge. EXPERIENCE SUMMARY Having 2.5 years experience as a Design Engineer Having 1 year experience as a Design Engineer in ST Microelectronics. Having 1.5 year experience as a Design engineer in RF Silicon Pvt. Ltd, Noida, India WORKING EXPERIENCE Project-1 Post Silicon Validation on DPhy and MPhy. Tools : PARBert, LAPG, DSA, Source Generator, Function Generator etc. My Job: Post Silicon Validation on DPhy & MPhy and DFT. Description DPhy and MPhy are a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. It is targeted to be suitable for multiple protocols, including UniProSM and DigRFSM v4, and for a wide range of applications. Project-2 SPI-AHB-DMA IP Verification Languages : System Verilog / Verilog Tools : Synopsis (VCS, CMVIEW) Role : Design Engineer My Job: Full verification of SPI-AHB-DMA IP in Verilog and System Verilog. Description DMA controller has two channels to perform read/write operations between the memory and customizable interface (SPI, USB, UART etc). The DMA can perform only single data transfers (no burst transactions) across the AHB bus. Each DMA channel enables movement of data from a source AHB address to the IP or IP to the destination AHB address, for a given programmed count. It can be programmed using its AHB slave interface by the system (ARC) processor. The DMA’s master controller is initially inactive but comes to active mode after ARC programs a set of control registers
Transcript of 2+ M.tech Raghav Resume
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RAGHAVENDRA S. SOLANKY
Add: C-106, Gamma-1, Mobile: +91-9810549508, 9958279769 Greater Noida -302022 E-mail: [email protected] U.P (India) [email protected] OBJECTIVE Interested in working as a member of a motivated development team involved in challenging projects, where I can exercise my existing skill set to the best and also gather new skills to reinforce my knowledge. EXPERIENCE SUMMARY Having 2.5 years experience as a Design Engineer
Having 1 year experience as a Design Engineer in ST Microelectronics. Having 1.5 year experience as a Design engineer in RF Silicon Pvt. Ltd, Noida, India
WORKING EXPERIENCE Project-1 Post Silicon Validation on DPhy and MPhy. Tools : PARBert, LAPG, DSA, Source Generator, Function Generator etc. My Job: Post Silicon Validation on DPhy & MPhy and DFT. Description
DPhy and MPhy are a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. It is targeted to be suitable for multiple protocols, including UniProSM and DigRFSM v4, and for a wide range of applications.
Project-2 SPI-AHB-DMA IP Verification Languages : System Verilog / Verilog Tools : Synopsis (VCS, CMVIEW) Role : Design Engineer My Job: Full verification of SPI-AHB-DMA IP in Verilog and System Verilog. Description DMA controller has two channels to perform read/write operations between the memory and customizable interface (SPI, USB, UART etc). The DMA can perform only single data transfers (no burst transactions) across the AHB bus. Each DMA channel enables movement of data from a source AHB address to the IP or IP to the destination AHB address, for a given programmed count. It can be programmed using its AHB slave interface by the system (ARC) processor. The DMA’s master controller is initially inactive but comes to active mode after ARC programs a set of control registers
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Project-3 Bluetooth low energy (BTLE) Tools : Cadence (NCSIM). Language : VHDL, System Verilog, C. Role : Design Engineer
My Job : Full verification of HCI block in System Verilog. Description
BTLE is the first generation of low voltage and low power, fully integrated single-chip Bluetooth functionality. The design implements Bluetooth low energy functionality of controller and HCI. ACADEMIC PROJECTS Project-1: Design and Implementation of Reed Solomon Encoder/Decoder using
FPGA Project-2: Design & Implementation of FIFO 128 on FPGA. KEY COMPETENCIES & SKILLS SETS Languages System Verilog, Verilog, VHDL, LabView Protocols MPhy, DPhy, AMBA AHB, SPI. Technical Skills System Verilog, Verilog, Digital Design, FPGA EDUCATIONAL QUALIFICATIONS M.Tech (VLSI Design & CAD, 2007-09) from Thapar University Patiala.
EXTRA ACHIVEMENTS
GATE Qualified in 2007 (96 Percentile) President Award in The Bharat Scouts & Guides
PERSONAL INFORMATION
Name : Raghavendra S. Solanky
Date of Birth : 07th Dec. 1984
Father’s Name: Sh. Gajendra Singh
Nationality : Indian
Languages : Hindi, English
Interests : Yoga, Reading books, Listening devotional music
I hereby declare that the particulars given herein are true and complete to the best of my knowledge and belief. Date: 12/06/2012 Raghavendra S. Solanky Signature
