XII sekcija

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Kauno technologijos universitetas, KompiuteriStudentu g. 50 – 214c, 3028 Kaunas

{ekaza ; pakal ; valka ; zviron } @dsplab.ktu.lt

Šiandienos IT pagrindinis poreikis yra apdorreikalingos realaus laiko sistemos -

cijai reikalingos

nepritaikytose dirbti re–

1Nedaugelis prieštaraus, kad apie 80% šiuolaikini sistem

bendros paskirties (General Purpose Processor -sus

gijos sunaudojimo

2

algoritmo dalys r

FILTRAS

Adaptyvus Fi l t ras

F P G A

G P P

( a) (b)

Adaptyvus Fi l t ras

perprogramuojam -schema (Aplication Specific Integrated Circuit –

Egidijus Kazanavi K stutis Pakalniš388

3-

sukuriamas prototipas, kuris panaudojamas sistemos funkciniam modeliavimui.

4 Projektavimas ir realizacija

Apsk k=Σwk(i)xk-i;

k=yk-nk;

k+1(i)=wk(i) + 2uekxk-i;

parenkama lygiagretaus vykdymo, kadangi sistema turi tenkinti realaus laiko sistemos reikalavimus. Šios

Fi l t ravimas

Pakla idosapska iè iav imas

Koef ic ien tøperska iè iav imas

N u o s e k l u svykdymas

N u o s e k l u svykdymas

N u o s e k l u svykdymas

Lygiagre tusvykdymas

Lygiagre tusvykdymas

Lygiagre tusvykdymas

(a) (b) (c)

Filtravimas

Paklaidos apskai

389

5 Algoritmo funkcinis patikrinimas –

r jo parametrai. Paveiksle 4 pateikiami MATLAB modelio rezultatai.

4 pav. Funkcinio modeliavimo rezultatai

Kadangi filtravimo sistemos atliko funkcines spec

6

realizacija atlikta Xilinx firmos programuojamoje logikoje. Le

amos logikos

1

C slankaus kablelio

realizacija

HDL 8 bit

Realizavimo platforma PC PC PC PC FPGA FPGA 233 233 233 233 31 54

Vykdymo ciklai, *103 240000 110000 50000 50000 16 16 Vykdymo laikas, ms 1013.903 462.216 216.34 215.37 0.4937 0.2866 Santykinis vykdymo laikas, %

3535 1612 753 750 1.7 1

kiekis, CLB – – – – 4200 1330

Egidijus Kazanavi K stutis Pakalniš390

7 Išvados • •

kiekio.

•

•

[1] E.C. Ifeachor, B.W. Jervis. Digital Signal Processing. Addison Wesley, 1993.

[2] D.D. Gajski. Principles of Digital Design. Prentice-Hall.

[3] Microsoft MSDN Library.

[4] G. Iliev, N. Kasabov. Adaptive Filtering with Averaging in Noise Cancelation for Voise and Speech Recognition. University of Otago.

Summary

EVALUATION OF HETEROGENEOUS ADAPTIVE SYSTEM The main problem today’s IT – information processing. This task can be solved only real time systems, based on heterogeneous systems. As an example for this project was chosen adaptive filtering. The main task of this project is to design, implement and evaluate heterogeneous adaptive system.

DESIGN AND IMPLEMENTATION OF A DES ALGORITHM

Egidijus Kazanavicius, Kestutis Pakalniskis

Kaunas University of Technology, Computer Department, Signal Processing Laboratory, Studentu g. 50 – 214c, 3028 Kaunas

{ekaza ; pakal}@dsplab.ktu.lt

Abstract. Project was organized using OOA&D methodology and involves analysis, design, implementation and testing of DES algorithm for encryption/decryption in software and hardware. The main purpose of this project is to evaluate SW and HW solutions, development process, algorithm coding languages C and VHDL.

1 Introduction The main purpose of this project is to evaluate HW and SW solutions. The DES algorithm was chosen

as our example throughout the project. This project will involve design, implementation and test of the DES algorithm for encryption/decryption in C and VHDL. The VHDL design will be synthesised and downloaded into FPGA. The speed of C and VHDL implementation's will be compared. The VHDL implementation will be evaluated by area and speed performance. Project idea is shown in Figure 1.

Sof twareImplementat ion

in C

HardwareImplementat ion

in VHDL

Evaluat ion ofS W a n d H W

solut ions

DES A lgor i thm

Figure 1. Idea of the project

2 Data Encryption Encryption is the conversion of data into a form, called a cipher, that cannot be easily understood by

unauthorized people. Decryption is the process of converting encrypted data back into its original form, so it can be understood.

There are a many encryption algorithms and one of them is DES (Data Encryption Standard). DES is a widely used method of data encryption using a private (secret) key.

For each given message, the key is chosen at random from among this enormous number of keys. Like other private key cryptographic methods, both the sender and the receiver must know and use the same private key.

DES applies a 56-bit key to each 64-bit block of data. The process can run in several modes and involves 16 rounds or operations. Although this is considered strong encryption, many companies use triple DES, which applies three keys in succession. Triple DES uses 3 times more operations than DES. But triple DES has been proven much more secure than conventional DES, and is a good alternative for current designs.

3 System specifications

3.1 InterfaceSystem interface is the communication path between a system and the environment. The purpose during

the analysis and design is to make sure that the technical connections of described computerized system can be realized.

The system interface can be described in two levels:

• Logical,

• Physical.

Egidijus Kazanavicius, Kestutis Pakalniskis 392

Using these terms the logical level will describe information our system have to receive and what information it will have to send after processing of received data. This system has three actors: Input File, DES, Output File. DES as a kernel of the system receives data from Input File, encipher it and sends the result to Output File, as shown in Figure 2.

Input Fi leOutput

Fi leD E S

Figure 2. Logical interface model

Physical level will describe , how our system communicate, how it is connected with other computerized systems or devices, how it exchanges information with them. SW implementation system’sinterface composed of three actors: Input File , Computer, Output File. Look to the 0.The computer encipher plain text from input file it and send it to the output file, as shown in Figure 3.

Input Fi leOutput

Fi leComputer

Figure 3. Physical interface for software implementation

HW implementation system’s interface is composed of Input File, Computer, Memory on the board, FPGA on the board and Output File. Lets look to 0Computer reads plain text from Input File. Put it in memory and send to Board Memory. FPGA on the board enciphers and sends back to Board Memory, Computer and to Output File, as shown in Figure 4.

Input Fi leOutput

Fi leComputer

F P G A

Memory

RC 1000 PP Board

Figure 4. Physical interface for hardware implementation

3.2 ModulesThe DES algorithm includes three basic module types shown in Figure 5.

Switching wires based modules (Initial Permutation, Expansion Box, P Box, Final Permutation Permuted Choise1 and Choise2). The module S-Boxes computes output from the table of constant values. Bitwise xor operation for 48 and 32 bits. All operations are performed in bit data type level in DES algorithm.

LUT64 x 4

S B O Xpatternin ROM

(a) Permutation (b) S Boxes based LUT (c) Exclusive OR module

Figure 5.

Design and implementation of a DES algorithm 393

3.3 Estimation

3.4 Estimation of SW implementationSoftware implementation of DES algorithm are performed in C language. The PC is the platform for

implementation of algorithm.

All of the encryption system modules are operating with operands in bit level. C allows manipulation in bit level only with logical operations. Other operations like permutation can’t be performed because C has no bit type to representation. In this case was choisen 64 bits operand’s representation as string of 64 characters.

As mentioned above the encryption system has the logical interface, which reads and writes the data to the file. The physical interface communicates between files and PC memory. The SW estimation was done with 1000 execution times for more precise evaluation. Table 1 summarizes the absolute and relative timing of the basic design modules and total algorithm.

Conclusions on timing. Algorithm has an extra functions to manipulate with strings, which increases the execution time. The conversions necessary because C has no bit type data representation. The data representation as string calls a lot of time consumption for simple bitwise xor logic operation.

Table 1. SW timing evaluation

Module\ Timing Absolute timing, μs Relative timing, %Permute 1.741 – 23.950 0.1 – 2.0 Sbox 308.245 25.9 XOR 202.687 17.1 Total DES 1188.180 100.0

3.5 Estimation of HW implementationHardware implementation of DES algorithm are performed in VHDL language. The RC1000 PP board

based on Xilinx Virtex 1000 FPGA is the platform for implementation of algorithm.

Logical level of HW implementation interface is the same as SW. Data from file are sended to the core of the system and returned to the file. Physical interface has two parts:

Communication between PC and memory on the board. The communications between memory banks and PC are implemented in C. The RC1000-PP support software also provides a lot of macros for host support. There are used macros for request, release, read and write banks, read status, write control ports. Also are used some addition functions for opening RC1000PP card and downloading of the design to the FPGA by C using. This channel is based on DMA transfers. Satndard PCI interfase are used. The data transfer rate though this channel are aproximately 50 M samples. The timing analysis was performed using standad timeb.h hearder in C.

Communication between FPGA and memory on the board. The communications between FPGA and memory banks are implemented in FPGA. The RC1000-PP support software provides a lot of macros. In the module are used macros that requests and releases memory banks, reads and writes to memory banks, also read the control port and writes to status port. This module is called R/W. The estimation of this module is presented in table 2. This table also shows the estimation of basic modules of DES algorithm. For estimation of basic modules was necessary use R/W module. The permutation based module consumes the same amount of hardware, it shows that this module are only switching wires. Logical Sbox arrangement is 8x64x4. Physical Sbox module places 128x16x1 ROM cells. This module takes more gates, but they are for decoding of memory adreses. The module XOR shares HW resources for the xor operation with R/W module, because it takes the same amount of HW.

The table 3 shows timing analysis of the HW implementation. Processing rate for the basic modules are aproximatelly the same. This table also shows the max net delay. These delays a lot decreasing of processing rate. The delays ocures, because the FPGA is much more bigger, then this algorithm requares HW resources.

Table 2. HW resource evaluation

Module\ Area 4 input LUT’s Flip flops ROM’s Total gate R/W 37 0 0 830 Permute 37 0 0 830 Sbox 69 0 128x16x1 5310 XOR 37 0 0 830 Total DES s 745 479 128x16x1 12,734 Total DES p 729 383 128x16x1 11,870

Egidijus Kazanavicius, Kestutis Pakalniskis 394

Table 3. HW timing evaluation

Module\ Timing Max. Freq., MHz Max. net delay, nsR/W 40.783 9.433 Permute 45.157 10.937 Sbox 37.309 10.937 XOR 41.171 9.375 Total DES s 31.642 16.493 Total DES p 30.541 23.663

The whole design has two architectural implementationt for one round. The architecture called DES s executes all operations sequentialy. Other called DES p executes all operation inside one round parallel. The serial execution takes a little more HW, because it needs temporary registers.

4 Conclusions Technical aspect of project was to implement the DES algorithm, evaluate and analyse the achieved

results. Implemented two architectures:

• One round serial execution.

• One round parallel execution.

The system design using hardware description languages. There are two levels of the system descriptions:

• Structural level

• Behavioural level

C programming language provides only behavioural description of the algorithm. Behavioural synthesis is very useful in design of graphical co-processors, digital signal algorithms. But it not very suitable for well structured system design.

References [1] Data Encryption Standard (DES). FIPS PUB 46-2.

[2] Daniel D. Gajski. Principles of Digital Design.. Prentice-Hall.

[3] Handel-C Language Reference Manual. Embedded Solutions.

[4] RC1000-PP Software User Guide. Embedded Solutions.

[5] RC1000-PP Hardware Reference Manuel. Embedded Solutions.

[6] Virtex 2.5 V. Field Programmable Gate Array. Xilinx

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– 214c, 3028 Kaunas

ai

1

n

sistemoms.

taikomosios programos modelio sudarymui ir modeliavimui, bet nepalaiko detalaus taikomosios programos

Pol -projektavimas

s.

–PADE) – Delft Technologijos Universiteto, Informacijos

sResearch Laboratories, Eindhoven) [2]. Kita metodologija –

–(EESC Department, University of California at Berkeley) [3].

2 SPADE metodologija SPADE

PADE

program

atskleisti taikymo lygiagretumo ir bendravimo gal

blokai gali

–PADE

396

1 pav. SPADE

2.1 Taikymo modelio sudarymas

bendrauja per neriboto ilgio FIFO kanal

• tiek

• su valdymo konstrukcijomis, tokiomis kaip while ciklai ir if–then–else sakinius. Kahn’o modelyje daug

aprašytoje C/C++ programoje.

PADE

• generuoja taikymo lygyje.

•

• a

IDCT operacijai 8x8 matricos pavidalu.

utomatiškai, taikymo

2.2

paprastas. SPADE , funkcionavimo elgsena aprašyta taikymo ly

teisingas (generic building) . Kai

397

• (TDEUdu išlaikoma taikymo proceso vykdymo tvarka. TDEU turi

protokolu.

•

- -pirmas-aptarnautas (first-come-first-parametrizuoti. gaišties laikas

imas, ir perdavimo

2.3 Paskirstymas Vienas

• - - -to-one) pavidalo,

•

T D E U

I/F

T D E U

I/F

2 pav. T

398

3

3.1

skirtinguose skaidymo

���������

P 1 P 1

P 1 P 2 P 3

– driven) bendros – nukreipimo (dat – – procesoriaus blokuose.

(proceso vykdymo metu), arba nustatyti co –

lygio kalbos panaudojimas yra esminis reikalavimas efektyviai DSP greito – prototipo sudarymo aplinkai.

3.2 Metodologija Tyrimo metodol

parenkami PDA (Energija– –Plotas) makromodeliai kiekvienai komponentei. Makromodelis –

Algoritmas paskirstomas procesoriaus šerdyje (core) (3 etapas). Nustatoma kaip sprendinys atitinka

– atliekamas projekto padalinimas (4 ir 5

399

1 e tapas

2 e tapas

3 e tapas

4 e tapas

5 e tapas6 e tapas

3.3

s primityvas.

matavimus, fizikinio arba RTL lygio modeliav–

– priimtini kai kurie netikslumai. Be funkciniams modeliams, tokiems kaip atmintis, ALU, daugintuvai, ir t.t.. Efektyvaus perjungimo analitinio modelio talpa Cef

,2ddefFU VNCEnergija ××=

kur N –

sujungi

400

,int2

erddtinklasi

iINTER NVCEnergija ×⎟⎟⎠

⎞⎜⎜⎝

⎛×= ∑

⊆

kur Ninter – .–

P funkcija (naudojama N ir Ninter parametrams gauti), kuri parodo funkcin

4 Apibendrinimai SPADE

PADE metodologija atskiria

modeliai.

efektyviai,

[1] Joseph Buck, Soonhoi Ha, Edward A Lee, David G. Messerschitt. Ptolemy: A framework for simulating and prototyping heterogeneous systems. International Journal of Computer Simulation, Aug. 31 1992. Special issue on Simulation Software Development.

[2] Paul Lieverse, Pieter van der Wolf, Ed Deprettere, Kees Vissers. A Methodology for architecture exploration of heterogeneous signal processing systems. Proc.1999 IEEE Workshop on Signal Processing Systems (SiPS’99), 1999, 181-190.

[3] Marlene Wan, Yuji Ichikawa, David Lidsky, Jan Rabaey. An Energy Conscious Methodology for Early Design Exploration of Heterogeneous DSPS. Proceedings of the Custom Integrated Circuit Conference , Santa Clara, CA, USA, May 1998.

[4] Pieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei and Kees Vissers, ``An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology'', In Proc. 7-th Int. Workshop on Hardware/Software Codesign (CODES'99), Rome, Italy, May 3 - 5 1999.

[5] Marlene Wan, Hui Zhang, Varghese George, Martin Benes, Arthur Abnous, Vandana Prabhu, Jan Rabaey.Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System", Journal of VLSI Signal Processing, 2000.

Summary

A METHODOLOGIES FOR ARCHITECTURE EXPLORATION OF HETEROGENEOUS SIGNAL PROCESSING SYSTEMS Modern signal processing systems are increasingly becoming multi–functional systems that also have to support multiple standards. Such systems need design technology that helps designers to define such heterogeneous architectures starting from a set of target applications. A classical approach that departs from single application and iteratively pushes it through some transformational process towards a dedicated implementation architecture, is not suited for the design of programmable systems. In this paper are presented two methodologies mostly suited for architecture exploration of heterogeneous signal processing systems.

������������*(������������� �����–KLA ��*�����MATEMATINIS MODELIS

�+������������ �+��%�,� �+�����-

g. 50 –– LT.

-LT

alias galimybes kraujotakos sistemos

– arterinio spaudimo

-modelis.

temos

– arterinio SPB

modifikuojant ar papildant koeficientais gautais remiantis.

sistem -

D – išorinis skersmuo, d – vidinis skersmuo, S – sienel –σ1 – ašinis σ2 – tangentinis σ3 – radialinis

σ3

�2

σ1

σ1

σ3�3

S

Dd

[3]:

402

S

dpvid

⋅⋅

=22σ ; (1)

S

dpvid

⋅⋅

=41σ ; (2)

vidp−=3σ (3)

( );32-1 += (4)

μ - 0C < T < 400C μ = 0.36 ÷ 0.5. Bendra deformacija aprašoma dviem parametrais:

ε = ε0 + Δε; (5)

kur ε0 – Δε - de

;0

3

0

2

0

10 ⎟⎟⎠

⎞⎜⎜⎝

⎛+−=

EEE (6)

;11

0⎟⎟⎠

⎞⎜⎜⎝

⎛−=

EE (7)

E0 – pradinis tamprumo modulis, E –

;E = (8)

vid :

( )( ) ;11

2

11

0321

0⎟⎟⎠

⎞⎜⎜⎝

⎛−=+−⎟⎟⎠

⎞⎜⎜⎝

⎛−=

EE

p

EEvid (9)

;24

11

0⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞⎜

⎝⎛ −

⋅−

⋅⋅⎟⎟⎠

⎞⎜⎜⎝

⎛−= vid

vidvid pS

dp

S

dp

EEE (10)

σ

;0 CONST; ==dt

d (11)

;0dt

dEE

dt

d+=+ (12)

Θ -jos sprendinys:

( );0

0

0 EtECeE

⋅⋅−+= C – integravimo konstanta (13)

aprašo

0

�

1tt

2 pav. Deformacijos kitimas esant pradiniam tamprumo moduliui E0

– 403

Laiko momentu t1

;)(

ln00

0

E

C

t

EE

−= (14)

E

t

krovos veikimo laiko

astovi:

;0 CONST; ==dt

d (15)

;)( t000

−−+= eEE (16)

σσ0

σrib

t

Kadangi kra –

;24

1⎟⎟⎠⎞

⎜⎜⎝⎛

⎟⎠⎞⎜

⎝⎛ −−= ⋅⋅

vidvidvid p

ddp

S

p

SE (17)

-

;sin)( 2SAP(t) += ω (18)

A –S –ρ – kraujo tankis, ω – ,γ -

oporcingas spaudimui P(t) ir lygus:

;sin)( 2SKAP(t)KH +=⋅= ρ (19)

H – kraujo stulpelio nueitas kelias, K – ≅ 1.

aprašomas Eilerio diferencialine lygtimi[3]:

404

;2

dt

dvv

dS

dP(t)vid ρ−=⋅+− (20)

v –ξ – hidrodinaminis pasipriešinimas .

Esant pastoviam debetui Z≡

;)( 02 PSvaP(t) vid +⋅−⋅−= ξρ (21)

P0 -a – kraujo stulpelio pagreitis.

Perrašysime (21) patogesne forma:

;02vid PSvSaSP(t) +⋅−⋅⋅−⋅= ρ (22)

Lygtyje (1

),( 2a SAP += ω (23)

H = K⋅Pa⋅Sin(ω⋅t); (24)

v = H′ = ω⋅K⋅Pa⋅Cos(ω⋅t); (25)

a = H′′ = -ω2⋅K⋅Pa⋅Cos(ω⋅t); (26)

kur Pa –

;22

122 vvvvid ⋅−⋅=⋅ (27)

ξ1 – 1,ξ2 – 2,v – kraujo greitis vieno širdies susitraukimo metu.

( ) ;2 2221

2 ⋅−=−=⋅⋅ Svvid (28)

ξ1 − ξ2 = − [3]. Atlikus visus pakeitimus lygtis

;cos2sinsin)( 0222

a222

a2

a PPPtP +++= (29)

( ) ;cos2sinsin11 T

00

222a

222a

2a

T

0dtPPP

TP(t)dt

TPvid ∫ +++=∫= (30)

;22 0

222

a2

PvPK

Pvid ++= ρρ (31)

K ≅ 1,P0 = CONST, ω = 2πf = 2πT, T = t

;1

22 0

222

a2

tPv

PK

dt

dPvid⎟⎟⎠

⎞⎜⎜⎝

⎛++= ρ

ρ (32)

;22 0

222

a2

PvPK

k ++= ρρ (33)

gaunama: ;lntkPvid ⋅= (34)

– 405

priklauso nuo išorinio ir vidinio skersmens tolygumo, kraujo tankio ir jo specifinio svorio, tiesiai proporcingas

deformacijoms.

[1]:

• ÷ 2.4 [ ÷ 1.8 [cm], pilvo aortos 0.5 ÷ 1.2 [cm],

• ÷ 0.08 [cm], nusil ÷ 0.06 [cm], pilvo aortos 0.02 ÷ 0.06 [cm],

• [ [cm], pilvo aortos 15[cm].

[2] tamprumkitimo ribos 3⋅105 ÷ 12⋅105 [N/m2 [1] ⋅105 ÷ 10⋅105 [N/m2]. Tai gi

( , – variacinio .

ε = f(t)→max

σ = f(t)→ = f(t)→ ai tenka vis didesnis vid = f(t)→max.

[1] C.G.Caro, T.J.Pedley, R.C.Schroter, W.A. Seed. The mechanics of the circulation. Oxford University Press, New York Toronto 1981.

[2] T.J.Pedley.Cambrige monographs on mechanics and applied mathematics, The fluid mechanics of large biood vessels. Cambridge University press, Cambridge 1983.

[3] . . 1974.

[4] 1975.

Summary

MATHEMATICAL MODEL OF LARGE ARTERIAL VESSEL AS VISCOELASTIC BODYComputers and biomedical instrumentation provide capability investigation mechanics of arterial system. Much attention provides to the noninvasive estimate wall condition of large vessels. Exceptionally informative parameter thou obtain with noninvasive method is pulse wave velocity. Values of this parameter determine mechanical behavior of large vessels wall. This article describes mathematical model of large arterial vessel as viscoelastic body.

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g. 50 – 214c ,

- g

vietoje rekomenduojami hidromechaniniai, elektriniai, matematiniai modeliai. Ši pateikiamos informacijos gausa –

CONSTTpV

=⎟⎠⎞⎜⎝

⎛∂

∂ (1)

kietuose, skystuose, tampriuose bei tampriai-[4]:

F(p, V, T) = 0 (2)

P – V – T –

TRVp ⋅=⋅ (3)

2p

TR

p

V ⋅−=∂∂

(4)

p1=ϑ (5)

R = 8.31 - ϑ -Kietiems, skystiems, tampriems bei tampriai-

ϑ p, V, T) nustatyti nepavyksta, o ϑ randamas eksperimento keliu.

spaudimui vienu vienetu izoterminio proceso metu [4]:

CONSTTp

V

V =⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂−= 1ϑ (6)

idealioms dujoms ϑ = 0.98⋅10-6 (to ϑ = 48⋅10-12 ( H2O, to C= 20, p = 1atm), ϑ = 10-12 .

2

2

2

2

x

E

t ∂

∂⋅=

∂

∂ ξρ

ξ(7)

tx ,,,ξ - ρ - E – tamprumo modulis,

dydis ( )E2vE =ρ (8)

407

dim2

2

3

22

3

2

s

m

mkg

msmkg

mkg

mNE =⋅

⋅⋅⋅=

⋅

⋅=⎥⎦

⎤⎢⎣

⎡−

−−

−

−

ρ

ρEv = (9)

Tai garso sklidimo greitis idealiose dujose. Taikant

pV

pVE

CONSTT

=⎟⎠⎞⎜

⎝⎛

∂∂

−==

(10)

ϑ1=E (11)

pv ⋅= ϑ1 (12)

Nuo šios vietos išraiškos (9) ir (12) transformuojamos pritaikant jas garsoMensas ir Kortvegas

(ϑ [3] -

ρϑ ⋅=

adv

1(13)

–[2] :

d

hEc

⋅⋅=

ρ(14)

d

hEc

⋅⋅⋅=

ρ15.1 (15)

E – tamprumo modulis, ρ - kraujo tankis, d – h –

c –Naudojant (15) ir (16) sk %.

svcp ⋅⋅= ρ (16)

sv -

Pertvarkius (17) gaunamas SPB greitis:

sv

pc

⋅=

ρ(17)

δρ d

E

E

Ec

⋅+

⋅=0

0

1

1 (18)

E – E = (3÷12)102 [ ]2mkN , E0 – kraujo tamprumo modulis,

[ ]220 mkN10921.3 ⋅=E , d – δ -

ρ0E -

1)

[ ];5.19321005.1

1010921.3v

3

850

g smE

=⋅

⋅⋅==ρ

(19)

2) adϑ ):

[ ];5.19321005.155.2

10101v

3

86

g sm

ad=

⋅⋅

⋅=⋅

=ρϑ

(20)

408

( ) ( );

1

vc

0

g

δdEE ⋅+= (21)

Iš (21) aorta ascendens),

d δ = 0.05cm, E0 = 3.921⋅105 [kN/m2], E = 3⋅105 [kN/m2]

( ) ( )];/[41.5

05.0103

5.110921.31

5.1932

1

vc

5

50

gsm

dEE=

⋅⋅

⋅⋅+

=⋅+

=δ

÷ 6 m/s [1]. us

ρνdlp ⋅⋅

= 1Re (22)

Re – ν - kraujo klampumas, p –

( );

Re

vc

g

δd+= (23)

Tarkim, reikia rasti S ld δ = 0.08cm, E0 = 3.921⋅105 [kN/m2], E = 3⋅105 [kN/m2], arterinis sistolinis spaudimas p = 120mmHg = 15996[kg/s2⋅m2].

42751005.1

105.2108.015996

104

11Re

2

3

3

6=

⋅

⋅⋅⋅⋅

⋅=

⋅⋅=

−−

ρνdlp

,

( )[ ]sm03.6

1.0

5.24275

5.1932

Re

vc

g =⋅

=+

=δd

,

÷ 6 m/s [1]. [2], bei T.Pedli formules (2.7a, 2.7b)

[2

naudojama SPB sklidimo matematiniam modeliavimui.

[1] C. G. Caro, T. J. Pedley, R.C. Schroter, W.A. Seed. The mechanics of the circulation. Oxford University Press, New York Toronto 1981.

[2] T.J. Pedley.Cambrige monographs on mechanics and applied mathematics, The fluid mechanics of large blood vessels. Cambridge University press, Cambridge 1983.

[3]

[4] 1964.

Summary

THEORETICAL EVALUATION VELOCITY OF PULSE WAVE PROPAGATION IN ARTERIAL SYSTEMS. Velocity of pulse wave propagation is significant physiological parameter to evaluation large blood vessels wall tone. Scientific papers presenting much information about pulse wave propagation and others parameters. However this information abundance cover point of the matter – sound propagation velocity in blood vessels. This paper describes theoretical evaluation velocity of pulse wave and sounds in arterial systems.

����������������� �����������������MACIJA ���������������� ��� ����� �����E

������� ��������� !�� ������!��

Kauno technologijos u – 208, 3028 Kaunas

GCVesant dideliam tri

1

Naudojant šiuos metodus atlikus signalo su triu

lauso tiek nuo

metodu.

2

,,1, Nify iii =+= ε

y = f + ε,

y – f –

ε – triukšmas, stacionarus stochastinis signalas, t.y.

0=Ε iε ir Nii ...,,1,22 =∀=Ε σε .

W gausime

V = W ⋅ f,

ω = W ⋅ ε, (1)

w = W ⋅ y = V + ω.

ε yra baltas triukšmas, tai jo transformacija taip pat yra baltas

w vektoriumi wδ:

wδ = Dδ ⋅ w,

kur Dδ = diag[dii].

Atlikus ši –δ ir δDδ koeficientais.

410

δ – slenkstis.

⎪⎩

⎪⎨⎧

≥−

<

. ,1

, ,0= δδ

δ

ii

i

ii ww

wd

⎪⎩

⎪⎨⎧

<≥−

<

., ,1

, ,0=

11 δδδδ

δ

ii

i

ii ww

wd

wδ, gausime

yδ = W-1 wδ.

3δ

δpagal signalo - δ, reikia maksimizuoti STS

∑∑⋅

2

2

10log10 =i

ifSTSδε

,

kur:

Nify iii ,1 , =−= δδε –

R(δ) minimizavimui:

( ) ( )N

fyR

N

i ii∑ −1=

2

= δδ .

iau, kadangi determinuotas signalas f ( )δR

δ

σδ ⋅⋅= Nlog2 . (2)

σ2

Tokiu atveju, kai n σ ( )δR funkcijos naudojamas apibendrintas tarpusavio

validavimo metodas (Generalized Cross Validation) metodas [3, 4].

Funkcija ( )δGCV

( )( ) 2

21

N

DTRN

wwNGCV

′−

−=

δδ , (3)

kur:

j

iij w

wd

∂∂ δ=′ ,

⎪⎩

⎪⎨⎧

≥<

=′,,1

,,0

δδ

i

iii w

wd ( ) { }0≠=′ iwiDTR δ .

( )δR ir ( )δGCV

naudojant abi funkcijas.

4

signalui, pateiktam 1 paveiksle.

411

Rezultatai, gaut

σKaip matome iš 2- as triukšmo parametrui σ.

w = Wy = Wf + Wε . (4)

( ) εε WWffW +≠+ , t.y. didesni triukšmai taip pat

412

ezultatai gauti naudojant 256-

GCV

%.

5 pav. ir 1- GCV -ias diskretizuoto signalo reikšmes ir

GCV(δδ Visu

Shrink, Sure Shrink) [2] nurodoma, kad geriausi rezultatai gaunami, kai yra 4096 ir daugiau diskretizuoto signalo

413

5– ar

ek

ww ≥ . (5)

” optimalaus %

10% ju”% %

414

%

6 Išvados• %

paklaida.

•

• GCV

[1] D. L. Donoho and I. M. Johnstone. Ideal separatial adaption via wavelet shrinkage. Biometrika, 81, 1994, p. 425 - 455.

[2] D. L. Donoho and I. M. Johnstone. Adapting to unknown smoothness via wavelet shrinkage. J. Amer. Statist. Assoc., 1995

[3] G. Wahba. Spline Models for Observational Data, chapter 4. CBMS-NSF Regional Conf. Series in Appl. Math. Society for Industrial and Applied Mathematics, Philadelphia, PA, 1990.

[4] M. Jansen, M. Malfait, A. Bultheel. Generalized Cross Validation for wavelet tresholding. Signal Processing 56(1),1996.

[5] A.Mikuckas,. Technologija, Kaunas, 2000, 174 - 179 pp.

[6] D. Donoho. De-noising via soft tresholding. Technical Report 409, Department of Statistics, Stanford University,1992.

[7] A.Mikuckas,. Konfe . Technologija, Kaunas,

1999, 336 - 341 pp.

Summary

THRESHOLD ESTIMATION FOR WAVELET TRANSFORM BASED DENOISING METHODS It is very important to choose optimal threshold value in wavelet transform based denoising. Different approaches providing better visual qality or mean square error are evaluated in this paper.

DTMF (DUAL–TONE MULTI–FREQUENCY) KODAVIMAS –DEKODAVIMAS SU ANALO�����)�����������OCESORIUMI

ADSP-21065L EZ-LAB

��#���&��%��!�� �������������������� �%!�%���!��"���� �%�����%�0#����"�� ��1�����'$"�

-214c, 3028 Kaunas

ADSP-su

-

1DTMF (Dual–Tone Multi– signalizacijos bendrinis vardas. Ši

metu DTMF naud

2 DTMF Standartai ir reikalavimai

697, 770, 852, 941Hz 1209, 1336, 1477, 1633Hz

šios specifikacijos daugeliu atveju tenkina CCITT rekomendacijas Q.23 ir Q.24.

Pagrindiniai reikalavimai:

priimtina nepriimtina

a) 40 ms min. b) 23 ms max. c) 40 ms min. d) 10 ms max.

:

Stulpeliai 1209Hz 1336Hz 1477Hz 1633Hz

697Hz 1 2 3 A 770Hz 4 5 6 B 852Hz 7 8 9 C 941Hz * 0 # D

Kiekvieno klavišo paspaudimu sugeneruojamas dvie

Va416

kuri yra IIR modifikacija.

3 Projekto tikslai

- projekto tikslams. DTMF

praktiškai -

4Ši sistema sujungta per RS-

O S R S 2 3 2d r iv e r

A D S P -2 1 0 6 5

R A M

B o o tR O M

R S 2 3 2

A D 1 8 1 9 A 1 6 b i ts o u n d p o r t

c o d e c

G U I( V is u a l C + + )

G U I &a lg o r it h m

im p le m e n t a t io n( M A T L A B )

P C( W in d o w s N T )

A D S P - 2 1 0 6 5 E Z - L A BE v a lu a t io n b o a r d

( V is u a l D S P )

I nO u t

4.1 Grafinis interfeisas

4.2 Alg– skaitmeninis ir skaitmeninis – analoginis

keitikliai, 8 juostiniai filtrai, modulio išskyrimo funkcija ir dekodavimo logika:

DTMF kodavimas– -21065L EZ-LAB 417

L oo pb ac k

P C (W in d o w s N T )

A D S P -2 1 0 6 5 L E Z - L A B

C 4

C 3

C 2

R 1

R 2

R 3

R 4

C 1

6 9 7 H z

7 7 0 H z

8 5 2 H z

9 4 1 H z

1 2 0 9 H z

1 3 3 6 H z

1 4 7 7 H z

1 6 3 3 H z

A B S

A B S

A B S

A B S

A B S

A B S

A B S

A B S

B an d p as s fi l te r s A bs ol u te va l u e

De

co

din

g l

og

ic

S ig n alsge ne rato r

1 6 b it D A C

1 6 b it A D C

R S 23 2 d rive r

G U I

schema

4.2.1 Signalo generavimas

)];1,1

**2cos(*2,1[ −=Fs

Fa π

)].0,1

**2cos(,1[Fs

Fb π−=

4.2.2 Filtrai

generuoti. Taip išlošiama atsako laiko ir gaunamas pakankamai geras slopinimas nepralaidumo juostoje.

šskiriama absoliuti

Va418

4.2.3 Dekodavimo logika

niu lygiu,

5 Realizacija

-21065L EZ-LAB.

ADSP-21065L EZ-

1. Super Harvard’o k –

2.

3. 544 b

4. Greitaveika – 66MIPS, 198MFLOPS;

5.atminties.

Algoritmas suprogramuotas Analog Devices šeimos asemblerio kalba.

Projekte naudojama Analog Devices ADSP21065L EZ--

6 ApibendrinimasSistemoje naudojamas algoritmas gana atsparus triukšmams, reikalauja tiktai 20dB SNR, kai triukšmo

[1] E. C. Ifeachor, B. W. Jervis. Digital Signal Proccesing: A Practical Approach. Addison-Wesley, 1997.

[2] Analog Devices. ADSP-21065L EZ-LAB Development System Manual. Analog Devices Inc., March 1, 1999.

[3] G. Arslan, B. L. Evans, F. A. Skarya, J. L. Pino . Performance Evaluation and Real-Time Implementation of Subspace, Adaptive, and DFT Algorithms for Multi-tone Detection. Dept. of Electronics and Comm. Eng., Yildiz Technical University, Istanbul, Turkey, Dept. of EECS, University of California, Berkeley, CA 94720, USA, 1996

Summary

DTMF CODING/DECODING SYSTEM BASED ON ADSP-21065L EZ-LAB EVALUATION BOARD The main tasks of this project are to familiarize with practical usage of DSP algorithms and to soak up with ADSP-21065L board. DTMF task was choosed because it has wide usage. We meet with large variety questions of signal proccesing theory here, such as sampling, quantization, filtering. We meet with practical comunication between differrent devices through RS232 interface too. This algorithm could be inserted in to project of wider spread, and developed as product successfully. For example: phone number decoding, equipment of interactive service, equipment of gathering of steady information.

���������� �� ������������������IMAS �������������������������

������������������������ ����!�"���#����$%&"��������

Kauno technologijos u -214b, Kaunas

1

sunaudojamas resu

nuoseklios

Z=f(X,Y)

X Y

Z

mas

X

Z=f(X,Y)

Y

Z

lsd

msd

msd

lsd

a)

X

Z=f(X,Y)

Y

Z

lsd

msd

msd

lsd

b)

a) pradedant jauniausiomis skiltimis, b) pradedant vyriausiomis skiltimis

(angliškas terminas on-

5 0

4 9

0

9

?

?

1

? ? ? ? ?

0

0

9?

Z

X

Y

5 0

4 9

1 -1Z

X

Y

a) b)

3 pav. Pavyzdys: nuoseklus sumavimas pradedant vyriausiomis skiltimis: r r

interfeisus

Valdas Kavaliauskis, Egidijus K420

Vienos operacijos OL algoritmas vienas vienas Daugiaoperacinis OL algoritmas keli vienas

keli keli S keli keli (integruoti)

2

),( YXFZ = (2.1)

kliai, pradedant

Dρ kuri

},...,0,...,1,{ ρρρρ +−−≡D

kur ρ Dρ

1−≡

rK

ρ

kur r sistemos pagrindas.

δ, yra sukaupiamas gi j+δ-1

forma:

ρδδ

δ

DxxjXprijungtirxjX jj

j

i

ii ∈== −+−+

−+

=

−∑ 11

1

1

),],[(][

ρδδ

δ

DyyjYprijungtiryjY jj

j

i

ii ∈== −+−+

−+

=

−∑ 11

1

1

),],[(][

ρDzzjZprijungtirzjZ jj

j

i

ii ∈== ∑

=

− ),],[(][1

...x1 x2 x3

x

...y1 y2 y3

y

z

z1 z2 z3 ...

δ

f

x y

z

δ

jj rjYjXFjZ −+= ε])[],[(][ (2.2)

εj

1<jε .

po j+δ-1 j jr −± . Jei m yra m+δ-1 X[m] = X ir Y[m] = Y)

421

mrYXFmZ −<− ),(][

ir Z[m] yra teisingas funkcijos F(X, Y) rezultatas su m lumu.

išreiškiama

]))[],[(][(][ jYjXFjZGjP −=kur transformacijos funkcija G turi tokias savybes

1. P[j]

2. Jei

)(]))[],[(][( jrGjYjXFjZG −<− (2.3)

tai jrjYjXFjZ −<− ])[],[(][ (2.4)

Transformacijos funkcijos G1.2.

]))[],[(][(][][ jYjXFjZGrjPrjR jj −=≡ (2.5)

)1[][(]1[][ −−+−= jPjPrjrRjR j (2.6)

Kadangi P[j]ir P[j-1]Z[j] išreiškus

jj rzjZjZ −+−= ]1[][

atskiriame narius, kuriuose yra zj

][][]1[][ 21 jHzjHjrRjR j++−= (2.7)

kur

])1[][(][][ 21 −−=+ jPjPrjHzjH jj

ir H1[j] nepriklauso nuo zj. Tegul

][]1[][ 1 jHjrRjA +−≡ (2.8)

tada ][][][ 2 jHzjAjR j+= (2.9)

⎪⎩

⎪⎨⎧

=

+−+−= −

])[(

][)1[]1[(][ 121

jASz

jHjHzjArjA

j

j (2.10)

kur S

išrinkimo funkciniai komponentai (5 pav.).

3Tarkime OL aritmetikos s

Valdas Kavaliauskis, Egidijus K422

X

√

+

δ

δ

δ

δ

x

X

y

z

δ

x y

z

x2 y2+=z

a) b)

6 pav. Išraiškos 22 yxz +=

Pirmas tipas yra

šiuos fiksuotus

Kitas tipas yra daugiaoperaciniai OL algoritmai

[1] M. D. Ercegovac. On-line arithmetic: an overview. IEEE Computer, Sausis 1982, p. 37-46.

[2] M. D. Ercegovac, T.Lang. On-line arithmetic: A design methodology and applications in digital signal processing. IEEE Acoustics, Speech, and Signal Processing Society Workshop on VLSI Signal Processing, Lapkritis 1988, p. 252-263.

[3] P. Kang-Guo Tu. On-line arithmetic algorithms for efficient implementation. Ph.D. dissertation, University of California, Los Angeles, 1990.

[4] A. G. Nielsen. Number systems and digit serial arithmetic. Ph.D. dissertation, Odense University, Denmark, 1997.

Summary

SERIAL ARITHMETIC OPERATIONS USAGE FOR DIGITAL SIGNAL PROCESSING Implementing parallel arithmetic operations in programmable logic the main problem is large resource usage. Using digit serial arithmetic decreases resources. This publication represent ways for computation organisation, the general approach for the derivation of on-line algorithms, the types of on-line algorithms for sequences of arithmetic operations.