2 Dispositivos Integrados - Unidad FPGA VHDL_1
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Por ejemplo:
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Por ejemplo:
entity sumador is port (A,B: in bit_vector (3 downto 0) ; Cin: in bit; Cout: out bit; SUMA: out bit_vector( 3 downto 0)) ; end sumador;
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1 — Ejemplo 2 library ieee; 3 use ieee.std_logic_1164.all ; 4 entity tabla is port( 5 a,b,c: in std_logic; 6 f: out std_logic); 7 end tabla; 8 architecture ejemplo of tabla is 9 begin 10 f <= '1' when (a='0' and b= '0‘ and c= '0') else 11 '1' when (a= '0‘ and b= 1 and c= '1') else 12 ‘1 ‘ when (a= '1‘ and b= '1' and c= '0') else 13 '1‘ when (a= '1' and b= '1' and c= '1’ ) else 14 '0'; 15 end ejemplo;
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library ieee; use ieee.std_logic_1164.all; entity logic is port ( a,b,c,d,e,f: in std_logic; x1,x2,x3: out std_logic) ; end logic; architecture booleana of logic is begin x1 <= a xnor b; x2 <= ( ( (c and d) or (a xnor b) ) nand ( (e xor f) and (c and d) ) ) ; x3 <= (e xnor f) and (c and d) ; end booleana;
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Diseño de un multiplexor El primer ejercicio consistirá en crear el diseño de un multiplexor de dos entradas de datos de un bit. Por tanto, este multiplexor tendrá una señal de selección (un bit).
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http://books.google.es/books?id=wpRRNiq5V1EC&printsec=frontcover&dq=boylestad&hl=es&sa=X&ei=raVrVIrxC4qhNsiPgqAE&ved=0CCUQ6AEwAA#v=onepage&q=boylestad&f=false