14465_051-7164 M57 TRUCKEE

TABLE_TABLEOFCONTENTS_ITEM





















































































TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPDENG

DATE

APPDCK

ECNZONEREV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTIOND

SIZE

APPLICABLENOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OFSHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

12345678

12345678

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

Schematic / PCB #s

SCHEMATIC,MACBOOK PRO 17"9/26/2006

SCHEMATIC,MACBOOK PRO 17

?? ?? ?

871

051-7164 06004

(.CSA)

SYNCDATE

CONTENTSPAGE

LAST_MODIFIED=Tue Sep 26 13:17:56 2006

TITLE=TRUCKEE

ABBREV=DRAWING

44 M59_MLBFireWire Ports 06/27/200646

SCHEM,TRUCKEE,M57051-7164 CRITICALSCH1

PCBF,TRUCKEE,M57 CRITICALPCB1820-2059

N/AN/A1 1 Table of Contents

PAGE(.CSA)

SYNCDATE

CONTENTS

45 M59_MLBCamera Connector 09/15/200649

46 (MASTER)Internal USB Hub (MASTER)50

47 M59_MLBExternal USB Connector 09/15/200652

48 (MASTER)Left I/O Board Connector (MASTER)55

49 (MASTER)Current & Thermal Sensors (MASTER)56

50 (MASTER)PCI-E Connections (MASTER)57

51 M59_MLBSMC 09/15/200658

52 M59_MLBSMC Support 09/15/200659

53 (MASTER)LPC+ Debug Connector (MASTER)60

54 M59_MLBThermal Sensors 09/15/200661

55 M59_MLBCurrent & Voltage Sensing 09/15/200662

56 M59_MLBSPI BOOTROM 09/15/200663

57 (MASTER)ALS Support (MASTER)64

58 (MASTER)Fan Connectors (MASTER)65

59 M59_MLBSudden Motion Sensor (SMS) 09/15/200666

60 M59_MLBTPM 09/15/200667

61 M59_MLBIMVP6 CPU VCore Regulator 09/15/200675

62 M59_MLB5V / 1.5V Power Supply 09/15/200676

63 M59_MLB2.5V & 1.2V Regulators 09/15/200677

64 (MASTER)1.8V Supply (MASTER)78

65 (MASTER)3.3V / 1.05V Power Supplies (MASTER)79

66 M59_MLB3.3V G3Hot Supply & Power Control 09/15/200680

67 (MASTER)Power Aliases (MASTER)81

68 (MASTER)DC-In & Battery Connectors (MASTER)82

69 M59_LIOPBus Supply & Batt. Charger 09/15/200683

70 (MASTER)ATI M56 PCI-E (MASTER)84

71 (MASTER)GPU (M56) Core Supplies (MASTER)85

72 (MASTER)ATI M56 Core Power (MASTER)86

73 (MASTER)ATI M56 Frame Buffer I/F (MASTER)87

74 M57_MLB_MGGPU Straps 08/08/200688

75 (MASTER)GDDR3 Frame Buffer A (MASTER)89

76 (MASTER)GDDR3 Frame Buffer B (MASTER)90

77 (MASTER)ATI M56 GPIO/DVO/Misc(MASTER)91

78 (MASTER)ATI M56 Video Interfaces (MASTER)93

79 M57_MLB_MGInternal Display Connectors 08/08/200694

80 M59_MLBExternal Display Connector 09/15/200697

81 (MASTER)M57 SPECIFIC CONNECTORS (MASTER)98

82 M59_MLBLVDS Interface Pull-downs 09/15/200699

83 (MASTER)Revision History (MASTER)100

84 (MASTER)Napa Platform Constraints (MASTER)101

85 (MASTER)More System Constraints (MASTER)102

86 (MASTER)M9 Spacing & Physical Constraints (MASTER)103

87 (MASTER)M57 NET PROPERTIES (MASTER)104

(MASTER)(MASTER)2 2 System Block Diagram

(MASTER)(MASTER)3 3 Power Block Diagram

(MASTER)(MASTER)4 4 BOM CONFIGURATION

(MASTER)(MASTER)5 5 Functional / ICT Test

(MASTER)(MASTER)6 6 Signal Aliases

M59_MLB09/15/20067 7 CPU 1 OF 2-FSB

M59_MLB09/15/20068 8 CPU 2 OF 2-PWR/GND

M59_MLB09/15/20069 9 CPU Decoupling & VID

M59_MLB09/15/200610 10 CPU MISC1-TEMP SENSOR

(MASTER)(MASTER)11 11 CPU ITP700FLEX DEBUG

M59_MLB09/15/200612 12 NB CPU Interface

M59_MLB09/15/200613 13 NB PEG / Video Interfaces

M59_MLB09/15/200614 14 NB Misc Interfaces

M59_MLB09/15/200615 15 NB DDR2 Interfaces

M59_MLB09/15/200616 16 NB Power 1

M59_MLB09/15/200617 17 NB Power 2

M59_MLB09/15/200618 18 NB Grounds

M57_MLB_MG08/08/200619 19 NB (GM) Decoupling

M59_MLB09/15/200620 20 NB Config Straps

M59_MLB09/15/200621 21 SB: 1 OF 4

M59_MLB09/15/200622 22 SB: 2 of 4

M57_MLB_MG08/08/200623 23 SB: 3 OF 4

M59_MLB09/15/200624 24 SB: 4 OF 4

M59_MLB09/15/200625 25 SB Decoupling

(MASTER)(MASTER)26 26 SB Misc

(MASTER)(MASTER)27 27 M57 SMBUS CONNECTIONS

M59_MLB09/15/200628 28 DDR2 SO-DIMM Connector A

M59_MLB09/15/200629 29 DDR2 SO-DIMM Connector B

(MASTER)(MASTER)30 30 Memory Active Termination

M59_MLB09/15/200631 31 Memory Vtt Supply

M59_MLB09/15/200632 32 DDR2 VRef

M59_MLB09/15/200633 33 CLOCKS

M59_MLB09/15/200634 34 Clock Termination

M59_MLB09/15/200635 37 Mobile Clocking

(MASTER)(MASTER)36 38 PATA Connector

M59_MLB09/15/200637 39 FireWire Link (TSB83AA22)

M59_MLB09/15/200638 40 FireWire PHY (TSB83AA22)

M59_MLB09/15/200639 41 ETHERNET CONTROLLER

M59_MLB09/15/200640 42 Ethernet Connector

M59_MLB09/15/200641 43 Yukon Power Control

M59_MLB09/15/200642 44 FW PHY Power Supply

(MASTER)(MASTER)43 45 FireWire Port Power

DSIZE

OFSHT

DRAWING NUMBER



III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT


12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

P.46,81

USB 2.0 Hub/Sleep LED IRConnector

USB

USB

P.78

Controller

PCIe x1

P.47Connector

Right USB 2.0

SATAUSB

HDD/BT

P.68

CK410 Clock

Controller

P.33-34

Temperature

Sensors

Connector

LCD Panel

P.79,82

TPM

Connector

LPC

Debug

P.21-26

RT ALS

Expansion/Lower Connector

Factory/Upper Connector

(Merom)

ATI M56P

Yukon Gig-E

P.39P.41

P.37-38Controller

TSB83AA22 FireWire

P.44Connectors

USB x2

w/TV-Out Support

SENSOR

& REGULATOR

DDR2 VTT

DDR2 SO-DIMM A

J2800

J2900

Connector

Audio Board

Left I/O &

DDR2 VREFBUFFER

Azalia (HD-Audio)

PCIe x1

Connector

ITP700FLEX

CPU Debug

479 BGA

CH.A

CH.B

FSB

NB1466UFCBGA

945GM

Core DuoCPUTHERMAL

GDDR3

USB

609 BGA

Sensors

SMC

SPIBootROM

SMBusUSB

USB

SB SMBus

PATA66MHZ16BITS

TP Connector

Geyser KB /

Connector ODD

Connector

CONNECTOR

INVERTER

Yukon Power

PCI

FW

SMS

Fan

ConnectorsPWM/Tach

SMC SMBus

DDR2 SO-DIMM B

Battery SMBus

Analog

SMBus x5

H8S/2116

GPU

128MB/256MBFrame Buffer

ENET

DVI-I/DL Connector

P.10

P.7-9

P.11

P.12-20P.30-31P.29

P.28

P.32

P.45

P.36

P.27

P.27

Connectors

Power

P.40Connector

RJ45 (Ethernet)

Supplies

1394a/b (FireWire)

P.42

PHY Power

LPC 33MHZ

SB

ICH7-M

PBUS Supply

Batt Chgr/

PCIe x1

DMI x4

PCIe x16

Port Power

P.43

LVDS Graphics

Dual-Channel TMDS

S-Video/Composite

MUX

PWM

Dual-Channel LVDS

P.79

P.80

P.75-76

P.70-74,77-78

P.81

Camera

P.45

P.48,54

P.56

P.58

P.51-52

P. 60 P.53

P.57

P.59

P.55

P.48

P.69

P.61-68,71

051-7164

872

06004

System Block DiagramSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PPDCIN_G3H

18.5V - 9V

PP5V_S3

PM_SLP_S4_LS5V

Q7610

5.0V

PPBUS_G3H

U8300

SUPPLY

PBUS

12.6 - 9V

PPBUS_G3H

3.425

(LT3470)

ENABLE

3.425V

PP3V42_G3H

U8000

G3Hot

12.6V - 9V

(LTC3728)

1.25V - 0.8V

J9450

PP1V8_D3C

=GPUVCORE_EN_L

1.1V - 0.95V

SMC_PM_G2_ENABLE

U7900

IMVP_PWRGD_IN/ALL_SYS_PWRGD

U7700

PM_SLP_S3_LS5V

PM_SLP_S4_LS5V

PM_SLP_S3BATT

ODD_PWR_EN_L (SB GPIO14)

PP5V_S0_IDE_ODD

Q3820

5.0V

PP5V_S0

5.0V

PM_SLP_S3BATT

PM_SLP_S3BATT

PP3V3_S3AC

Q4300

3.3V

PP3V3_S3

3.3V

Q7945

PM_SLP_S3_LS5V

PP2V5_S0

Q7720

2.5V

PP2V5_D3C

P1V2R2V5DC3_EN_LS5V

2.5V

Q7721

NC

PP2V5_S3

P1V2R2V5D3C_EN_LS5V

PP1V2_D3C

(TPS62510)

ENABLE

2.5V

S5S0

S3

(ISL6269B)

(ISL6269B)

(ISL6269B)

(TPS51100)

(TPS5117RGY)

(ISL9504)

Q7947

PM_SLP_S3_L

PM_SLP_S4_L

1.8V

PM_SLP_S3_LS5V_L

1.2V

Q4565

0.9V

PP0V9_S0S0

0.9V (Vtt)

U3100

PM_SLP_S3_L

PGOOD

ENABLE

S3

U7800

1.8V

NC

ENABLE

ENABLE

S0

IMVP_VR_ON

CPU VCoreS0

VR_PWRGOOD_DELAY

SMC_PM_G2_ENABLE

1.5V

5V

U7600ENABLES

PGOOD

NC

PP5V_S5

5.0V

PP1V5_S0

PGOOD

2.5V

PP1V2_S3

1.2V

ENABLE

1.2V

PGOOD

S3

(LTC3412)

NC

3.3V

ENABLE

GPU VCore

S0

U7950

1.05V

PGOOD

ENABLE

3.3V

S5

PGOOD

1.5V

NC

PP3V3_S0

U8500

5V/1.5V

FWPWR_EN

12.6V - 9V

PPBUS_S5_FWPORT

Connector

Inverter

RSMRST_PWRGD

PGOOD

"IMVP6"

Q7770

U7750

PPVCORE_S0_CPU

ENABLES

Q7845

PM_SLP_S3_L

1.05V

PP1V05_S0

PP3V3_S5U7530

IMVP_PWRGD_IN

PGOOD

PPVCORE_S0_GPU

3.3V

1.8V

PP1V8_S3

5.0V

PM_SLP_S3_LS5V_L

(ISL6255AHRZ)

ENABLE Q7615

PP18V5_G3H_CHGR

Q8250

Connector

MLB DC in

J8290

LIO PowerConnector

J8290ACIN_ENABLE_DIV_L

3 87

06004051-7164

Power Block DiagramSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM



TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD




TABLE_BOMGROUP_ITEM

SMC_TPM_PPSMC_TPM_GPIO1SMC_TPM_GPIO2Extra TPM options:

IS

MODULE PARTS

ALTERNATE PARTS

BAR CODE LABELS / EEE #S

1338S0269 CRITICALU1200IC,945GM,NORTHBRIDGE

1343S0385 CRITICALU2100IC,ICH7M,BGA

337S3393 1 U0700 CRITICAL CPU_2_33GHZ_B2IC,MDC,B2,PRQ,2.33GHZ,34W,667M,4M,479 BGA

TRUCKEE,2.33GHZ,B2,256VRAM,SAM,M57 VRAM_256SAM,M57_COMMON,CPU_2_33GHZ_B2,EEE_WJK630-7814 1341S1924 CRITICALIC, BOOTROM, DEVELOPMENT, UNLOCKED ,M57 U6301

335S0384 IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC81 CRITICAL BOOTROM_BLANKU6301

IC, BOOTROM, FINAL, LOCKED, M57341S1925 1 CRITICALU6301

U3301359S0109 1 IC,LOW POWER CLOCK SYNTHESIZER,68PIN

IC, TPM, 28-PIN TSSOP TPM1341S1789 U6700 CRITICAL

1 IC,EEPROM,SERIAL IIC,8KBIT,SO8341S1797 U4102 CRITICAL

IC,SMC,HS8/21161338S0274 U5800 SMC_BLANKCRITICAL

IC,PRGRM,SMC(NEW),M571 U5800 CRITICAL341S1931 SMC_PRGRM

M57_TPM TPM

[EEE:WJK]LBL,P/N LABEL,PCB,28MM X 6 MM826-4393 1 CRITICAL EEE_WJK

VRAM_128_SAMSUNGVRAM_128SAM

VRAM_256SAM GPU_MEM_256M,VRAM_256_SAMSUNG

ALTERNATE,COMMON,M57_COMMON1,M57_COMMON2,M57_COMMON3,M57_COMMON4,M57_DEBUGM57_COMMON

ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3,ISL6255A,NO_3GM57_COMMON1

M57_COMMON2 KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU

M57_COMMON3 LVDS_PD,FW_PORT_FAULT_PU

M57_COMMON4

ITP,LPCPLUSM57_DEBUG

338S0368 IC,ATI,M56P,GRPHSCTRL,880BGA,LF U84001 CRITICAL

333S0354 U8900,U8950,U9000,U90504 CRITICAL VRAM_128_SAMSUNGIC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

4333S0350 U8900,U8950,U9000,U9050IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA VRAM_256_SAMSUNGCRITICAL

333S0377 IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA U8900,U8950,U9000,U9050 VRAM_256_INFINEONCRITICAL4

128S0083 1.86 MAX ALT TO 1.9 MAX128S0073 C2516

128S0093 KEMET IS ALT TO SANYO128S0092 ALL

376S0445 ALL Si7806ADN for FDM6296376S0448

333S0351 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 VRAM_256_HYNIX4 CRITICAL

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 VRAM_128_INFINEONCRITICAL333S0376 4

1 IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO338S0270 U4101 CRITICAL

353S1461 U75301 CRITICALIC,ISL9504,SYNC REG CTL,QFN 48

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 VRAM_128_HYNIX4333S0358 CRITICAL

152S0287 152S0435 ALL Alternates for Coilcraft MSS5131

353S1461353S1465 Screened ISL6262 for ISL9504ALL

SYNC_MASTER=(MASTER)

4

051-7164

SYNC_DATE=(MASTER)

87

06004

BOM CONFIGURATION

BOOTROM_DEVEL

BOOTROM_FINAL

CRITICAL

BOOTROM_DEVEL,SMC_PRGRM

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

EXPOSED_VIA

opening for use as engineering probe point.should have a via with 10-mil soldermaskEXPOSED_VIA property indicates that the net

Power Supply NO_TESTsNO_TEST EXPOSED_VIA

NO_TEST

EXPOSED_VIA

NO_TEST EXPOSED_VIA

Misc NO_TESTs

CPU FSB NO_TESTs

Misc EXPOSED_VIA Nets

Inverter Connector

Camera Connector

Request for at least 2 GND TPs per resistor

FUNC_TEST

Left I/O Power Connector

Resistor CalibrationFUNC_TEST

Request for at least 10 GND test points

Request for at least 10 GND TPs

Characterization TPs

FUNC_TEST

Power Nets

(=PP3V3_S0_CK410)

FUNC_TEST

Functional Test Points

Battery Connector

FUNC_TEST

Fan Connectors

FUNC_TEST

MAC-1 TPs

FUNC_TEST

(=PP1V2_S3_ENET)(=PP3V3_S3_ENET)(=PP2V5_S3_ENET)

FUNC_TEST

LPC+ Debug Connector

FUNC_TEST

Left I/O Data Connector

Thermal Sensors

SMC TPs

FUNC_TEST

FUNC_TEST

FUNC_TEST

I134

I135

I138

I139

I140

I141

I142

I143

I164

I165

I166

I167

I168

I169

I172

I173

I174

I175

I176

I177

I178

I179

I182

I183

I184

I185

I186

I187

I188

I189

I190

I191

I192

I193

I194

I195

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I213

I214

I215

I216

I217

I218

I219

I220

I221

I222

I223

I224

I225

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I267

I269

I273

I275

I276

I277

I278

I279

I280

I281

I282

I283

I285

I286

SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-7164 06004

875

Functional / ICT Test

=PCIE_MINI_D2R_NTRUE

PCIE_CLK100M_MINI_NTRUE

PCIE_CLK100M_MINI_PTRUE

=PCIE_MINI_R2D_PTRUE

ACZ_BITCLKTRUE

TRUE LTALS_OUT

TRUE =PCIE_EXCARD_R2D_P

=SMBUS_LIO_SB_SCLTRUE=SMBUS_LIO_SB_SDATRUE

TRUE =SMBUS_LIO_SMC_SCL

TRUE BOOT_LPC_SPI_L

LPC_FRAME_LTRUE

LPC_ADTRUE

LPC_ADTRUE

=PP3V3_S5_LPCPLUSTRUE=PP5V_S0_LPCPLUSTRUE

TRUE PM_SYSRST_L

TRUE SMC_ONOFF_L

RSFSTHMSNS_D_NTRUE

TRUE HSTHMSNS_DX_NTRUE HSTHMSNS_DX_P

RSFSTHMSNS_D_PTRUE

TRUE =PP1V5_S0_LIO

TRUE =PPBUS_G3H_LIO_CONNTRUE PP18V5_DCIN

=PCIE_MINI_D2R_PTRUE

TRUE =USB2_LT2_N

=PCIE_EXCARD_D2R_PTRUE

TRUE ALS_GAIN

FAN_RT_TACHTRUE

TRUE =PPBATTNEG_G3H_BATT_CONN

GNDTRUE

SMC_LRESET_LTRUE

TRUE IMVP6_VID

TRUE NB_RST_IN_LPEG_RESET_LTRUE

PP2V5_S3TRUEPP2V5_S3_ENET_AVDDTRUE

TRUE PP3V3_S0_CK410_VDDA

PM_SLP_S3_LTRUE

TRUE PP3V3_S0_CK410_VDD_CPU_SRC

TRUE PP3V3_S0_CK410_VDD_PCITRUE PP3V3_S0_CK410_VDD48

PP3V3_S0_CK410_VDD_REFTRUE

PP3V3_S0TRUETRUE PP2V5_S0_GPU_LVDDRTRUE PP2V5_S0_GPU_LPVDDTRUE PP2V5_S0_GPU_A2VDDTRUE PP2V5_S0_GPU_AVDDTRUE PP2V5_S0_GPU_TXVDDRTRUE PP2V5_S0_GPU_TPVDD

TRUE CPU_PWRGD

TRUE NB_SB_SYNC_LTRUE FSB_DPWR_L

TRUE FSB_CPURST_LTRUE VR_PWRGOOD_DELAYTRUE VR_PWRGD_CK410TRUE PM_STPPCI_LTRUE PM_STPCPU_LTRUE SB_RTC_RST_L

TRUE PM_RSMRST_L

TRUE PM_SB_PWROK

TRUE PCI_RST_LTRUE PM_LAN_ENABLETRUE CPU_DPSLP_L

TRUE TP_CPU_CPUSLP_L

TRUE TP_SB_SUS_CLKTRUE CPU_THERMTRIP_R

TRUE NB_CLK_DREFSSCLKIN_P

TRUE NB_CLK_DREFSSCLKIN_N

TRUE NB_CLK_DREFCLKIN_NTRUE NB_CLK_DREFCLKIN_PTRUE NB_CLK100M_GCLKIN_NTRUE NB_CLK100M_GCLKIN_PTRUE CLK_NB_OE_L

FSB_CLK_NB_NTRUE

TRUE TPM_LRESET_L

FSB_CLK_CPU_NTRUE

CPU_DPRSTP_LTRUE

PM_SLP_S4_LTRUE

IMVP_DPRSLPVRTRUE

TRUE LPC_AD

TRUE LPC_AD

TRUE FWH_INIT_L

TRUE INT_SERIRQ

PP3V3_S0TRUEPP2V5_D3CTRUE

TRUE =SMBUS_BATT_SDA

SMC_BS_ALRT_LTRUE

=PP5V_S0_FAN_LTTRUE

TRUE =SMBUS_BATT_SCL

TRUE =PPBATTPOS_G3H_BATT_CONN

PP3V3_S3ACTRUEPP1V2_S3TRUE

PP1V95_FWPHY_PLLVDDTRUEPP1V95_FWPHYTRUE

TRUE PP3V3_FWPHY_PLLVDDPP3V3_FWPHY_AVDDTRUEPP3V3_FWPHYTRUE

PCI_CLK_PORT80_LPCTRUE

TRUE SMC_TX_LSMC_MD1TRUE

TRUE SMC_TDOTRUE SMC_TRST_LTRUE DEBUG_RST_LTRUE SMC_TMS

TRUE PM_CLKRUN_L

FAN_RT_PWMTRUE

FAN_LT_TACHTRUETRUE FAN_LT_PWM

PP2V5_S0TRUE

TRUE FSB_SLPCPU_L

PP0V9_S0TRUE

PP1V2_D3CTRUE

PP1V5_S0TRUEPP1V5_S0_NBTRUE

PP1V2_S3TRUE

PP1V05_S0TRUE

TRUE PP3V3_S3

PPBUS_G3HTRUE

PP5V_S5TRUEPP5V_S3TRUE

PP5V_S0TRUEPP3V3_S5TRUE

PP1V8_D3CTRUEPP1V8_S3TRUE

PLT_RST_LTRUE

FSB_CLK_NB_PTRUE

CPU_STPCLK_LTRUE

FSB_CLK_CPU_PTRUE

P1V5P1V05S0_PGOODTRUE

PM_SLP_S5_LTRUE

TRUE PM_SLP_S3BATT

TRUE IMVP_VR_ON

TRUE GND

TRUE PM_DPRSLPVR

TRUE SMC_EXCARD_PWR_EN

LTUSB_OC_LTRUE

EXCARD_OC_LTRUE

ACZ_RST_LTRUE

=USB2_LT2_PTRUE=PCIE_MINI_R2D_NTRUE

PCIE_CLK100M_EXCARD_NTRUEPCIE_CLK100M_EXCARD_PTRUE

TRUE =PCIE_EXCARD_D2R_N

TRUE =PCIE_EXCARD_R2D_N=USB2_EXCARD_PTRUE

TRUE =USB2_EXCARD_N=USB2_LT_PTRUE=USB2_LT_NTRUE

ACZ_SYNCTRUE

LIO_PLT_RESET_LTRUE

TRUE EXCARD_CLKREQ_LSMC_EXCARD_CPTRUE

MINI_CLKREQ_LTRUESYS_ONEWIRETRUE

LIO_P5V_P3V3S3_ENTRUE

LIO_P5V_P3V3S0_EN_LTRUE

LT2USB_OC_LTRUE

ACZ_SDATAOUTTRUETRUE ACZ_SDATAIN

=SMBUS_LIO_SMC_SDATRUE

TRUE SMC_BC_ACOKTRUE PCIE_WAKE_L

TRUE ISENSE_CAL_EN

TRUE SV_SET_UPTRUE SMC_RX_LTRUE SMC_NMI

SMC_RST_LTRUE

SMC_TCKTRUE

SMC_TDITRUE

PM_SUS_STAT_LTRUE

TRUE =USB2_CAMERA_PTRUE =USB2_CAMERA_NTRUE =PP5V_S3_CAMERA

=PP1V8_S3_REGTRUE=PP1V05_S0_REGTRUE

TRUE =PPVCORE_S0_CPU

GND_INVERTERTRUE

INVERTER_PWMTRUE

PP5V_INVERTER_SWTRUETRUE PPBUS_S0_INVERTER

=GND_CHASSIS_INVERTERTRUE

PP5V_S3_CAMERA_FTRUE

TRUE GND

TRUE =PPVCORE_S0_GPU

TRUE PP5V_S0_ISENSECAL

TRUE FSB_A_LTRUE FSB_ADS_L

TRUE FSB_ADSTB_LTRUE

TRUE FSB_BREQ0_LTRUE FSB_BNR_L

TRUE FSB_D_LFSB_DBSY_LTRUE

TRUE TRUE FSB_DINV_LFSB_DRDY_LTRUEFSB_DSTBN_LTRUE TRUE

TRUE TRUE FSB_DSTBP_LFSB_HIT_LTRUE

TRUE FSB_HITM_LFSB_LOCK_LTRUE

TRUE FSB_REQ_L

TRUE DMI_N2S_PDMI_N2S_NTRUE

TRUE SB_CLK100M_SATA_NTRUE SB_CLK100M_SATA_P

TRUE USB_BT_P

TRUE P1V5S0_RUNSS

P1V8S3_FSETTRUE

TRUE GPUVCORE_FSET

P1V05S0_COMPTRUE

TRUE P2V5S3_MODE

P1V8S3_COMPTRUE

P1V2S3_RUNSSTRUETRUE P1V2S3_RT

TRUE P2V5S3_SHDNRT

GPUVCORE_COMPTRUE

IMVP6_RBIASTRUE

TRUE P5VS5_RUNSS

TRUE P3V3S5_COMP

TRUE P3V3S5_FSET

P1V05S0_FSETTRUE

P3V42G3H_FBTRUE

GPUBBP_ADJTRUE

TRUE USB_BT_N

TRUE TP_FW_CTLTRUE USB2_CAMERA_N_FTRUE USB2_CAMERA_P_F

87D6 12D6

67D1

12C6

87D6

87D6

87D6

66C8 53B4

69A6

53B5

60C6

55D7

77A7

87D6

12B6

12B4

12B4

12B4

60C6

60C6

60C6

81C4

51C5

87D6

66B8 60C6

60C6

60C6

52B3

60C6

87C6

68A6

52B3

53B5

55A6

72D8

12D4

87C6

7C4

7C4

7C4

7C4

87D6

87B4

53B4

53C4

53C4

53C4

51B7

52C6

51B5

43C8

67C3

87C6

87D6

12C4

61C7

87C6

34B4

34B4

61C7

51C5 53C5

53C5

53C5

53C5

67C3

68B2

52B2

53B4

53B4

53C4

82A4

87C6

52A2

61C8

52B3

87B4

87B4

52A2

52B2

87B4

87B4

52A2

48C3

53B5

52B2

53B5

53B5

53B5

52A2

67D8

9D7

67A6

12C4

87D6

12C4

87D6

87D6

7C3

87D6

7C3

87D6

7C3

7C3

87D6

87D6

87D6

12B4

50C6

48C6

48C6

50C6

48B3

57C7

50C6

48B3

48B3

48B6

51C7

51C7

51D7

51D7

67D3

67A1

26C5

52B2

67C6

68D5

68C5

50C6

48C6

50C6

48C4

51C7

61C7

26C1

70A5

40D5

42A8

66B5

21C4

22A6

12B4

11B5

26B5

26B8

33C4

33C4

26D4

51D7

26A6

37C2

51D7

21C4

34B4

34B4

34B2

34B2

34C4

34C4

33B4

34D3

60B7

34D3

21C4

41B6

87C6

51C7

51C7

52D3

51C7

66B5

82D7

68B2

52B2

67A1

68B2

67D6

53C5

51C7

53B4

52B2

53B4

53B4

52B2

51C5

67B6

12A4

67D6

82D7

67C6

67D6

67C1

67C1

67B1

82D7

26C3

34D3

21C4

34D3

51C5

61C7

23C3

51B7

48C3

48C3

48B3

48C6

50C6

48B6

48B6

50B6

50C6

48C6

48C6

48C6

48C6

48B3

48C3

48C3

51B7

48C3

51B7

48C3

48C3

48C3

48B3

48B3

48B6

51C5

39C6

55A8

23C3

51C7

53B5

52D6

52B2

52B2

51C5

45B3

45C3

67B1

67B8

65A2

8D7

79A6

55C7

7D8

12C4

7D8

12C4

12C4

7B4

12B4

7B4

12B4

7B4

7B4

12B4

12B4

12B4

12A4

22D2

22D2

34C3

34C3

66C6

63B7

66A6

48C6

34D4

34D4

48C6

21C7

48C3

48B6

27B6

27B6

27C3

22B3

21C5

21D4

21D4

53C4

53C4

23C5

51C5

54C5

54C5

54D5

48B6

67C1

68B8

48C6

6C3

48B6

6D5

58B3

68B2

26B1

9C1

14B7

26B1

67B6

39D5

23C3

33C5

5D4

78B7

78B7

78B7

78C7

78C7

78C7

7B3

14B6

7B3

7D6

14B6

23C5

23C8

23C8

21D6

23C1

23C3

22A6

23C3

7B3

21C4

6C7

21C2

14B4

14C4

14C4

14C4

14C4

14C4

14B6

12A6

26B1

7C6

7B3

23C3

61C7

21D4

21D4

21C4

23C8

5A4

67A6

27C1

51C5

58C7

27C1

68A2

67D1

5D4

38D3

6C5

38C6

38D5

6C5

34D6

47B5

51C1

51B5

51C1

26B1

51B5

23C8

58B3

58B6

58B6

66B5

7A3

66B5

67D6

66C5

67C6

5A4

67D6

67C3

55D3

52B5

67B1

66B5

67D3

67B6

67B6

22A6

12A6

7C8

7C6

66B3

23C3

41B5

51D7

14B7

48C3

6D3

6C3

21C7

6C3

48C6

34B3

34C3

48B6

48B6

6C3

6C3

6D3

6D3

21C7

26C1

34A3

48C3

34A3

48C3

6A2

6A2

6C3

21C7

21C7

27B3

48C3

23C8

51B7

23B6

47B5

51C1

51C3

51C5

51B5

23C5

6D3

6D3

45C3

64C1

55A4

8B5

79A5

79A5

79B5

79B5

6A6

45C5

55A5

7C8

7D6

7C8

7D6

7D6

7B3

7D6

7B3

7D6

7B3

7B3

7D6

7D6

7D6

7D8

14B4

14B4

21B6

21B6

6C2

62C4

71C7

65A7

41C4

63B6

71C7

61C7

62C5

65C6

65D6

65B7

66C3

71B7

6C2

37C3

45B5

45B5

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Chassis connection to be made at the mounting hole northwest of the DVI connector. Plated hole.

Base net is PM_SLP_S3_LS5V

Base net is PM_SLP_S4_L

Left CPU TM Hole

Frame holes

Thermal Module Holes

Lower Left GPU TM Hole

Ethernet Powr Management Support

USB Port "C" = Left USB 2.0 Port

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "B" = Trackpad (Geyser)

USB Port "D" = Camera

USB Port "F" = USB 1.1 Hub

USB Port "E" = ExpressCard

"ENET_LOWPWR_EN" are mutually-exclusive.NOTE: BOM options "USB_G_OC_PU" and

Right CPU TM Hole

Top GPU Right TM HoleTop CPU TM Hole

Add one through via per hole to GND or 2 blind vias per side per hole to GND

FireWire Aliases

NOTE: NB_CFG require test access

Inverter PWM Reset Alias

LEFT CLUTCH BARREL CABLING

LVDS Pull Down Aliases

USB Port "H" = 2nd Left USB 2.0 Port

USB Port "G" = Bluetooth (M13P)

Chassis connection to be made at the mounting hole southwest of the USB connector. Plated hole.

Chassis connection to be made at the mounting hole east of the LVDS connector

Chassis connection to be made on FW shell

Chassis connection to be made at the fan cutout near the right ALS. Not stuffed at Proto.

195R106

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

0

5%1/16WMF-LF402

402

5%1/16W

0

MF-LF

ENET_LOWPWR_EN

5%1/16W

0

402MF-LF

NO STUFF

0G-502620REMI-SPRING

NO STUFF

402X7R50V10%0.01UF

402X7R50V10%0.01UF

10%50VX7R402

0.01UF

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

50V10%

0.01UF

X7R402

50V

0.01UF10%X7R402

195R106

402X7R50V10%0.01UF

10%50VX7R402

0.01UF

0.01UF10%50VX7R402

0.01UF10%50VX7R402

0.01UF10%50VX7R402

HOLE-VIA-P5RP25

0.01UF10%50VX7R402

0.01UF10%50VX7R402

HOLE-VIA-P5RP25

SHLD-SM-LFOG-503040

HOLE-VIA-P5RP25 MF-LF402

0

1/16W5%

NO STUFF

Signal AliasesSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-7164 06004

876

GND_CHASSIS_ENET

VOLTAGE=0VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_DVI2=GND_CHASSIS_DVI4

=GND_CHASSIS_DVI3=GND_CHASSIS_DVI1

=GND_CHASSIS_FW_PORT2U=GND_CHASSIS_FW_PORT1=GND_CHASSIS_ENET

=GND_CHASSIS_LCD3=GND_CHASSIS_LCD4

=GND_CHASSIS_LCD2=GND_CHASSIS_LCD1

=GND_CHASSIS_RTUSB=GND_CHASSIS_FW_PORT2L=GND_CHASSIS_FW_EMI_R

MAKE_BASE=TRUE

GND_CHASSIS_LVDS

MIN_NECK_WIDTH=0.25 mmVOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mmGND_CHASSIS_USB

MAKE_BASE=TRUEVOLTAGE=0VMIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_DVI5

=GND_CHASSIS_3GPOWER

TP_CPU_A37_L

=GND_CHASSIS_CAMERA=GND_CHASSIS_INVERTERMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUEVOLTAGE=0VMIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_INVERTER

USB_HUB_NMAKE_BASE=TRUE

MAKE_BASE=TRUEUSB_BT_P

MAKE_BASE=TRUEUSB2_LT2_N

TP_USB2_3G_PMAKE_BASE=TRUE

TP_USB2_3G_NMAKE_BASE=TRUE

NC_CPU_A35_LNO_TEST=TRUEMAKE_BASE=TRUE

TP_CPU_APM0_L

TP_CPU_APM1_L

INVERTER_PLT_RST_L =INVERTER_PWM_PLT_RST_L

MAKE_BASE=TRUETP_NB_CFG





MAKE_BASE=TRUETP_SB_SUS_CLK

NB_CFG


SUS_CLK_SB

TP_CPU_A39_L

=GND_CHASSIS_LCBC_CONN

TP_CPU_A33_L

TP_CPU_A36_L

MAKE_BASE=TRUEPPFW_PORTA_VP_UF =PPFW_PORT1_VP

ENET_CTRL25

=USB2_3G_P

=USB2_EXCARD_N

=USB_HUB_N

=USB2_3G_N

USB_HUB_PMAKE_BASE=TRUE

=USB_HUB_P

LIO_P5V_P3V3S0_EN_L LIO_P3V3S0_EN_L

LIO_P5V_P3V3S3_EN LIO_P3V3S3_EN

=LVDS_PD_U_DATA_N LVDS_U_CLK_PMAKE_BASE=TRUE

MAKE_BASE=TRUELVDS_U_CLK_N

LVDS_U_DATA_NMAKE_BASE=TRUE

=LVDS_PD_U_DATA_PMAKE_BASE=TRUELVDS_U_DATA_P

=LVDS_PD_U_DATA_N LVDS_U_DATA_PMAKE_BASE=TRUE

MAKE_BASE=TRUELVDS_U_DATA_N

MAKE_BASE=TRUELVDS_U_DATA_P

MAKE_BASE=TRUELVDS_U_DATA_N

=LVDS_PD_L_DATA_N LVDS_L_DATA_PMAKE_BASE=TRUE

=LVDS_PD_L_DATA_P LVDS_L_DATA_NMAKE_BASE=TRUE

=LVDS_PD_L_DATA_NMAKE_BASE=TRUELVDS_L_CLK_P

=LVDS_PD_L_DATA_PMAKE_BASE=TRUELVDS_L_CLK_N

=LVDS_PD_L_DATA_N LVDS_L_DATA_NMAKE_BASE=TRUE

=LVDS_PD_L_DATA_PMAKE_BASE=TRUELVDS_L_DATA_P

=LVDS_PD_L_CLK_P

=LVDS_PD_L_CLK_N LVDS_L_DATA_PMAKE_BASE=TRUE

MAKE_BASE=TRUEUSB2_LT2_P TP_USB_H_P

USB_BT_NMAKE_BASE=TRUE

=USB_BT_P

MAKE_BASE=TRUEUSB2_EXCARD_N

=USB2_EXCARD_PMAKE_BASE=TRUEUSB2_EXCARD_P

=USB2_CAMERA_N USB2_CAMERA_NMAKE_BASE=TRUE

USB_G_N

USB_G_P

EXCARD_OC_LMAKE_BASE=TRUE

USB_E_OC_L

USB_E_P

USB_E_N

USB_D_N

UNUSED_USB_D_OC_LMAKE_BASE=TRUE

USB_D_OC_L

=USB2_CAMERA_P USB2_CAMERA_PMAKE_BASE=TRUE

=USB2_LT_NMAKE_BASE=TRUEUSB2_LT_N

=USB2_LT_P USB2_LT_PMAKE_BASE=TRUE

=USB_TRACKPAD_NMAKE_BASE=TRUEUSB_TRACKPAD_N

=USB_TRACKPAD_PMAKE_BASE=TRUEUSB_TRACKPAD_P

=RTUSB_OC_L RTUSB_OC_LMAKE_BASE=TRUE

=USB2_RT_NMAKE_BASE=TRUEUSB2_RT_N

USB_D_P

MAKE_BASE=TRUELTUSB_OC_L USB_C_OC_L

USB_C_N

USB_C_P

MAKE_BASE=TRUEUNUSED_USB_B_OC_L USB_B_OC_L

USB_B_P

USB_B_N

USB_A_OC_L

USB_A_N

=USB2_RT_P USB2_RT_PMAKE_BASE=TRUE

USB_A_P

SB_GPIO30

NO_TEST=TRUEMAKE_BASE=TRUE

NC_MEM_A_A


MAKE_BASE=TRUENO_TEST=TRUE

NC_MEM_B_A

TP_CPU_A32_L

TP_CPU_HFPLL

NB_CFG

MAKE_BASE=TRUEPCI_AD

NB_CFG

=PP1V95_FWPHY_CORE_LDO

NC_CPU_A32_LMAKE_BASE=TRUENO_TEST=TRUE

MEM_A_A

NB_CFG

NB_CFG

MEM_B_A

TP_CPU_SPARE4

NC_CPU_SPARE1NO_TEST=TRUEMAKE_BASE=TRUE


NC_CPU_EXTBREF


TP_CPU_SPARE1

TP_CPU_SPARE2NC_CPU_SPARE2NO_TEST=TRUEMAKE_BASE=TRUE

NC_CPU_HFPLLMAKE_BASE=TRUENO_TEST=TRUE

NC_CPU_SPARE0


TP_CPU_SPARE0

=RTALS_GAINRTALS_GAINMAKE_BASE=TRUE

MAKE_BASE=TRUENO_TEST=TRUE

NC_ENET_CTRL25

ENET_CTRL12MAKE_BASE=TRUENO_TEST=TRUE

NC_ENET_CTRL12

ENET_LOWPWR_EN

=PPFW_PORT2_VP

=PP3V3_FWPHY

=PP3V3_FWPHY_CORE

=PP3V3_FWLATEVG

=PP3V3_FWLATEVG_ACTIVE

=PP3V3_FWPHY_OSC

=PP1V95_FWPHY

MAKE_BASE=TRUESMC_RSTGATE_L

=PP3V3_FWPHY_REG

TP_CPU_A34_L

TP_CPU_A35_L

TP_CPU_A38_L


NC_CPU_APM0_LMAKE_BASE=TRUENO_TEST=TRUE

ALS_GAIN

NB_CFG

NB_CFG

TP_CPU_EXTBREF

=FW_PCI_REQ_L

=FW_PCI_GNT_L

=FW_PCI_IDSEL

=SMC_FWRSTGATE_L

=PP1V8_FWPHY_OSC

MAKE_BASE=TRUEPPFW_PORTB_VP_UF

NC_CPU_SPARE4MAKE_BASE=TRUENO_TEST=TRUE

VOLTAGE=1.95VMIN_LINE_WIDTH=0.38 mm

MAKE_BASE=TRUE

PP1V95_FWPHY

MIN_NECK_WIDTH=0.25 mm


PP3V3_FWPHYMIN_LINE_WIDTH=0.38 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

MAKE_BASE=TRUELT2USB_OC_L

=USB2_LT2_N

=USB2_LT2_P

=USB_BT_N


LVDS_L_DATA_NMAKE_BASE=TRUE

MAKE_BASE=TRUEPCI_REQ3_L

PCI_GNT3_LMAKE_BASE=TRUE

=GND_BATT_CHGND


VOLTAGE=0V

GND_CHASSIS_LIOFLEX_HOLE


GND_CHASSIS_BATTCONN_HOLEMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0VMAKE_BASE=TRUE

GND_CHASSIS_ODD_HOLE



GND_CHASSIS_LEFT_DIMM_HOLE


MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V

MIN_LINE_WIDTH=0.5 mmGND_CHASSIS_LNDACARD_HOLE

=LVDS_PD_U_DATA_P

=LVDS_PD_U_DATA_N

=LVDS_PD_U_DATA_P

=LVDS_PD_U_CLK_P

=LVDS_PD_U_CLK_N

TP_USB_H_N

SB_GPIO31

USB_F_N

USB_F_P

NC_CPU_APM1_L


NC_CPU_A37_L




MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUEVOLTAGE=0V

GND_CHASSIS_DVI_BOT

VOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmGND_CHASSIS_DVI_TOP

MAKE_BASE=TRUE

VOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmGND_CHASSIS_FANFRAME

ZT0600

ZT06031

ZT06021

R06001 2

R06901 2

R06011 2SH0601

1

C06131

2

C06191

2

C06151

2

ZT06121

ZT06111

ZT06101

C0600 1

2

C0602 1

2

ZT0601

C06121

2

C06141

2

C06161

2

C06111

2

C06101

2

ZT06131

C06181

2

C06171

2

ZT06141

SH06001

2

3

ZT06041

R06021 2

82C3

82C3

82C3

82B3

82C3

82C3

82C3

82C3

82C3

82C3

82C3

82C3

82C3

82C3

82C3

52B3

51B5

82C3

45C5

79A6

5A7

48C6

46B3

46B7

48C3

48C3

79D7

79D7

79D7

79D7

79D7

79D7

79D7

79D7

79D7

79D7

79D7

79D7

79D7

79D7

79D7

5A7

48C6

45C3

48C3 22D8

22D8

45B3

48C6

48C6

48C3 22D8

22D8

22D8

22D8

37C6

44B8

48C4

5A4

5A4

48C3

48C6

48C6

79D7

26D2

22D8

80A5

80A3

80A2

80B5

44A1

44C1

40B2

79C3

79B2

79D3

79D2

47B2

44A1

44A3

80A2

7B8

45B5

5B2

46C3

46C3

7B8

7B8

26B1 79A8

5B4

14C6

23C3

7B8

7B8

7B8

43B2 44D3

39C8

5C1

46A7

46B3

5C1 66C6

5C1 66A6

82B8 78B3

78B3

78B3

82B8 78B3

82C8 78B3

78B3

78B3

78B3

82C8 78A3

82C8 78A3

82C8 78A3

82D8 78A3

82D8 78A3

82D8 78A3

82C8

82C8 78A3

22C2

81A4

5C1

5B2

22C2

22C2

5C1 22C4

22C2

22C2

22C2

22C4

5B2

5C1

5C1

81C4

81C4

47C5

47B5

22C2

5C1 22C4

22C2

22C2

22C4

22C2

22C2

22C4

22C2

47B5 22C2

22C4

7C8

7B8

14C6

22A7

14C6

42C1

28C3

14C6

14C6

29C3

7B6

7B6

7B6

7B6

57C4

39C8

39B8

44B3

38D7

42C4

44A8

43B8

38D5

51D7

42C4

7B8

7B8

7B8

5C1

14C6

14C6

7B6

37D3

37D3

37B7

37A8

38B2

43A2

5C1

5B1

5B1

81A4

78A3

22B6

22B6

69A1

82B8

82B8

82C8

82B8

82B8

22C2

22C4

22C2

22C2

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

A7*

RSVD14RSVD15

BCLK1BCLK0

RSVD20

RSVD17RSVD18RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*TMS

TDO

TDI

TCK

PREQ*PRDY*

BPM3*

BPM1*BPM2*

BPM0*

HITM*

HIT*

TRDY*

RS2*RS1*RS0*

RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BPRI*

BNR*

ADS*

RSVD11

RSVD6RSVD7RSVD8

RSVD1RSVD2RSVD3RSVD4RSVD5

RSVD9RSVD10

SMI*

LINT0LINT1

STPCLK*

IGNNE*

FERR*

A20M*

ADSTB1*

A30*A31*

A27*A28*A29*

A26*A25*A24*

A22*A23*

A21*A20*A19*A18*A17*

REQ4*REQ3*

REQ1*REQ0*

REQ2*

ADSTB0*

A14*A15*A16*

A13*A12*A11*A10*A9*A8*

A6*A5*A4*A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1

ADDR GROUP0

CONTROL

XDP/I

TP S

IGNA

LS

PSI*SLP*

PWRGOOD

DPRSTP*

DPSLP*DPWR*

COMP2COMP3

COMP1COMP0

DSTBP3*DSTBN3*

DINV3*

D63*D62*D61*D60*D59*D58*D57*D56*D55*D54*

D52*D53*

D51*D50*D49*D48*

DINV2*

DSTBN2*D47*

DSTBP2*

D45*D46*

D44*D43*D42*D41*D40*D39*D38*D37*D36*D35*D34*D33*D32*

BSEL2

DSTBN1*

BSEL0BSEL1

TEST2

TEST1

DINV1*DSTBP1*

D31*D30*D29*

D26*D27*D28*

D24*D25*

D23*

D21*D22*

D20*D19*D18*

D16*D17*

DINV0*DSTBP0*DSTBN0*D15*D14*D13*D12*D11*D10*D9*D8*D7*

D6*D5*D4*D3*D2*D1*D0*

GTLREF

NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CPU IS HOTAND CPU VR TO INFORM

WITHOUT T-ING (NO

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

PLACE GND VIA W/IN 1000 MILS

FSB_IERR_L WITH A GNDPLACE TESTPOINT ON

LAYOUT NOTE: 0.5" MAX LENGTH

ICH7-M AND GMCH

TRACE LENGTH SHORTER THAN 0.5".

TRACE LENGTH SHORTER THAN 0.5".COMP0,2 CONNECT WITH ZO=27.4OHM, MAKELAYOUT NOTE:

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

CPU_PROCHOT_L TO SMC

SHOULD CONNECT TOPM_THRMTRIP#

STUB)

SPARE[7-0],HFPLL:ROUTE TO TP VIA AND

0.1" AWAY

1/16W402MF-LF

54.91%

MF-LF402

5%1/16W68

1/16W1%

402MF-LF

1K

1/16W1%

402MF-LF

2.0K 54.9

4021%

27.4

54.9

4021%

402

27.4

0

402

NOSTUFF

NOSTUFF

1K

MF-LF402

5%1/16W

MF-LF402

5%1/16W51

54.91%1/16WMF-LF402

54.9

4021%

1%402

54.9

54.9

4021%

BGA

YONAHCPU

OMIT

CPUYONAH

BGA

OMIT

SYNC_DATE=09/15/2006SYNC_MASTER=M59_MLB

87

051-7164 06004

7

CPU 1 OF 2-FSB

FSB_BPRI_LFSB_BNR_LFSB_ADS_L

CPU_PSI_LFSB_SLPCPU_LCPU_PWRGD

CPU_DPRSTP_LCPU_DPSLP_LFSB_DPWR_L

CPU_COMPCPU_COMP

CPU_COMPCPU_COMP

FSB_DSTBP_LFSB_DSTBN_L

FSB_DINV_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_LFSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_DINV_L

FSB_DSTBN_LFSB_D_L

FSB_DSTBP_L

FSB_D_LFSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

CPU_BSEL

FSB_DSTBN_L

CPU_BSELCPU_BSEL

CPU_TEST2

CPU_TEST1

FSB_DINV_LFSB_DSTBP_L

FSB_D_LFSB_D_LFSB_D_L


FSB_D_LFSB_D_L

FSB_D_L

FSB_D_LFSB_D_L


FSB_D_LFSB_D_L

FSB_DINV_LFSB_DSTBP_LFSB_DSTBN_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

CPU_GTLREF

FSB_A_L

TP_CPU_SPARE1TP_CPU_SPARE2

FSB_CLK_CPU_NFSB_CLK_CPU_P

TP_CPU_SPARE7

TP_CPU_SPARE4TP_CPU_SPARE5TP_CPU_SPARE6

TP_CPU_SPARE3

TP_CPU_SPARE0

TP_CPU_EXTBREF

PM_THRMTRIP_L

CPU_THERMD_NCPU_THERMD_PCPU_PROCHOT_L

XDP_DBRESET_LXDP_TRST_LXDP_TMSXDP_TDOXDP_TDIXDP_TCK

XDP_BPM_LXDP_BPM_LXDP_BPM_L

XDP_BPM_L

FSB_CPURST_L

FSB_LOCK_L

CPU_INIT_LFSB_IERR_L

FSB_BREQ0_L

FSB_DRDY_LFSB_DEFER_L

TP_CPU_HFPLL

TP_CPU_A37_LTP_CPU_A38_LTP_CPU_A39_L

TP_CPU_A32_LTP_CPU_A33_LTP_CPU_A34_LTP_CPU_A35_LTP_CPU_A36_L

TP_CPU_APM0_LTP_CPU_APM1_L

CPU_SMI_L

CPU_INTRCPU_NMI

CPU_STPCLK_L

CPU_IGNNE_LCPU_FERR_LCPU_A20M_L

FSB_ADSTB_L

FSB_A_LFSB_A_L

FSB_A_LFSB_A_LFSB_A_L


FSB_A_LFSB_A_L

FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L

FSB_REQ_LFSB_REQ_L

FSB_REQ_LFSB_REQ_L

FSB_REQ_L

FSB_ADSTB_L


FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L

FSB_A_LFSB_A_LFSB_A_LFSB_A_L

XDP_TCK

XDP_TDI

XDP_TMS

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

FSB_DBSY_L

XDP_BPM_L

=PP1V05_S0_CPUFSB_TRDY_LFSB_RS_L

FSB_HIT_LFSB_HITM_L

XDP_BPM_L

FSB_RS_LFSB_RS_L

R07021

2

R07041

2

R07051

2

R07061

2

R07191 2

R07181 2

R07171 2

R07161 2

R07301 2

R07071

2

R07121

2

R07031

2

R07201 2

R07211 2

R07221 2

U0700

N3P5P2L1P4P1R1

Y2U5R3W6

A6

U4Y5U2R4T5T3W3W5Y4

J4

W2Y1

L4M3K5M1N2J1

H1

L2

V4

A22A21

E2

AD4AD3AD1AC4

G5

F1

C20

E1

H5F21

A5

G6E4

D20

C4

B3

C6B4

H4

AC2AC1

D21

K3H2K2J3L5

B1F3F4G3

AA1

C3

B25

T22

D2F6D3C1AF1D22C23

AA4

C24

AB2AA3M4N5T2V3B2

A3

D5

AC5AA6AB3

A24A25

C7

AB5

G2

AB6

U0700

B22B23C21

R26U26U1V1

E22F24

J24J23H26F26K22H25

N22K25P26R23

E26

L25L22L23M23P25P22P23T24R24L26

H22

T25N24

AA23AB24V24V26W25U23U25U22

F23

AB25W22Y23AA26Y26Y22AC26AA24

AC22AC23

G25

AB22AA21AB21AC25AD20AE22AF23AD24AE21AD21

E25

AE25AF25AF22AF26

E23K24G24

J26

M26

V23

AC20

E5B5D24

H23

M24

W24

AD23

G22

N25

Y25

AE24

AD26A2

AE6

D6D7

C26

D25

67D6

67D6

11C5

67D6

67D6

11C5

11B3

11C5

11C5

11B3

9B7

11B3

11B3

9B7

87D6

8C7

9B7

9B7

8C7

87D6

87D6

87C6

61C7

87C6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

52C1

12C4

87D6

87D6

87D6

87C6

87C6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87C6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6 7D5

8C7

8C7

87D6

7D5

87D6

87D6

87D6

12C4

12C4

12A4

21C4

21C4

21C4

12B4

12B4

12B4

12B4

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B4

12B4

12B6

12B4

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12B4

12B4

12B4

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12B4

12B4

12B4

12C6

12C6

12C6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D4

34D3

34D3

21C2

52D3

26C6

11B3

11B3

11B3

87C6

87C6

87C6

87C6

11B5

12B4

87C6

12C4

12B4

87D6

87C6

87C6

87C6

21C4

87C6

87C6

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12A4

12A4

12B4

12B4

12A4

12C4

12D4

12D4

12C4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

11B3

11B3

11B3

7B6

7D5

7D5

12B4

87C6

7B6 87D6

87D6

12B4

12B4

87C6

87D6

87D6

12C4

5B7

5B7

61C7

5A4

5B4

5C4

5B4

5A4

87C6

87C6

87C6

87C6

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

34B6

5B7

34C6

34B6

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

87C6

5B7

6C7

6C7

5C4

5C4

6C7

6C7

6C7

14B6

10B6

10B6

52C1

11B4

11B3

7B8

11B5

7B8

7A8

11B3

11B3

11B3

11B3

5A4

5A7

21C4

87C6

5B7

5B7

12B4

6C7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6C7

21C4

21C4

21C4

5C4

21C4

21C2

21C4

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5A7

5A7

5A7

5A7

5A7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

7C6

7C6

7C6

7B5

7B6

7B5

5B7

11B3

7B5 12A4

12A4

5B7

5B7

11B3

12A4

12A4

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VSS_82VSS_83VSS_84VSS_85

VSS_87VSS_86

VSS_88VSS_89VSS_90

VSS_92VSS_91

VSS_93VSS_94VSS_95

VSS_97VSS_96

VSS_100

VSS_98VSS_99

VSS_102VSS_101

VSS_105

VSS_103VSS_104

VSS_106VSS_107

VSS_110VSS_109VSS_108

VSS_111VSS_112



VSS_120VSS_119

VSS_123

VSS_121VSS_122

VSS_124VSS_125

VSS_128

VSS_126VSS_127

VSS_129VSS_130

VSS_133

VSS_131VSS_132

VSS_134VSS_135

VSS_138

VSS_136VSS_137


VSS_143VSS_142

VSS_146

VSS_144VSS_145

VSS_147VSS_148


VSS_152VSS_153



VSS_161VSS_160

VSS_162

VSS_1VSS_2VSS_3

VSS_5VSS_4

VSS_6VSS_7

VSS_8

VSS_10VSS_9

VSS_11VSS_12

VSS_15

VSS_13VSS_14

VSS_16VSS_17VSS_18VSS_19VSS_20

VSS_23VSS_22VSS_21

VSS_24VSS_25

VSS_28VSS_27VSS_26

VSS_29VSS_30

VSS_33VSS_32VSS_31

VSS_34VSS_35

VSS_38VSS_37VSS_36


VSS_46

VSS_44VSS_45

VSS_47VSS_48

VSS_51

VSS_49VSS_50

VSS_52VSS_53

VSS_56

VSS_54VSS_55


VSS_63VSS_62

VSS_64VSS_65VSS_66

VSS_69VSS_68VSS_67

VSS_70VSS_71

VSS_74VSS_73VSS_72

VSS_75VSS_76

VSS_79VSS_78VSS_77

VSS_80VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66VCC_65

VCC_63VCC_62VCC_61

VCC_59VCC_60

VCC_58VCC_57VCC_56

VCC_54VCC_55

VCC_53

VCC_51VCC_52

VCC_49VCC_50

VCC_48VCC_47VCC_46

VCC_44VCC_45

VCC_43

VCC_41VCC_42

VCC_40VCC_39VCC_38

VCC_36VCC_37

VCC_33

VCC_35VCC_34

VCC_31VCC_32

VCC_29VCC_30

VCC_28

VCC_26VCC_27

VCC_23

VCC_25VCC_24

VCC_22VCC_21VCC_20

VCC_18VCC_19

VCC_17VCC_16VCC_15

VCC_13VCC_14

VCC_12

VCC_10VCC_11

VCC_8VCC_9

VCC_7

VCC_6VCC_5

VCC_3VCC_4

VCC_2VCC_1 VCC_68

VCC_69

VCC_71VCC_70

VCC_72

VCC_74

VCC_76VCC_75

VCC_78VCC_77

VCC_79

VCC_81VCC_80

VCC_84

VCC_82VCC_83

VCC_86VCC_85

VCC_87

VCC_89VCC_88

VCC_90VCC_91VCC_92

VCC_94VCC_93

VCC_95VCC_96VCC_97

VCC_99VCC_98

VCC_100

VCCP_1VCCP_2VCCP_3VCCP_4VCCP_5VCCP_6VCCP_7

VCCP_9VCCP_8

VCCP_11VCCP_10

VCCP_12VCCP_13VCCP_14

VCCP_16VCCP_15

VCCA

VID0VID1VID2VID3VID4VID5VID6

VSSSENSE

VCCSENSE

VCC_73(3 OF 4)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CPU_VCCSENSE_P/CPU_VCCSENSE_N USEZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

(CPU INTERNAL PLL POWER 1.5V)

TO TP_VSSSENSE WITH NO

LAYOUT NOTE:

PROVIDE A TEST POINT (WITH NO STUB)TO CONNECT A DIFFERENCTIAL PROBEBETWEEN VCCSENSE AND VSSSENSE AT THELOCATION WHERE THE TWO 54.9 OHM

SHOULD BE OF EQUAL LENGTHVCCSENSE AND VSSSENSE LINESLAYOUT NOTE:

STUB.

(CPU IO POWER 1.05V)

(CPU CORE POWER)

LAYOUT NOTE:

RESISTORS TERMINATE THE 55 OHMTRANSMISSION LINE

VID FOR CPU POWER SUPPLYIF NO USE, NEED PULL-UP ORPULL-DOWN

LAYOUT NOTE: CONNECT R0803

VCCA=1.5 ONLY

87B6 9C2

87B6 9C2

87B6 9C2

87B6 9C2

87B6 9C2

87B6 9C2

1/16W1%

402MF-LF

100

87B6 9C2

87B6 61A1

87B6 61B1

100

MF-LF402

1%1/16W

OMIT

BGA

YONAHCPU

OMIT

BGA

YONAHCPU

CPU 2 OF 2-PWR/GND

051-7164 06004

8 87

SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VIDCPU_VIDCPU_VIDCPU_VIDCPU_VIDCPU_VIDCPU_VID

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

R08031

2

R08021

2

U0700A4

B8

V25W1W4W23W26Y3Y6Y21Y24AA2

B11

AA5AA8AA11AA14AA16AA19AA22AA25AB1AB4

B13

AB8AB11AB13AB16AB19AB23AB26AC3AC6AC8

B16

AC11AC14AC16AC19AC21AC24AD2AD5AD8AD11

B19

AD13AD16AD19AD22AD25AE1AE4AE8AE11AE14

B21

AE16AE19AE23AE26AF3AF6AF8AF11AF13AF16

B24

AF19AF21AF24

C5C8C11

A8

C14C16C19C2C22C25D1D4D8D11

A11

D13D16D19D23D26E3E6E8E11E14

A14

E16E19E21E24F5F8F11F13F16F19

A16

F2F22F25G4G1G23G26H3H6H21

A19

H24J2J5J22J25K1K4K23K26L3

A23

L6L21L24M2M5M22M25N1N4N23

A26

N26P3

P6P21P24R2R5R22R25T1

B6 T4T23T26U3U6U21U24V2V5V22

U0700A7

B7

AF20

B9B10B12B14B15B17B18B20C9

A9

C10C12C13C15C17C18D9D10D12D14

A10

D15D17D18E7

E9E10E12E13E15E17

A12

E18E20F7

F9F10F12F14F15F17F18

A13

F20AA7

AA9AA10AA12AA13AA15AA17AA18AA20

A15

AB9AC10AB10AB12AB14AB15AB17AB18

AB20AB7

A17

AC7

AC9AC12AC13AC15AC17AC18AD7AD9AD10

A18

AD12AD14AD15AD17AD18AE9AE10AE12AE13AE15

A20

AE17AE18AE20AF9AF10AF12AF14AF15AF17AF18

B26

V6

N6R21R6T21T6V21W21

G21J6K6M6J21K21M21N21

AF7

AD6AF5AE5AF4AE3AF2AE2

AE7

67D6

67D1

11C5

67D1

55D7

11B3

55D7

55A6

9B7

55A6

9D7

7D5

9D7

8B5

7B6

67C6

8D7

5B2

7B5

9B7

5B2

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

4x 330uF. 20x 22uF 0805

VCCA (CPU AVdd) Decoupling

1x 470uF, 6x 0.1uF 0402

between CPU and NB

1x 10uF, 1x 0.01uF

Resistors to allow for override of CPU VIDWill probably be removed before production

VCCP (CPU I/O) Decoupling

CPU VCORE HF AND BULK DECOUPLING

NOTE: This cap is shared

NCNC

CPU VCORE VID Connections

6.3V20%

CERM805

22UF6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM805

22UF

6.3V20%

CERM805

22UF6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

0.1UF

CERM402

20%10V

470uF

CRITICALD2T

TANT2.5V20%

6.3V20%

CERM

22UF

805

6.3V20%

CERM

22UF

805

20%

CERM

22UF6.3V

805

6.3V20%

CERM

22UF

805

0.1UF

CERM402

20%10V

0.1UF

CERM402

20%10V

0.1UF

CERM402

20%10V

0.1UF

CERM402

20%10V

0.1UF

CERM402

20%10V

22UF

CERM

20%6.3V

805

16V

0.01UF

CERM402

20%

X5R

10uF20%

6.3V

603

SM-LF1/16W

5%0

SM-LF1/16W

5%0330UF20%

2.5VPOLYD2T

CRITICAL CRITICAL

D2TPOLY2.5V20%330UF 330UF

20%2.5VPOLYD2T

CRITICAL CRITICAL

D2TPOLY2.5V20%330UF

CPU Decoupling & VID

051-7164


06004

9 87

IMVP6_VIDIMVP6_VIDIMVP6_VID

CPU_VIDCPU_VIDCPU_VID

IMVP6_VIDIMVP6_VIDIMVP6_VIDIMVP6_VID

CPU_VIDCPU_VIDCPU_VIDCPU_VID

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

C09081

2

C09071

2

C09191

2

C09181

2

C09061

2

C09041

2

C09161

2

C09141

2

C09031

2

C09021

2

C09011

2

C09131

2

C09121

2

C09111

2

C09001

2

C09101

2

C09361

2

C0935 1

2 3

C09051

2

C09091

2

C09151

2

C09171

2

C09371

2

C09381

2

C09391

2

C09401

2

C09411

2

C09811

2

C0980 1

2

RP0990

1

2

3

4

8

7

6

5

RP0991

1

2

3

4

8

7

6

5

C09501

23

C09521

23

C09531

23

C09541

23

67D6 11C5

67D1

11B3

55D7

8C7

55A6

7D5

8D7

61C7

61C7

61C7

87B6

87B6

87B6

61C7

61C7

61C7

61C7

87B6

87B6

87B6

87B6

7B6

67C6

8B5

5C4

5C4

5C4

8B7

8B7

8B7

5C4

5C4

5C4

5C4

8B7

8B7

8B7

8B7

7B5

8B7

5B2

IO

IO

IN

OUT

GND

VDD

SDATASCLK

THM*

ALERT*/

D+

D-

THM2*

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PLACE U1001 NEAR THE U1200

CPU ZONE THERMAL SENSOR

ADD GND GUARD TRACE

FOR CPU_THERMD_P AND

CPU_THERMD_N

LAYOUT NOTE:

10 MIL SPACING

LAYOUT NOTE:

10 MIL TRACE

LAYER.

CPU_THERMD_N ON SAME

ROUTE CPU_THERMD_P AND

(TO CPU INTERNAL THERMAL DIODE)

(TC0D) 0.001UF10%

402CERM50V

0.1UF

X5R16V10%

402

CRITICAL

TMP401MSOP

MF-LF402

1/16W5%10K

1/16W5%

402

10K

MF-LF

499

1%1/16WMF-LF402

499

402MF-LF1/16W1%


051-7164 06004

10 87

CPU MISC1-TEMP SENSOR

THRM_ALERT_L

THRM_ALERTSMB_THRM_CLK

SMB_THRM_DATA

THRM_CPU_DX_N

CPU_THERMD_N

THRM_CPU_DX_PCPU_THERMD_P

=PP3V3_S0_THRM_SNR

C10011

2

C1002 1

2

U10016

32

5

87

4

1

R10051

2

R10061

2

R10011 2

R10021 2

27D1

27D1

7C6

7C6

67B3

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IO

IO

IO

IO

IO

IO

OUT

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

ITP TCK SIGNAL LAYOUT NOTE:

CONNECTORS FBO PIN.

518S0320

(TCK)

(FBO)

CPU ITP700FLEX DEBUG SUPPORT

(DEBUG PORT ACTIVE)(DBR#)

(DBA#)

NC

NC

NCTO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC(AND WITH RESET BUTTON)

(DEBUG PORT RESET)

(FROM CK410M HOST 133/167MHZ)

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEXROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO CPUS

MF-LF

22.6

1%1/16W402

ITP

ITP

402

1%

22.6

1/16WMF-LF

54.91/16W1%

402MF-LF

ITP

402X5R16V10%0.1UF

1/16W240

402MF-LF

5%

F-RT-SM52435-2872

CRITICAL

ITPCONN

1/16W402

54.91%

MF-LF

680

402

5%1/16WMF-LF

CPU ITP700FLEX DEBUG

051-7164 06004

11 87

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

ITPRESET_L

XDP_DBRESET_L

ITP_TDO

CPU_XDP_CLK_P

XDP_TCKXDP_BPM_L

XDP_BPM_L

XDP_BPM_L

XDP_BPM_L

XDP_BPM_L

XDP_TRST_L

CPU_XDP_CLK_N

XDP_TMS

=PP1V05_S0_CPU

=PP3V3_S5_SB_PM

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L

FSB_CPURST_L

=PP1V05_S0_CPU

R11001 2

R11021 2

R11031

2

C11001

2

R11041

2

J1101

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

R11011

2

R11061

2

67D6

67D6

11B3

11C5

9B7

9B7

8C7

87D6

8C7

11B3

7D5

67D3

11B3

12C4

7D5

26C6

87C6

7C6

87C6

87C6

87C6

87C6

87C6

87C6

7C6

7B6

26C5

7C6

7C6

87C6

7D6

7B6

87C6

7C6

34D3

7A8

7C6

7C6

7C6

7C6

7C6

7C6

34D3

7B8

7B5

23D1

7C6

7B8

7A8

7C6

5A4

7B5

IO

IO

IO

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

IO

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IN

IO

IN

IO

IO

HD4*

HD6*

HD16*

HTRDY*HSLPCPU*

HRS1*HRS0*

HHITM*

HLOCK*

HHIT*

HDSTBP2*HDTSBP3*

HDSTBP1*HDSTBP0*

HDSTBN3*

HDSTBN1*HDSTBN2*

HDSTBN0*

HDINV2*HDINV3*

HDINV1*HDINV0*

HDVREF

HDRDY*

HDPWR*HDEFER*

HDBSY*HCPURST*HBREQ0*HBPRI*HBNR*

HAVREF

HCLKIN*HCLKIN

HYSWING

HYRCOMPHYSCOMP

HXSWINGHXSCOMPHXRCOMP

HA13*

HADS*HADSTB0*

HD3*HD2*HD1*HD0*

HD63*HD62*HD61*HD60*HD59*HD58*HD57*HD56*HD55*HD54*HD53*HD52*HD51*HD50*HD49*HD48*HD47*HD46*HD45*HD44*HD43*HD42*HD41*HD40*HD39*HD38*HD37*HD36*HD35*HD34*HD33*HD32*HD31*

HD29*HD28*HD27*HD26*HD25*HD24*HD23*HD22*HD21*HD20*HD19*HD18*HD17*

HD15*

HD10*HD11*HD12*HD13*HD14*

HD5*

HD7*HD8*HD9*

HA30*HA29*HA28*HA27*HA26*HA25*HA24*HA23*

HA31*

HA20*HA19*HA18*

HA16*HA15*HA14*

HA21*HA22*

HA17*

HA9*HA8*HA7*HA6*HA5*HA4*HA3*

HA10*HA11*HA12*

HADSTB1*

HREQ0*HREQ1*HREQ2*HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

402X5R16V10%

0.1uF 2001%1/16WMF-LF402

1001%1/16WMF-LF402

54.91%

1/16WMF-LF402

402MF-LF1/16W

1%24.9

2211%1/16WMF-LF402

1%1/16WMF-LF402

100 0.1uF

402X5R16V10%

402X5R16V10%0.1uF

2211%1/16WMF-LF402

54.91%

1/16WMF-LF402

1%1/16WMF-LF402

100

402MF-LF1/16W

1%24.9

BGA

NB

945GM

OMIT

SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006

NB CPU Interface

06004

12 87

051-7164

FSB_D_L

FSB_DSTBN_LFSB_DSTBN_L

FSB_DSTBP_LFSB_DSTBP_LFSB_DSTBP_L

FSB_DINV_L

FSB_DSTBN_L

FSB_DINV_LFSB_DINV_L

NB_FSB_VREF

FSB_D_LFSB_D_L



FSB_D_L

FSB_D_L

FSB_D_L

FSB_TRDY_LFSB_SLPCPU_L

FSB_RS_LFSB_RS_L

FSB_HITM_LFSB_LOCK_L

FSB_HIT_L

FSB_DSTBP_L

FSB_DSTBN_L

FSB_DINV_L

FSB_DRDY_LFSB_DPWR_LFSB_DEFER_LFSB_DBSY_LFSB_CPURST_LFSB_BREQ0_LFSB_BPRI_LFSB_BNR_L

FSB_CLK_NB_NFSB_CLK_NB_P

NB_FSB_YSWING

NB_FSB_YRCOMPNB_FSB_YSCOMP

NB_FSB_XSWINGNB_FSB_XSCOMP

FSB_A_L

FSB_ADS_LFSB_ADSTB_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_L


FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L

FSB_A_L



FSB_A_LFSB_A_L

FSB_A_L

FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L


FSB_ADSTB_L

FSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_L

FSB_D_L

FSB_REQ_L

FSB_RS_L

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

NB_FSB_XRCOMP

C1211 1

2

R12111

2

R12101

2

R12201

2

R12211

2

R12251

2

R12261

2

C12261

2

C12361

2

R12351

2

R12301

2

R12361

2

R12311

2

U1200

H11

J12

G14

D9

J14

H13

J15

F14

D12

A11

C11

A12

A13

E13

G13

F12

B12

B14

C12

A14

H9

C14

D14

C9

E11

G11

F11

G12

F9

E8

B9

C13

J13

C6

F6

C7

AG2

AG1

B7

F1

J1

K7

J8

H4

J3

K11

G4

T10

W11

T3

U7

H1

U9

U11

T11

W9

T1

T8

T4

W7

U5

T9

J6

W6

T5

AB7

AA9

W4

W3

Y3

Y7

W5

Y10

H3

AB8

W2

AA4

AA7

AA2

AA6

AA10

Y8

AA1

AB4

K2

AC9

AB11

AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

G1

AB5

AD10

AD4

AC8

G2

K9

K1

A7

C3

J7

W8

U3

AB10

J9

H8

K4

T7

Y5

AC4

K3

T6

AA5

AC5

K13

D3

D4

B3

D8

G8

B8

F8

A8

B4

E6

D6

E3

E7

E1

E2

E4

Y1

U1

W1

67D6

67D6

67D6

34C8

34C8

34C8

34C6

34C6

34C6

34B8

34B8

34B8

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87C6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87D6

87C6

87D6

87D6

87D6

87D6

87D6

87D6

19D7

19D7

19D7

7C4

7C3

7B3

7B4

7C3

7B3

7C4

7C4

7B4

7C3

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7A3

7D6

7D6

7D6

7C4

7B4

7B3

34D3

34D3

7D8

7D6

7D8

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7C4

7C4

7C4

7C4

7C4

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7D8

7D8

7D8

7C8

7C8

7C8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7C8

7D8

7D8

7D8

7D8

7B4

7D8

12C2

12C2

12B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5A4

5B7

5A7

5B7

5B7

5B7

5B7

5B4

5C4

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5B7

5A7

5A7

5A7

5A7

5B7

5A7

12A7

12B7

12A7

CRT_BLUE*

CRT_BLUE

CRT_GREEN*CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNCCRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF

TV_IRTNA

TV_DACB_OUT

TV_DACC_OUT

TV_DACA_OUT

LB_DATA2LB_DATA1LB_DATA0

LB_DATA2*LB_DATA1*LB_DATA0*

LA_DATA2LA_DATA1LA_DATA0

LA_DATA2*LA_DATA1*LA_DATA0*

LB_CLKLB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBGL_IBG

L_DDC_CLKL_DDC_DATA

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN0EXP_A_RXN1EXP_A_RXN2EXP_A_RXN3EXP_A_RXN4EXP_A_RXN5EXP_A_RXN6EXP_A_RXN7

EXP_A_RXN8EXP_A_RXN9EXP_A_RXN10EXP_A_RXN11EXP_A_RXN12EXP_A_RXN13

EXP_A_RXN15EXP_A_RXN14

EXP_A_RXP0EXP_A_RXP1EXP_A_RXP2

EXP_A_RXP4EXP_A_RXP3





EXP_A_RXP15

EXP_A_TXN1EXP_A_TXN0


EXP_A_TXN6EXP_A_TXN5EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8EXP_A_TXN9EXP_A_TXN10EXP_A_TXN11EXP_A_TXN12


EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2EXP_A_TXP1

EXP_A_TXP3EXP_A_TXP4EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6


EXP_A_TXP12EXP_A_TXP11


L_CLKCTLB

L_BKLTEN

L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IO

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN#SDVO_INT#

SDVO_TVCLKINSDVO_INTSDVO_FLDSTALL

SDVOB_GREENSDVOB_RED

SDVOC_CLKNSDVOC_BLUE#SDVOC_GREEN#SDVOC_RED#SDVOB_CLKNSDVOB_BLUE#SDVOB_GREEN#SDVOB_RED#

SDVOB_CLKPSDVOB_BLUE

SDVOC_REDSDVOC_GREENSDVOC_BLUESDVOC_CLKP

Otherwise, tie VCCD_LVDS to GND also.

LVDS Disable

VCCD_LVDS must remain powered with proper decoupling.

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

filtering components. Unused DAC outputs should

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

Component: DACA, DACB & DACC

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

connect to GND through 75-ohm resistors.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can omit

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

TV-Out Signal Usage:

Composite: DACA only

TV-Out Disable

CRT Disable

Can leave all signals NC if LVDS is not implementedTie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

OMIT

945GMNBBGA

24.91%1/16WMF-LF402

NB PEG / Video InterfacesSYNC_DATE=09/15/2006SYNC_MASTER=M59_MLB

13 87

06004051-7164

TV_DACA_OUTTV_DACB_OUTTV_DACC_OUT

TV_IREF

TV_IRTNATV_IRTNB

TV_IRTNC

PEG_D2R_N

PEG_D2R_N

PEG_D2R_N

CRT_BLUE_LCRT_BLUE

CRT_GREEN_LCRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED_L

CRT_DDC_DATA

CRT_IREF

LVDS_B_DATA_PLVDS_B_DATA_PLVDS_B_DATA_P

LVDS_B_DATA_NLVDS_B_DATA_NLVDS_B_DATA_N

LVDS_A_DATA_PLVDS_A_DATA_PLVDS_A_DATA_P

LVDS_A_DATA_NLVDS_A_DATA_NLVDS_A_DATA_N

LVDS_B_CLK_PLVDS_B_CLK_NLVDS_A_CLK_PLVDS_A_CLK_N

LVDS_VDDEN

LVDS_VREFLLVDS_VREFH

TP_LVDS_VBGLVDS_IBG

LVDS_DDC_CLKLVDS_DDC_DATA

PEG_COMP

PEG_D2R_NPEG_D2R_NPEG_D2R_NPEG_D2R_NPEG_D2R_NPEG_D2R_NPEG_D2R_N

PEG_D2R_N

PEG_D2R_NPEG_D2R_NPE

14465_051-7164 M57 TRUCKEE

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Transcript of 14465_051-7164 M57 TRUCKEE