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9/15 2Figure 11.17 A 2M+N-bit memory chip organized as an array of 2M rows 2N columns.

MemorySRAM

organization

• organized as an array of 2M rows 2N columns• Each chip can be

organized 1-bit, 4, 8 or 16-bit wide

• Eg 64M-bit would be 64M x 1 226 bit address

• Storage cells organized as a square array

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Figure 11.23 A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by

using the “dummy cell” arrangement shown in Fig. 11.25.

SRAM cellBuilt with CMOS transistorsUsed in Cache

Sense Amps are used to detect “sense” bit lines that

have small signal values

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Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

NMOS transistor structureSource (S), Drain (D), Gate (G)L channel length, W width of transistor

NMOS transistor cross-section

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Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

NMOS transistor+ve Gate (G) voltage n-channel

NMOS Transistor•N-Channel MOSFET•Built on p-type substrate•MOS devices are smaller than BJTs•MOS devices consume less power than BJTs

source

drain

gate

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Figure 4.4 iD–vDS characteristics of MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.

NMOS transistor iD – VDS +ve VGS > Vt & small VDS ===> resistive device

iD

VDS

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Figure 4.3 NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity).

NMOS transistor+ve VGS > Vt & small VDS ===> acts like resistorChannel induced

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Figure 4.5 Operation enhancement NMOS transistor as vDS is increased. The induced channel acquires tapered shape, its resistance increases as vDS increased. Here vGS is kept constant at a value > Vt.

NMOS transistor+ve VGS > Vt & increase VDS ===> resistance increases

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Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

NMOS transistor id – VDS characteristic+ve VGS …. increase VDS

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Threshold Voltage VtValue of VG for which channel is “inverted

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Characteristics of VT

•Inverting substrate from p-type to n-type inversion layer in channel•Controlled by inversion in channel•Adjusted by implantation of dopants into the channel•Can be positive or negative•Influenced by the body effect

threshold voltage VT (or Vt )

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Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant.

NMOS circuit symbols(c) Is most common

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Figure 4.11 (a) n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.

NMOS transistor, 3 regionsCircuit &ID – VDS characteristicFor Different VGS

Cutoff VGS < Vt

Triode VGS > Vt, small VDS

Saturation; large VDS, flat ID

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Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal.

P-channel MOSFET PMOS

(c)most common symbol

(c)Circuit, with V & I

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Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

CMOS structure, today’s ICsboth NMOS & PMOS transistorsPMOS formed in an n-well

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Why CMOS

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• Advantages• Virtually, no DC power consumed• No DC path between power and ground –

VDD to load OR load to Gnd

• Excellent noise margins (VOL=0, VOH=VDD)

• Inverter has sharp transfer curve • Drawbacks• Requires more transistors• Process is more complicated• pMOS size larger to achieve electrical

symmetry

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Figure 4.53 The CMOS inverter.

Digital CMOS Inverter (4.10)

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Figure 1.29 The VTC is approximated by three straight line segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).

Inverter Transfer CharacteristicVTC = voltage transfer characteristic

Ideal inverter

Typical inverter

Voh = output high; Vol = output low; Vil = max input interpreted as “0”; Vih = min input interpreted as “1”;

Voh

Vol

Vil Vih

Noise marginsNML NMH

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Figure 1.32 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter studied in Section 4.10.

CMOS inverter implementationThe most common inverter

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Figure 4.56 The voltage transfer characteristic of the CMOS inverter.

CMOS Inverter – Xfer Curve

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Figure 10.19 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load NMOS inverter.

Other Inverter ImplementationsAll NMOS - Not very popular -- FYI

(a) pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter.

© The depletion-load NMOS inverter.

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