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SoC (DSP+ARM) Platform

SungKyunKwan UniversityVADA Lab.

(2003.12.29)

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1.Multiprocessor SoC 설계 Platform• 성능 개선과 표준 변동에 능동적으로 대처

• Modular, Flexible and Scalable Architecture

• HW/SW partitioning

2. Multiprocessor SoC Platform test• DVB-T

3. Tools• Seamless (Mentor)

Abstract

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SoC (DSP+ARM) Platform

ARM920T DMA

DSP(Teaklite)

DPRAM

Shared memory

IP

AMBA

Communication interface & Dynamic memory management unit

Arbiter/Decoder

BIU/Decoder

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ARM Platform

AMBA BUS(APB)

Arbiter

Wrapper Interface

DMAARM920T Core

Decoder On chip RAM

AMBA BUS(AHB)Memory

Controller

ExternalBus

Interface(EBI) B

rid

ge

Timer

InterruptController

ROM

SRAM

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DSP Platform (1)

`

TeakLiteCore

P RAM

X RAM

Y RAM

BIU

AHBbus

Z BUS

ICU

DMMU

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DSP Platform (2)

X RAM( 4 K-words )

Y RAM( 4 K-words )

...

Peripheral

IP

Shared Memory

...

Boot Code( 1 K-words )

Interrupt vectors

…

ProgramMemory

0xFFFF

0x0FFF

0xF000

0x00000x0000

0xFFFF

0x0016

Program Memory Map Data Memory Map

Z space

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Communication Interface & DMMU

ARM

DMA

DPRAM

Communication interface & DMMU

Communication control logic

Address translation logic

Sharedmemory

IPs

BIU

DSP

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ARM Platform (1)

Arbiter

• Only one bus master has access to the bus

• Each bus master requests control of the bus

• Arbiter decides which has the highest priority and issues a grant signal

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Decoder

• The system decoder is used to decode the address bus

• Generate select lines to each of the system bus slaves or masters

ARM Platform (2)

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ARM Platform (3)

Default slave

• The default slave is used to respond to transfer that are made to undefined regions of memory map

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ARM Platform (4)

AMBA Bus (Master to slave multiplexer)

• The master to slave multiplexor is used to connect all of the system bus masters to the bus slaves, using the current HMASTER number to select the bus master outputs to use.

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ARM Platform (5)

AMBA Bus (Slave to master multiplexer)

• The slave to master multiplexor is used to connect the read data and response signals of the system bus slaves to the bus masters, using the current HSELx outputs to select the bus slave outputs to use.

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ARM Platform (6)

ARM920T Wrapper

• The ARM920T AHB wrapper interfaces between the ARM920T core and AHB bus.

ARM920Tcore

ARM920TWrapSM

ARM920TWrapMaster

ARM920TWrapSlave

AMBA(AHB)

ASB Master AHB Master

ASB Slave AHB Slave

ARM920T Wrapper

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ARM Platform (7)

ARM920T Wrapper

ARM920TWrapSM

• Converts the ASB accesses form the core into pseudo-AHB accesses

• Main state machine

• Address generation

ARM920TWrapMaster

• Converts the pseudo-AHB accesses form ARM920TSM into true-AHB accesses

• Error control (Holding, Error report to ARM920T core)

ARM920TWrapSlave

• Converts incoming AHB accesses into ASB accesses to the ARM920T core

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DMA_TOP_Module

Slave interface

DMA request & response interface

Interrupt request

Control logic & Register bank

Channel logic & Register bank

Master interface

INTERRUPT

HRDATA_DMA

HCLK

HTRANS_ARM

HSELDMA

HWRITE_ARM

HREADY

HADDR_ARM

HRESETn

HWDATA_ARM

HRESP_DMA

HREADY_DMA

DMA_REQ

DMA_WRITE

DMA_LOCK

DMA_RDATA

DMA_TRANS

DMA_BURST

DMA_WDATA

HREADY

DMA_BUSREQ

DMA_GRANT

HRESP

DMA_ADDR

DMA_SIZE

DMA_PROT

Direct Memory Access Controller Peripheral-to-Memory, Memory-to-Peripheral, Peripheral-to-Peripheral, and Memory-to-Memory transactions.

ARM Platform (8)

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개발 일정

내용기간 ( 2004 년 1 월 ~ 2004 년 12 월 )

1 2 3 4 5 6 7 8 9 10 11 12

1ARM platform 구현 및 test(APB, Peripheral, memory controller, EBI)

　 　 　 　 　 　 　 　 　 　 　　

2DSP platform 구현 및 test(BIU, decoder, memory)

　 　 　 　 　 　 　 　 　 　 　　

3 Communication Interface & DMMU 　 　 　 　 　 　 　 　 　 　 　　

41 차년도 연차보고서Multiprocessor Platform 기본 동작 test

　 　 　 　 　 　 　 　 　 　 　　

5 HW/SW partitioning block test 　 　 　 　 　 　 　 　 　 　 　　

6Multiprocessor platform 에 DVB-T 실장

test 진행 및 성능 평가 　 　 　 　 　 　 　 　 　 　 　　

7Multiprocessor (Arm+DSP) platform 성능

개선 작업 　 　 　 　 　 　 　 　 　 　 　　

8성능 개선된 Multiprocessor platform 에DVB-T 실장 test 진행2 차년도 연차보고서 작성

　 　 　 　 　 　 　 　 　 　 　　

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참고문헌

1. M. Shalan and V. Mooney, "Hardware Support for Real-Time Embedded Multiprocessor System-on-a-Chip Memory Management," CODES'02, pp 79-84, May 2002

2. Baghdadi, A.; Lyonnard, D., Zergainoh, N.-E., Jerraya, A.A. “An efficient architecture model for systematic design of application-specific multiprocessor SoC” DATE, 2001. pp 55 -62 , March 2001

3. Gharsalli, F., Lyonnard, D., Meftali, A., Rousseau, F., Jerraya, A.A, “Unifying memory and processor wrapper architecture in multiprocessor SoC design”, ISSS 2002, Page(s): 26 -31, Oct, 2002

4. Christou, C.S. “Fast computations on a low-cost DSP-based shared-memory multiprocessor system” Electronics, Circuits and Systems, 17-20, Page(s): 189 -192. Dec. 2000

5. www.arm.com

6. www.parthusceva.com

7. http://tima-cmp.imag.fr/Homepages/jerraya/jerraya.html

8. http://www.aijisystem.com/index_korea.htm, “scorpio user’s manual”