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Transcript of 1 Sequential logic networks State-machine structure (Mealy) typically edge-triggered D flip-flops...
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Sequential logic networks
State-machine structure (Mealy)
typically edge-triggered D flip-flops
output depends onstate and input
V. Sequential network design
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Sequential logic networks
State-machine structure (Moore)
output dependson state only
typically edge-triggered D flip-flops
V. Sequential network design
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Sequential logic networks
Q
Q’C
D Q
Q’C
S
R
Q
Q’C
J
K
Characteristic Table
S R q Q0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 1 0 0 1 1 -- --
J K q Q0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 1 0 0 1 1 1 0
D q Q0 0 0 1 1 0 1 1
0 0 1 1
Characteristic Equation Q = D
SRq 00 01 11 10
0
1 1
d
d 1
1
Q = S + R’q
JKq 00 01 11 10
0
1 1
1
1
1
Q = Jq’ + K’q
Transition Table(Excitation Table)
q Q D0 0 0 1 1 0 1 1
0 1 0 1
q Q S R0 0 0 1 1 0 1 1
0 d 1 0 0 1d 0
q Q J K0 0 0 1 1 0 1 1
0 d 1 d d 1d 0
D Flip flop S-R Flip flop J-K Flip flop
q : Current state
Q : Next state
V. Sequential network design
Flip Flop : summary
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Sequential logic networks
Characteristic table : For each input and state combination, define the next state of the flip flopCharacteristic equation: Define the next state (Q) as a function of current state and input to the flip flopTransition table (excitation table): For each transition type, define the inputs that cause the transition
V. Sequential network designFlip Flop : summary
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Sequential logic networks
Step 1: Start from state diagram or word description
Step 2: Construct a State/Output table
Moore machine: one output per state (one output column)
Mealy machine: One output per state and for each input combination (one output column per input combination)
Step 3: Reduce the number of states in State/output table by removing redundant states (a state is redundant if for the same input combinations) it has the same next state and output as another state.
Step4: Encode the states in binary (for n states, log2n bits are required). Each bit in the code represents a flip flop.
Step5: Substitute corresponding binary codes to states in the State/Output table
Step6: Separate the state table into flip flop next state maps (one map for each bit or flip flop)
Step7: Use the flip flop next state map to derive flip flop excitation maps (this step depends on the type of flip flop used in the design)
Step8: Use the flip flop excitation maps to determine excitation equations for the flip flop (these equations define the input logic of the flip flop)
Step 9: Use the State/Output table to define the output logic circuit
Step10: Draw the circuit, including flip flop, flip flop input circuits and output circuit.
V. Sequential network designMajor design steps
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Sequential logic networks
Example 1
Step1: Problem Description (Word description)
Design a sequential machine that detects a 01 sequence. The detection of sequence sets the output, Z=1, which is reset (Z=0) only by a 00 input sequence
Note: The input is scan one bit at a time
V. Sequential Network Design
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Sequential logic networks
Example 1: STEP 1
Step1: State Transition Diagram of the sequential machine:
Recall that a State Transition Diagram consists of : States (representated by circles) Transitions (represented as arcs) between states Transitions are labelled by input that cause them Output are associated with
– input labels (MEALY MACHINE)
– State labels (MOORE MACHINE)
V. Sequential Network Design
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Sequential logic networks
Example 1: STEP1V. Sequential Network Design
State diagram of example 1 (Mealy Machine):
0/0
1/1
0/1
1/0 A
State Description: A : initial state (sequence does not begin)
B
0/0
B : 0 is detected, expecting a 1
C
1/1
C : 01 sequence detected, output set to 1
Must detect a 00 to reset output to 0First 0 detected, go to B to wait for second 0
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Sequential logic networks
Example 1: STEP 2V. Sequential Network Design
For each (current state, input) pair, specify:•Next State•Output
State/Output table (Mealy Machine)
CSX=0
A B AB B CC B C
0 1
1 1
X= 1 X=0 X= 1
0 0
NS Output
0/0
1/11/0 A B
0/0
C
1/1
0/1
State/Output table
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Sequential logic networks
Example 1: STEP2V. Sequential Network Design
State diagram (Moore Machine):
0
1
1 A,0 B,0
0
C,1
1
D,1 00
1
A: Waiting for start of sequence 01 and output 0B: 0 is detected, wait for 1 and output 0C: Sequence 01 is detected, output 1 and wait for 00 to reset output
D: Start of 00 is detected; wait for the final 0 to reset output• when we get 0, go to B and output 0•When we get 1, go back to C to wait for 00 sequence
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Sequential logic networks
Example 1: STEP 2V. Sequential Network Design
State /Output Table:
CS NS X=0 X= 1
A B AB B CC D C
Output
0
0
1
0
11 A,0 B,0
0
C,1
1
D,1 00
1
D B C 1
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Sequential logic networks
Example 1: STEP 3V. Sequential Network Design
State /Output Table:
CS NS X=0 X= 1
A B AB B CC D C
Output
0
0
1D B C 1
Reduce the number of states in STATE/OUTPUT table:
NO Redundant states in example 1
Output does notDepend on input X
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Sequential logic networks
Example 1: STEP 4V. Sequential Network Design
State Assignment: Encode the different states
There are 3 states We need two States Variable y1 and y0• y1 is the leftmost bit (Flip flop 1)• y0 is the rightmost bit (Flip flop 0)
One possible state assignment:A 00, B 01, C 10 : State code 11 is not used (don’t cares …)
There are many more state assignments:
For example, We could use the following assignments
A 11, B 10, C 01 : State code 00 is not used (don’t cares …)A 10, B 11, C 00 : State code 01 is not used (don’t cares …)
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Sequential logic networks
Example 1: STEP 5V. Sequential Network Design
Substitute State Codes in the State/output table
State assignment:A 00, B 01, C 10
State/Output table (Mealy Machine)
CS NS X=0 X= 1
00 01 0001 01 1010 01 10
Output X=0 X= 1
0 0
0 1
1 1
11 dd dd d d
CS NS X=0 X= 1
A B AB B CC B C
Output X=0 X= 1
0 0 0 1
1 1
Unused state code
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Sequential logic networks
Example 1: STEP 6V. Sequential Network Design
Flip Flop Next State MapsState/Output table (Mealy Machine)
CS NS X=0 X= 1
00 0 1 0 001 0 1 1 010 0 1 1 0
Output X=0 X= 1
0 0
0 1
1 1
11 d d d d d d
(y1y0) X 0 1
00 0 0 01 0 1 10 0 111 d d
Current Next state Y1Flip flop 1
(y1y0) X 0 1
00 1 0 01 1 0 10 1 011 d d
Current Next state Y0Flip flop 0
Flip flop Next state maps
y1 (flip flop 1)
y0 (flip flop 0)
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Sequential logic networks
Example 1: STEP 7V. Sequential Network Design
Flip Flop Excitation Maps•Determine transitions of flip flop •For each transition, give the input that cause the transition (Depends on the type of flip flops)
Assume JK flip flop for y1 and y0
(y1y0) X 0 1
0 0 0 0 0 1 0 1 1 0 0 11 1 d d
Current Next state Y1Flip flop 1 (J1, K1)
Next transition for X=0 and X=1
0 0 0 d 0 d 0 1 0 d 1 d1 0 d 1 d 0 1 1 d d d d
(y1y0) X
0 1
Current Next state Y1Flip flop 1 (J1, K1)
J1 K1 J1 K1
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Sequential logic networks
Example 1: STEP 7V. Sequential Network Design
Flip Flop Excitation Maps
Assume JK flip flop for y1 and y0
Next transition for X=0 and X=1
0 0 1 d 0 d 0 1 d 0 d 11 0 1 d 0 d 1 1 d d d d
(y1y0) X
0 1
Current Next state Y0Flip flop 0 (J0, K0)
J0 K0 J0 K0(y1y0) X 0 1
00 1 0 01 1 0 10 1 011 d d
Current Next state Y0Flip flop 0
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Sequential logic networks
Example 1: STEP 8V. Sequential Network Design
Flip Flop Excitation Equations (Input circuits of flip flops)
• Derive K- Maps from excitation maps• Use K-maps to derive flip flop input equations
(y1y0) X
0 1
0 0 0 d 0 d 0 1 0 d 1 d1 0 d 1 d 0 1 1 d d d d
Current Next state Y1Flip flop 1 (J1, K1)
J1 K1 J1 K1
K1 input
J1 input
y1y0X 0100 11 10
0
1
J1
0 0 d d0 1 d d
J1 = x•y0
y1y0X 0100 11 10
0
1
K1
d d d 1 d d d 0
K1 = x’
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Sequential logic networks
Example 1: STEP 8V. Sequential Network Design
Flip Flop Excitation Equations (Input circuits of flip flops)
• Derive K- Maps from excitation maps• Use K-maps to derive flip flop input equations
y1y0X 0100 11 10
0
1
K0
d 0 d d d 1 d d
K0 = X
y1y0X 0100 11 10
0
1
J0
1 d d 10 d d 0
J0 = X’(y1y0) X
0 1
0 0 1 d 0 d 0 1 d 0 d 11 0 1 d 0 d 1 1 d d d d
Current Next state Y0Flip flop 0 (J0, K0)
J0 K0 J0 K0J0 input
K0 input
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Sequential logic networks
Example 1: STEP 9V. Sequential Network Design
Determine the output logic circuit
State/Output table (Mealy Machine)
y1y0NS
X=0 X= 1
00 01 0001 01 1010 01 10
Output Z X=0 X= 1
0 0
0 1
1 1
11 dd dd d d
y1y0X 0100 11 10
0
1
Z
0 0 d 1 0 1 d 1
Z = y1 + x•y0
K-map of output Z
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Sequential logic networks
Example 1: STEP 10V. Sequential Network Design
Draw the circuit: (Flip flops and logic gates)
X
CLK
y1J1 Q
K1
y0
J0 Q
K0
Input circuit
Memory components
Output circuit
OR Z
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Sequential logic networks
HomeworkV. Sequential Network Design
Design the 01 sequence detector as a Moore machine. The ouput is reset0 when a 00 sequence is detected.
Design the detectector using:• clocked JK flip flops • clocked D flip flops
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Sequential logic networks
Example 2 V. Sequential Network Design
Give the state diagram of a clocked sequential circuit that recognizes the input sequence 1010, including overlapping.
For example, for the input sequence X = 00101001010101110, the corresponding output Z is Z = 00000100001010000
State diagram (Moore Machine):
0 A,0 B,0 C,0 D,0
1 0
E,1
1 0
1
1
01
0
Overlapping
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Sequential logic networks
Example 3V. Sequential Network Design
Design a Moore synchronous sequential circuit to detect a string of of three or more consecutive 1’s in an arbitrary input string.
Design the detectector using:• clocked JK flip flops • clocked D flip flops
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Sequential logic networks
Example 4V. Sequential Network Design
Using D flip flops, design a Moore synchronous sequential comparator circuit to determine which of the two multi-bits binary numbers X and Y (of equal Length) is larger. The comparison is carried out from left (Most Significant Bit) to right. Both MSB are used as input to the circuit. Assume two outputs Z1Z2 such that:Z1 = 1 if X > YZ2 = 1 if X < YZ1= Z2 = 0 if X = Y
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Sequential logic networks
Example 5V. Sequential Network Design
Design a two-bit clocked sequential counter circuit that counts clock pulses.
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Sequential logic networks
Design examples
Example1Give the state diagram of a clocked sequential circuit that recognizes the input sequence 1010, including overlapping. For example, for the input sequence
X = 00101001010101110, the corresponding output Z is Z = 00000100001010000
Example2Design a Moore synchronous sequential circuit to detect a string of of three or more consecutive 1’s in an arbitrary input string. Design the detectector using:• clocked JK flip flops • clocked D flip flops
Example3Using D flip flops, design a Moore synchronous sequential comparator circuit to determine which of the two multi-bits binary numbers X and Y (of equal Length) is larger. The comparison is carried out from left (Most Significant Bit) to right. Both MSB are used as input to the circuit. Assume two outputs Z1Z2 such that:Z1 = 1 if X > YZ2 = 1 if X < YZ1= Z2 = 0 if X = Y
Example4Design a two-bit clocked sequential counter circuit that counts clock pulses.