Digital Design: Sequential logic, Latches and Flip-Flops Part - II

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Chapter 14 Sequential logic, Latches Sequential logic, Latches and Flip and Flip - - Flops Flops

Transcript of Digital Design: Sequential logic, Latches and Flip-Flops Part - II

Page 1: Digital Design: Sequential logic, Latches and Flip-Flops Part - II

Chapter 14

Sequential logic, Latches Sequential logic, Latches and Flipand Flip--FlopsFlops

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Lesson 2

Sequential logic circuit, Flip Flop and Latch— Introduction

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Outline

•• Sequential logic circuit Sequential logic circuit • Clock input• Propagation delay, and Setup and hold

times • Flip Flop• Latch

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Example— Basic unit of Combinational Circuits

• Gates• Mux• decoder• PROM• PAL (unregistered)

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Example— Basic Sequential Circuits

• FF — SR, JK, D, T• Latch• Counter• Register

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Sequential Action

• Sequential action means (i) to remember what steps are to be done next, and (ii) to recall which step has just been finished

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Definition

• A sequential circuit is a circuit made up by combining logic gates such that the required logic at the output(s) depends not only on the current input logic conditions but also on the past inputs, outputs and sequences.

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Sequential Circuit State Table• Sequential circuit has a state table (like

truth table in a combinational circuit)• Sequences are specified by a table

called state table. • State table gives the past, current and

future states at the output.

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Sequential Circuit Features

• Sequential circuit has a feedback of the output(s) from a stage to the input of either that stage or any previous stage

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Sequential Circuit Features• An output depends on the current input

state and past input state (thus past output state)

• An output(s) can remain stable (constant) even after the input conditions change

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Sequential circuit feature

• An output(s) at each stage appears after a delay of few tens or hundred ns depending upon the gate type or family of used to implement the circuit

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Outline

• Sequential logic circuit • Clock input• Propagation delay, and Setup and hold

times • Flip Flop• Latch

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Sequential Circuit Features

• A sequential circuit may have a clock (gate) input to control the instance or time interval in which the output gets affected as per the inputs to the sequential circuit and in which the output undergoes transition to next state

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Clock Input

• Input after which the state at output(s) of sequential circuit undergoes transition to next state

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Clock Input

• Asynchronous input (Level clocking) — A time interval defined by clock input during which input changes reflect on the output

• Level means 1 for a time interval or 0 for a time interval

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Clock Input

• Synchronous input — (i) Edge +ve or –ve defines the instance at which input affects the output and transition is to next state (ii) Master slave —at +ve edge at master section of circuit, there is transition at master’s output and at –ve edge, the slave output undergoes transition as per master output.

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+ ve edge and -ve edge

• + edge means transition at input from 0 to 1

• - edge means transition at input from 0 to 1

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Outline

• Sequential logic circuit• Clock input• Propagation delay, and Setup and hold

times • Flip Flop• Latch

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Propagation Delay 0 to 1 transition

• Propagation delay, tp (01) or tpLH is the time interval between t’ and t’’, where t’ is the instance midway between 0 and 1 when a sequential circuit input is changing from 0 to 1 and t’’ is the instance midway between 0 and 1 when an output Q is changing from 0 to 1

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Propagation Delay 1 to 0 transition

• Propagation delay, tp (10) or tpHL is the time interval between t’’’ and t’’’’, where t’’’ is the instance midway between 1 and 0 when an input is changing from 1 to 0 and t’’’’ is the instance midway between 1 and 0 when the output Q is changing from 1 to 0

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Average Propagation Delay

• Average propagation delay, tp of a latch or FF is the average of tp (01) and tp (10). [The delays tp(01), tp(10) and tp differs due to different impedances of the output stage transistor.] These also depend on the types and family of the gates used in designing an FF

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Setup Time

• Setup time, ts is an average of the minimum required time for input before enabling input (gate input or clock input) is applied so that the output Q is as per sequential circuit design and its state table.

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Hold Time

• Hold time, th is an average of the minimum required time for input to hold its logic state unchanged after an enabling input (gate input or clock input) is applied so that the output Q is as per the circuit design and its state table.

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Outline

• Sequential logic circuit• Clock input• Propagation delay, and Setup and hold

times • Flip Flop• Latch

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FF

• Flip-Flop means a digital circuit of two stable states at an output:

1 means, rise on top. It means Flip, and0 means fall to ground. It means flop• Stable state can change only after a

clock input applies

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FF output Q along with its complement Q

• A particular combination of Q and Q represents a stable state.

• An FF is also called a bistable digital circuit. One of the stable state is Q = 1 and Q = 0, and other stable state is Q= 0 and Q = 1.

• An FF has one or two inputs and clock edge. The logic states at these inputs and the previous Q determine what shall be the current outputs

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FF

• FF can have two definite (discrete) states.

• FF forms a smallest basic memory unit or a one-bit register unit

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Present state feedbacks for next state

• Interconnections as well feedbacks are inputs

• Feedbacks are from outputs, Q and/or Q• Logic states at these inputs and the previous

Q determine what shall be the current outputs

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State table of flip-flop (FF)

• Describes how for the different input present and past conditions, the output Q (and/or Q) shall be in given of FF after a clocking instance

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FF• A flip-flop has a feature that output

should change only at a well defined instance of control input, called clock edge input.

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Outline

• Sequential logic circuit• Clock input• Propagation delay, and Setup and hold

times • Flip Flop•• LatchLatch

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Latch• A flip-flop is called latch, if the instance at

which output should change has no well defined instances clock input.

• A latch is FF without no edge triggered clocking mechanism for its inputs

• A latch may have a gating input (clock input interval) during which input changes affect changes in Q.

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Summary

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• Sequential circuit output state depends not only on present input but on past state also.

• For a sequential circuit, there is propagation delay, setup time and hold time

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• FF is a bistable circuit in which a timing input (called clock transition or clock edge input) controls the instance after which the output changes to next

• A latch is a class of flip-flop in place of clock-edge instance at which output changes, a clock interval exists during which that output changes to next

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End of Lesson 2 on Sequential logic circuit, Flip

Flop and Latch— Introduction

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